JP2006079639A - Bus bridge - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus bridge for reading data required by a master without reading unnecessary data, when reading data from a target. <P>SOLUTION: The bus bridge connected to a primary bus and a secondary bud has a primary bus interface, a secondary bus interface, a data FIFO, and a register block. Relay information for indicating the number of pieces of data relayed by the bus bridge is recorded in the register block writable from the master. When reading data from the target, the primary bus interface or the secondary bus interface reads out data from the target until the quantity of data indicated by the relay information recorded in the register block is stored in the data FIFO. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a bus bridge that relays data between devices connected to different buses.

2. Description of the Related Art Conventionally, in a computer system and a personal computer incorporated in information equipment, a bus bridge is provided between buses for the purpose of expanding the system and absorbing bus speed, bus width, and the like.
(Conventional bus bridge configuration)
FIG. 22 is a block diagram of a conventional bus bridge.

As seen in the figure, the bus bridge 10 includes a primary bus interface 11, a secondary bus interface 12, a bus arbiter 13, a configuration register 14, and a data FIFO 15.
The primary bus interface 11 functions as a primary bus interface capable of burst transfer and further controls the data FIFO 15.

The secondary bus interface 12 functions as a secondary bus interface capable of burst transfer, and further controls the data FIFO 15.
Here, the primary bus and the secondary bus are, for example, PCI (Peripheral Component) which is an address / data multiplexer type 32-bit bus.
Interconnect) bus.

The bus arbiter 13 is between the bus bridge 10 and the master of the secondary bus.
Arbitrate the right to use the secondary bus.
Here, the master is also referred to as an alias, a bus master, and refers to a device that drives a bus address line, designates a device to which data is transferred, and sends a bus command. In addition, in a certain data transfer, a device that functions only as a master is explicitly called an initiator.

The configuration register 14 holds setting information for determining the basic operation of the bus bridge 10. For setting information, PCI-PCI
Based on the format described in the PCI-to-PCI Bridge Architecture Specification.
The data FIFO 15 further includes a downstream data FIFO 16 (hereinafter referred to as a DS data FIFO 16), and an upstream data FIFO 17
(Hereinafter referred to as US data FIFO 17).

The DS data FIFO 16 holds an address of a bus cycle, a bus command, a byte enable bit, data, and the like generated from the primary bus initiator to the secondary bus target. When the bus bridge 10 generates a bus cycle as an initiator of the secondary bus, the stored address, bus command, byte enable bit, data, and the like are driven to the secondary bus.

Here, the target refers to a device that receives an address and a bus command, decodes the received address and bus command, and responds.
The US data FIFO 17 holds an address of a bus cycle, a bus command, a byte enable bit, data, and the like generated from the secondary bus initiator to the primary bus target. When the bus bridge 10 generates a bus cycle as an initiator of the primary bus, the stored address, bus command, byte enable bit, data, and the like are driven to the primary bus.

The read data transaction in the bus bridge 10 is performed until data of a predetermined size (for example, 8 entries) is stored in the data FIFO 15.
Read data from the target. It is assumed that addresses, bus commands, byte enable bits, etc. are not counted as entries.
Here, 1 entry is 4 bytes (32 bits), and 8 entries are 32
Points to a byte.
JP 2000-207354 A JP 2000-066993 A JP-A-10-254817 JP 05-173933 A JP 05-002557 A

However, the bus bridge 10 may read data that the initiator does not need from the target in the read data transaction.
For example, even when the initiator needs data of 2 entries, the bus bridge 10 reads data of 8 entries from the target.
As a result, the bus bridge 10 has a problem that the period of occupying the target-side bus is increased by reading unnecessary data.

The present invention has been made in view of the above-described problems. When reading data from a target in a read data transaction, the data required by the initiator is read without reading unnecessary data. It is an object of the present invention to provide a bus bridge, a data relay method using the bus bridge, a program for forming the bus bridge in a programmable device, and a recording medium capable of capturing the programmable device in which the program is recorded.

In the bus bridge according to the present invention, a device that is a supply destination of data to be relayed is a master, a device that is a supply source of data to be relayed is a target, and data between a master and a target that are connected to different buses is stored. A storage bridge for relaying, which is a bus bridge for relaying, recording relay information indicating an amount of data to be relayed in an internal storage area writable from the outside, and storage means for storing data read from the target in a temporary storage area; Until the amount of data indicated in the relay information recorded in the internal storage area is stored in the temporary storage area, the bus to which the target is connected is occupied and data is continuously read out. When data is stored, control means for releasing the occupied bus is provided.

Furthermore, a plurality of devices that can be either masters or targets are connected to the plurality of buses connected to the bus bridge, and the internal storage area is
A primary partial storage area corresponding to each bus, the recording means records the relay information in a primary partial storage area corresponding to the bus to which the target is connected, and the control means is a master corresponding to each bus. Each master function unit including a function unit may read out from the target the amount of data indicated in the relay information recorded in the primary partial storage area corresponding to the bus to which the target is connected.

Further, the primary partial storage area corresponding to a bus to which a plurality of target devices can be connected includes a secondary partial storage area corresponding to each device that can be a target connected to the bus, and the recording The means records the relay information in a secondary partial storage area corresponding to a device that can be a target, and each master function unit has an amount indicated in the relay information recorded in the secondary partial storage area corresponding to the target. The data may be read from the target.

Furthermore, the secondary partial storage area corresponding to the bus to which a device that can be a plurality of targets is connected is for each device that can be a master that relays data read from the device that can be a target connected to the bus. The recording means records the relay information in a tertiary partial storage area corresponding to a device that can be a master, and each master function unit relays data read from the target The amount of data indicated in the relay information recorded in the tertiary partial storage area corresponding to the master may be read from the target.

Further, the recording means may record the relay information as a default in the internal storage area in an initial state and when the control means releases the bus.
Further, the relay information may be one of the number of data in units of the bus width bits and the total size of data to be relayed.
In addition, the bus bridge includes a response unit that responds to a request from the master, and the response unit includes: (a) when the request from the master is a write request to the internal storage area, The data to be written in the internal storage area is recorded as relay information in the recording means, and (b) if it is a read request to the target, is the data output to the master recorded in the temporary storage area? (B1) if recorded, output the recorded data to the master, and (b2) if not recorded, request the read request again. It is also possible to notify the master and cause the control means to read out data to be output to the master.

Furthermore, a plurality of devices that can be either masters or targets are connected to the plurality of buses connected to the bus bridge, and identification information for identifying the devices is assigned to each device, and the internal storage The area includes an identification information storage area, the recording means records the identification information in the identification information storage area, the response means further responds to a request from the device, and a request from the device is received. (C) When the request is a write request to the identification information storage area, the data written in the identification information storage area is recorded as identification information in the recording means, and (d) is recorded in the identification information storage area. Data to be output from the bus bridge to the device corresponding to the identification information in the case of a write request to the device corresponding to the identification information. , As the relay information may be is recorded in the recording means.

In addition, the bus bridge includes a first bus to which a central processing unit as a master and an internal storage device as a target are connected, and a second bus to which a plurality of devices as masters and targets are connected. The internal storage area is connected to a first primary partial storage area in which relay information indicating the amount of data read from the target connected to the first bus is recorded, and to the second bus. A second primary partial storage area in which relay information indicating the amount of data to be read from the target is recorded, and the temporary storage area is a first temporary storage in which data read from the target of the second bus is recorded An area and a second temporary storage area in which data read from the target of the first bus is recorded, the recording means connected to the first primary partial storage area, A first selector that selects relay information recorded in the first primary partial storage area; and a second selector that is connected to the second primary partial storage area and selects relay information recorded in the second primary partial storage area. A bus arbiter that outputs to the first selector a control signal for selecting relay information corresponding to a device that can be a master of the second bus, and a device that can be a target of the second bus. And an address decoder that outputs a control signal for selecting corresponding relay information to the second selector, and the control means uses the first selector among relay information recorded in the first primary partial storage area. Data is read from the target connected to the first bus until the amount of data indicated in the selected relay information is recorded in the first temporary storage area Of the relay information recorded in the first master function unit and the second primary partial storage area, the amount of data indicated by the relay information selected by the second selector is stored in the second temporary storage area. Until the second
A second master function unit that reads data from a target connected to the bus.

The data relay method according to the present invention includes a master that is a device to which data to be relayed is supplied, a target that is a device that is a source of data to be relayed, and a master and a target that are connected to different buses. A data relay method for relaying data between the master, the relay information indicating the amount of data relayed to the master from the master to the bus bridge, and a read request for the target from the master When the data to be output to the master is stored in the bus bridge in the step of passing to the bus bridge, the stored data is transferred from the bus bridge to the master,
If it is not stored, it occupies the bus to which the target is connected until the amount of data indicated in the relay information passed to the bus bridge is stored, continuously reads the data, And the step of releasing the occupied bus.

Furthermore, a bus that relays data between a master that is a device to which data to be relayed is supplied, a target that is a device that is a source of data to be relayed, and a master and a target that are connected to different buses. A method of relaying data to and from a bridge, the step of passing a request for relaying supply information indicating the amount of data supplied from the target to the master from a device other than the master to the bus bridge; The supply information is duplicated, and the duplicated supply information is used as relay information indicating the amount of data read from the target.
A step of recording, a step of passing a read request to the target from the master to the bus bridge, and data stored in the bus bridge when the data to be output to the master is stored. If it is not stored and passed from the bridge to the master, it continuously occupies the bus to which the target is connected until the amount of data indicated in the relay information recorded in the bus bridge is stored. Then, when the data is read and the amount of data is stored, a step of releasing the occupied bus may be included.

The program according to the present invention relays data between a master and a target connected to different buses, with a device that is a supply destination of data to be relayed as a master and a device that is a supply source of data to be relayed as a target. A program for forming a bus bridge in a programmable device, a recording block for recording relay information indicating the amount of data to be relayed in an externally writable internal storage area, and data read from the target in a temporary storage area Until the amount of data indicated in the storage block to be stored and the relay information recorded in the internal storage area is stored in the temporary storage area, the bus connected to the target is occupied and data is continuously recorded. When the amount of data is stored, the control block that releases the occupied bus And to form a click into a programmable device.

Further, the program causes a programmable device to form a response block that responds to a request from the master, and the response block is configured such that the request from the master is (a) a write request to the internal storage area. The data to be written in the internal storage area is recorded in the recording block as relay information, and (b) if it is a read request to the target, the data to be output to the master is recorded in the temporary storage area. (B1) If recorded, output the recorded data to the master. (B2) If not recorded, request the read request again. To the master,
Data to be output to the master may be read by the control block.

A programmable device-capable recording medium according to the present invention has a master device that is a destination of data to be relayed as a master, a device that is a source of data to be relayed as a target, and a master and a target that are connected to different buses. Programmable device recording medium that records a program that allows a programmable device to form a bus bridge that relays data between them, and records relay information indicating the amount of data to be relayed in an externally writable internal storage area A storage block for storing data read from the target in a temporary storage area, and until the amount of data indicated in the relay information recorded in the internal storage area is stored in the temporary storage area, Occupies the bus to which the target is connected, and To read out data, when the amount of data is stored, and a control block which releases the bus occupying records a program to be formed into a programmable device.

Further, the recording medium records a program that causes a programmable device to form a response block that responds to a request from the master, and the response block includes:
When the request from the master is (a) a write request to the internal storage area, the data written to the internal storage area is recorded as relay information in the recording block, and (b) to the target If it is a read request, it is determined whether or not the data to be output to the master is recorded in the temporary storage area. (B1) If it is recorded, the recorded data is stored in the master. (B2) If not recorded, the master may be notified that the read request is requested again, and the control block may be made to read the data to be output to the master.

In the bus bridge according to the present invention, a device that is a supply destination of data to be relayed is a master, a device that is a supply source of data to be relayed is a target, and data between a master and a target that are connected to different buses is stored. A storage bridge for relaying, which is a bus bridge for relaying, recording relay information indicating an amount of data to be relayed in an internal storage area writable from the outside, and storage means for storing data read from the target in a temporary storage area; Until the amount of data indicated in the relay information recorded in the internal storage area is stored in the temporary storage area, the bus to which the target is connected is occupied and data is continuously read out. When data is stored, control means for releasing the occupied bus is provided.

Thus, in the read data transaction, before reading data from the target, the amount of data required by the master is written as relay information in the internal storage area, so that the data unnecessary by the master is read from the target, It becomes possible to read the amount of data required by the master. As a result, data that is not required by the master is not read from the target, so that the period of occupying the bus connected to the target is shortened.

Furthermore, a plurality of devices that can be either masters or targets are connected to the plurality of buses connected to the bus bridge, and the internal storage area is
A primary partial storage area corresponding to each bus, the recording means records the relay information in a primary partial storage area corresponding to the bus to which the target is connected, and the control means is a master corresponding to each bus. Each master function unit including a function unit may read out from the target the amount of data indicated in the relay information recorded in the primary partial storage area corresponding to the bus to which the target is connected.

As a result, each time the bus to which the target is connected changes, data can be efficiently relayed by writing the relay information once without writing it in the internal storage area. In addition, relay information optimized for each bus in advance,
By recording in the primary partial storage area corresponding to the bus, data can be relayed more efficiently.

Further, the primary partial storage area corresponding to a bus to which a plurality of target devices can be connected includes a secondary partial storage area corresponding to each device that can be a target connected to the bus, and the recording The means records the relay information in a secondary partial storage area corresponding to a device that can be a target, and each master function unit has an amount indicated in the relay information recorded in the secondary partial storage area corresponding to the target. The data may be read from the target.

As a result, each time a device that can be a target changes, data can be relayed efficiently by writing the relay information once without writing it in the internal storage area. In addition, it is possible to relay data more efficiently by previously recording relay information optimized for each device that can be a target in a secondary partial storage area corresponding to the device. There is.

Furthermore, the secondary partial storage area corresponding to the bus to which a device that can be a plurality of targets is connected is for each device that can be a master that relays data read from the device that can be a target connected to the bus. The recording means records the relay information in a tertiary partial storage area corresponding to a device that can be a master, and each master function unit relays data read from the target The amount of data indicated in the relay information recorded in the tertiary partial storage area corresponding to the master may be read from the target.

This makes it possible to relay data efficiently by writing the relay information once without changing the relay information to the internal storage area every time the device that can become the master changes. In addition, by previously recording the relay information optimized for each device that can be a master in the tertiary partial storage area corresponding to the device,
There is an effect that data can be relayed more efficiently.

Further, the recording means may record the relay information as a default in the internal storage area in an initial state and when the control means releases the bus.
As a result, there is an effect that the master can update the previously written relay information to the default value without writing the relay information.
Further, the relay information may be one of the number of data in units of the bus width bits and the total size of data to be relayed.

As a result, there is an effect that the amount of data required by the master can be read from the target based on the number of data in units of bus width or the total size of data to be relayed.
In addition, the bus bridge includes a response unit that responds to a request from the master, and the response unit includes: (a) when the request from the master is a write request to the internal storage area, The data to be written in the internal storage area is recorded as relay information in the recording means, and (b) if it is a read request to the target, is the data output to the master recorded in the temporary storage area? (B1) if recorded, output the recorded data to the master, and (b2) if not recorded, request the read request again. It is also possible to notify the master and cause the control means to read out data to be output to the master.

Thus, by issuing the relay information to the bus bridge together with a write request for the internal storage area, the relay information can be read from the target as the amount of data required by the master.
Furthermore, a plurality of devices that can be either masters or targets are connected to the plurality of buses connected to the bus bridge, and identification information for identifying the devices is assigned to each device, and the internal storage The area includes an identification information storage area, the recording means records the identification information in the identification information storage area, the response means further responds to a request from the device, and a request from the device is received. (C) When the request is a write request to the identification information storage area, the data written in the identification information storage area is recorded as identification information in the recording means, and (d) is recorded in the identification information storage area. Data to be output from the bus bridge to the device corresponding to the identification information in the case of a write request to the device corresponding to the identification information. , As the relay information may be is recorded in the recording means.

As a result, even in the master that cannot write the relay information in the internal storage area, the relay information is stored in the internal storage area by writing the relay information in the internal storage area in advance instead of a device other than the master (for example, the central processing unit). Even the master that cannot write to the area can read out the required amount of data from the target. Even if relay information is not written to the internal storage area for each device that can be a master, a plurality of relay information corresponding to the devices are managed in a specific device, and a plurality of relays are collectively performed from a specific device. By writing information in the internal storage area, there is an effect that data can be relayed more efficiently.

In addition, the bus bridge includes a first bus to which a central processing unit as a master and an internal storage device as a target are connected, and a second bus to which a plurality of devices as masters and targets are connected. The internal storage area is connected to a first primary partial storage area in which relay information indicating the amount of data read from the target connected to the first bus is recorded, and to the second bus. A second primary partial storage area in which relay information indicating the amount of data to be read from the target is recorded, and the temporary storage area is a first temporary storage in which data read from the target of the second bus is recorded An area and a second temporary storage area in which data read from the target of the first bus is recorded, the recording means connected to the first primary partial storage area, A first selector that selects relay information recorded in the first primary partial storage area; and a second selector that is connected to the second primary partial storage area and selects relay information recorded in the second primary partial storage area. A bus arbiter that outputs to the first selector a control signal for selecting relay information corresponding to a device that can be a master of the second bus, and a device that can be a target of the second bus. And an address decoder that outputs a control signal for selecting corresponding relay information to the second selector, and the control means uses the first selector among relay information recorded in the first primary partial storage area. Data is read from the target connected to the first bus until the amount of data indicated in the selected relay information is recorded in the first temporary storage area Of the relay information recorded in the first master function unit and the second primary partial storage area, the amount of data indicated by the relay information selected by the second selector is stored in the second temporary storage area. Until the second
A second master function unit that reads data from a target connected to the bus.

As a result, even if a plurality of relay information is recorded in the internal storage area, the relay information corresponding to the master, the relay information corresponding to the target, or the combination of the master and the target is combined by the bus arbiter and the address decoding. It becomes possible to select information. Then, based on the selected relay information, there is an effect that data required by the master can be read from the target.

The data relay method according to the present invention includes a master that is a device to which data to be relayed is supplied, a target that is a device that is a source of data to be relayed, and a master and a target that are connected to different buses. A data relay method for relaying data between the master, the relay information indicating the amount of data relayed to the master from the master to the bus bridge, and a read request for the target from the master When the data to be output to the master is stored in the bus bridge in the step of passing to the bus bridge, the stored data is transferred from the bus bridge to the master,
If it is not stored, it occupies the bus to which the target is connected until the amount of data indicated in the relay information passed to the bus bridge is stored, continuously reads the data, And the step of releasing the occupied bus.

Thus, in the read data transaction, before reading data from the target, the amount of data required by the master is written as relay information in the internal storage area, so that the data unnecessary by the master is read from the target, It becomes possible to read the amount of data required by the master. As a result, data that is not required by the master is not read from the target, so that the period of occupying the bus connected to the target is shortened.

Furthermore, a bus that relays data between a master that is a device to which data to be relayed is supplied, a target that is a device that is a source of data to be relayed, and a master and a target that are connected to different buses. A method of relaying data to and from a bridge, the step of passing a request for relaying supply information indicating the amount of data supplied from the target to the master from a device other than the master to the bus bridge; The supply information is duplicated, and the duplicated supply information is used as relay information indicating the amount of data read from the target.
A step of recording, a step of passing a read request to the target from the master to the bus bridge, and data stored in the bus bridge when the data to be output to the master is stored. If it is not stored and passed from the bridge to the master, it continuously occupies the bus to which the target is connected until the amount of data indicated in the relay information recorded in the bus bridge is stored. Then, when the data is read and the amount of data is stored, a step of releasing the occupied bus may be included.

As a result, even in the master that cannot write the relay information in the internal storage area, the relay information is stored in the internal storage area by writing the relay information in the internal storage area in advance instead of a device other than the master (for example, the central processing unit). Even the master that cannot write to the area can read out the required amount of data from the target. Even if relay information is not written to the internal storage area for each device that can be a master, a plurality of relay information corresponding to the devices are managed in a specific device, and a plurality of relays are collectively performed from a specific device. By writing information in the internal storage area, there is an effect that data can be relayed more efficiently.

The program according to the present invention relays data between a master and a target connected to different buses, with a device that is a supply destination of data to be relayed as a master and a device that is a supply source of data to be relayed as a target. A program for forming a bus bridge in a programmable device, a recording block for recording relay information indicating the amount of data to be relayed in an externally writable internal storage area, and data read from the target in a temporary storage area Until the amount of data indicated in the storage block to be stored and the relay information recorded in the internal storage area is stored in the temporary storage area, the bus connected to the target is occupied and data is continuously recorded. When the amount of data is stored, the control block that releases the occupied bus And to form a click into a programmable device.

As a result, programs obtained via recording media, networks, etc.
In general hardware such as a computer, if downloaded to a programmable device via a download cable, the downloaded programmable device needs the amount of data the master needs before reading data from the target in a read data transaction. As relay information, the amount of data required by the master can be read without reading out data unnecessary by the master from the target. As a result, data that is not required by the master is not read from the target, so that the period of occupying the bus connected to the target is shortened.

Further, the program causes a programmable device to form a response block that responds to a request from the master, and the response block is configured such that the request from the master is (a) a write request to the internal storage area. The data to be written in the internal storage area is recorded in the recording block as relay information, and (b) if it is a read request to the target, the data to be output to the master is recorded in the temporary storage area. (B1) If recorded, output the recorded data to the master. (B2) If not recorded, request the read request again. To the master,
Data to be output to the master may be read by the control block.

Thus, by issuing the relay information to the programmable device together with a write request for the internal storage area, the relay information can be read from the target as the amount of data required by the master.
A programmable device recording medium in which a program according to the present invention is recorded is connected to different buses, with a device serving as a data supply destination to be relayed as a master and a device serving as a data supply source to be relayed as a target. Programmable device recording medium that records a program that allows a programmable device to form a bus bridge that relays data between the master and target, and can internally write relay information indicating the amount of data to be relayed A recording block for recording in the storage area, a storage block for storing data read from the target in the temporary storage area, and an amount of data indicated in the relay information recorded in the internal storage area are stored in the temporary storage area Until the target is connected It occupies Rubasu read data continuously, when the amount of data is stored, and a control block which releases the bus occupying records a program to be formed into a programmable device.

Thus, if the program obtained via the recording medium is downloaded to a programmable device via a download cable in general hardware such as a computer, the downloaded programmable device is
Before reading data from the target in a read data transaction, the master needs the data that the master does not need to read from the target by writing the amount of data required by the master as relay information to the internal storage area. It is possible to read out the amount of data. As a result, data that is not required by the master is not read from the target, and the period of occupying the bus to which the target is connected is shortened.

Further, the recording medium records a program that causes a programmable device to form a response block that responds to a request from the master, and the response block includes:
When the request from the master is (a) a write request to the internal storage area, the data written to the internal storage area is recorded as relay information in the recording block, and (b) to the target If it is a read request, it is determined whether or not the data to be output to the master is recorded in the temporary storage area. (B1) If it is recorded, the recorded data is stored in the master. (B2) If not recorded, the master may be notified that the read request is requested again, and the control block may be made to read the data to be output to the master.

Thus, by issuing the relay information to the programmable device together with a write request for the internal storage area, the relay information can be read from the target as the amount of data required by the master.

(Embodiment 1)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected about the component same as the past, and the description is abbreviate | omitted.
(Bus bridge configuration)
FIG. 1 is a block diagram of a bus bridge according to the first embodiment.

As shown in the figure, the bus bridge 100 includes a primary bus interface 101 and a secondary bus interface 102 instead of the primary bus interface 11 and the secondary bus interface 12 as compared with the conventional bus bridge 10, and A register block 111 is provided.
The primary bus interface 101 is a primary bus interface 11.
In addition, the connection with the register block 111 is different. When the initiator of the secondary bus generates a read cycle for the target of the primary bus, the read cycle generated in the primary bus is controlled according to the relay information held in the register block 111.

Here, the relay information refers to the number of data transferred by the bus bridge 100.
The secondary bus interface 102 is connected to the secondary bus interface 12.
In addition, the connection with the register block 111 is different. When the initiator of the primary bus generates a read cycle for the target of the secondary bus, the read cycle generated in the secondary bus is controlled according to the relay information held in the register block 111.

The register block 111 holds relay information.
FIG. 2 is a detailed block diagram of the primary bus interface 101, the secondary bus interface 102, and the register block 111.
As seen in the figure, the primary bus interface 101 further includes a primary bus master 201, a primary bus target 202, and an address decoder 203.

The primary bus master 201 functions as a master for the primary bus. When data is read from the target of the primary bus, a read cycle is generated in the primary bus according to the relay information held in the register block 111.
The primary bus target 202 functions as a primary bus target.

The address decoder 203 refers to the configuration register 14 and identifies a device from the driven address together with the bus cycle generated in the primary bus. In addition, the address of the identified device is notified to the register block 111.
The secondary bus interface 102 further includes a secondary bus master 21.
1 and a secondary bus target 212.

The secondary bus master 211 functions as a master for the secondary bus. When data is read from the target of the secondary bus, a read cycle is generated in the secondary bus according to the relay information held in the register block 111.
The secondary bus target 212 functions as a target for the secondary bus.

The register block 111 further includes an address buffer 221 and a register 23.
1 and a register 241.
The address buffer 221 holds data (address) driven by the initiator of either the primary bus or the secondary bus together with the write cycle generated for the address buffer 221. Address decoder 2
03 and the register 231. If the data (address) held in the address buffer 221 matches the address notified from the address decoder 203, the data (relay information) driven with the write cycle following the matching address is displayed. The duplicated data is copied to the register 23.
Write to 1.

The register 231 holds data (relay information) driven by the initiator of either the primary bus or the secondary bus together with the write cycle generated for the register 231. And the secondary bus initiator
When a read cycle is generated for the primary bus target, the held data (relay information) is sent to the primary bus master 201.

The register 241 holds data (relay information) driven by the initiator of either the primary bus or the secondary bus together with the write cycle generated for the register 241. And the primary bus initiator
When a read cycle is generated for the secondary bus target, the held data (relay information) is sent to the secondary bus master 211.

(Configuration example of computer system provided with bus bridge 100)
FIG. 3 is a configuration diagram of a computer system including the bus bridge 100 as an example.
As seen in the figure, the computer system 300 includes a CPU 301 and a memory 302 connected to a primary bus, bus masters 303 and 304 and bus targets 305 and 306 connected to a secondary bus, a primary bus, And a bus bridge 100 connected to the secondary bus.

The CPU 301 functions as a primary bus master.
The memory 302 functions as a primary bus target.
The bus masters 303 and 304 function as a master for the secondary bus.
Further, the bus master 303 includes a register 311. Then, the data (relay information) driven together with the write cycle generated for the bus master 303 is stored in the register 311.

FIG. 4 is a diagram illustrating a memory map of addresses assigned to devices and registers in the computer system 300.
As seen in the figure, the memory map 400 shows a specific address or memory area in a 32-bit memory space in each row of the address column. In each row of the device and register column, each device or register associated with the same row address or memory area is shown. The address unit is Byte.
As shown in hexadecimal notation.

Hereinafter, in the computer system 300, the memory 302 has an address 000000.
00 to 3FFFFFFF is assigned, and bus target 305 has address 40000000 to 5FFF
FFFF is assigned. Bus target 306 addresses 60000000-7FFFFF
FF is assigned and address buffer 221 is assigned address 80000000. The register 231 is assigned an address 80000004, and the register 241 is assigned an address 8000000C. The register 311 has an address of 90
000000 is assigned.

(Bus bridge operation)
The operation of the bus bridge 100 configured as described above will be described.
(Data relay processing in the bus bridge 100)
FIG. 5 is a flowchart of data relay processing in the bus bridge 100.

As seen in the figure, the bus bridge 100 repeatedly executes the following processing until the bus bridge 100 is reset (step S501).
The bus bridge 100 determines whether or not a write cycle has occurred in the primary bus (step S502).
If it is determined that a write cycle has occurred, relay information storage processing is executed (step S503).

It is then determined whether a read cycle has occurred on the primary bus (
Step S504).
As a result of the determination, if a read cycle has occurred, a first read cycle response process is executed (step S505).
Also, it is determined whether or not a read cycle has occurred in the secondary bus (step S506).

As a result of the determination, if a read cycle has occurred, a second read cycle response process is executed (step S507).
(Relay information storage processing)
FIG. 6 is a flowchart of relay information storage processing in the bus bridge 100.

As seen in the figure, the primary bus target 202 determines the bus cycle generated in the primary bus from the address driven together with the write cycle (step S601).
As a result of the determination, if it is a write cycle for the register 241, the primary bus target 202 stores the data (relay information) driven together with the write cycle in the register 241 (step S602), and ends the relay information storage process. .

Alternatively, if it is a write cycle for the address buffer 221,
The primary bus target 202 stores the data (address) driven together with the write cycle in the address buffer 221 (step S603), and ends the relay information storage process.
Alternatively, in the case of a write cycle for a secondary bus device, the address buffer 221 determines whether the address notified from the address decoder 203 matches the data (address) held in the address buffer 221. Determination is made (step S604).

As a result of the determination, if they match, the address buffer 221 duplicates the data (relay information) driven with the write cycle, and stores the duplicated data in the register 231 (step S605). Further, the primary bus target 202 stores the address, command, byte enable bit, and data (relay information) in the DS data FIFO 16 (step S606).

Then, the secondary bus master 211 generates a write cycle for the secondary bus, drives the address and data (relay information) stored in the DS data FIFO 16 (step S607), and ends the relay information storage process.
(First read cycle response process)
FIG. 7 is a flowchart of the first read cycle response process in the bus bridge 100.

As shown in the figure, the primary bus target 202 determines whether the bus cycle generated in the primary bus is a read cycle for the target of the secondary bus from the address driven with the read cycle (step S701). .
As a result of the determination, if the read cycle is for the secondary bus target, the primary bus target 202 refers to the US data FIFO 17 to determine whether data to be transferred to the initiator that has generated the read cycle is prepared. Is determined (step S702).

If it is determined that the data to be transferred is prepared, the primary bus target 202 transfers the data stored in the US data FIFO 17 (
Step S703), the first read cycle response process is terminated. If the data to be transferred is not prepared, the primary bus target 202 stores the address driven together with the read cycle in the DS data FIFO 16 and responds with a retry to the initiator that has caused the read cycle (step). S704).

Then, the secondary bus master 211 receives the relay information from the register 241 and generates a read cycle for the secondary bus, and the DS data FIF
The address stored in O16 is driven to the secondary bus (step S
705).
Subsequently, the secondary bus master 211 reads data from the target,
The read data is stored in the US data FIFO 17 (step S706), and it is determined whether or not the number of data read from the target matches the received relay information (step S707).

If the determination results in a match, the secondary bus master 211 notifies the primary bus target 202 that the data to be transferred to the initiator that generated the read cycle is ready (step S708). 1 Read cycle response processing is terminated. If not, the process returns to step S706.

(Second read cycle response process)
FIG. 8 is a flowchart of the second read cycle response process in the bus bridge 100.
As shown in the figure, the secondary bus target 212 determines whether the bus cycle generated in the secondary bus is a read cycle for the target of the primary bus from the address driven with the read cycle (step S801). .

As a result of the determination, if the read cycle is for the target of the primary bus, the secondary bus target 212 refers to the DS data FIFO 16 and whether or not data to be transferred to the initiator that generated the read cycle is prepared. Is determined (step S802).
As a result of the determination, when the data to be transferred is prepared, the secondary bus target 212 transfers the data stored in the DS data FIFO 16 (
Step S803), the second read cycle response process is terminated. If the data to be transferred is not prepared, the secondary bus target 212 stores the address driven together with the read cycle in the US data FIFO 17, and responds with a retry to the initiator that generated the read cycle (step). S804).

The primary bus master 201 receives the relay information from the register 231, generates a read cycle for the primary bus, and uses the US data FIF.
The address stored in O17 is driven to the primary bus (step S
805).
Subsequently, the primary bus master 201 reads data from the target,
The read data is stored in the DS data FIFO 16 (step S806), and it is determined whether or not the number of data read from the target matches the received relay information (step S807).

If they match as a result of the determination, the primary bus master 201 notifies the secondary bus target 212 that the data to be transferred to the initiator that generated the read cycle is ready (step S808). 2 The read cycle response process is terminated. If not, the process returns to step S806.

The flowchart of the data relay process in the bus bridge 100 has been described above.
(Operation example)
Here, in the computer system 300 described below (case-1)
, (Case-2) as an example, the specific operation of the bus bridge 100 will be described with reference to a timing chart.

(Case-1) When data is transferred from the secondary bus target to the primary bus initiator (Case-2) When data is transferred from the primary bus target to the secondary bus initiator The data relay processing of the bus bridge 100 is referred to as upstream transfer processing, and the data relay processing of the bus bridge 100 in (Case-2) is referred to as downstream transfer processing.

(Upstream transfer processing)
First, specific operations of the upstream transfer process will be described with reference to a timing chart.
9 to 11 are timing charts in the upstream transfer process.

FIG. 9A is a timing chart relating to the primary bus from T0 to T8, and FIG. 9B is a timing chart relating to the primary bus from T7 to T15.
9A and 9B, a timing chart of the clock (CLK), the right to use the primary bus, the address / data, the phase, the read / write, and the bus response type is shown in order from the top. .

Here, the right to use refers to a device having the right to use the bus.
Here, the address / data refers to the state of the address / data line.
Here, the phase refers to a phase of a bus cycle such as “address”, “data”, “turn around”, “idle”, and the like.
Here, the bus response type is a bus bridge 10 such as “completion” or “retry”.
Refers to a bus response of zero.

FIG. 10A is a timing chart relating to the bus bridge 100 from T0 to T8, and FIG. 10B is a timing chart relating to the bus bridge 100 from T7 to T15.
As seen in FIGS. 10A and 10B, in order from the top, clock (CLK), register 333, US data FIFO 212 entry 1, US data FIFO 21
The timing chart of 2 entry 2 is shown.

11A is a timing chart relating to the secondary bus from T0 to T8, and FIG. 11B is a timing chart relating to the secondary bus from T7 to T15.
As seen in FIGS. 11A and 11B, the timing chart of the clock (CLK), the right to use the secondary bus, the address / data, the phase, the read / write, and the bus response type is shown in order from the top. .

The timing charts shown in FIGS. 9 to 11 are synchronized.
First, as seen in FIG. 9A, at T0 to T2, the CPU 301
Assert the primary bus, generate a write cycle, and address 80
00000C (address of register 241) and data 00000002 (relay information) are driven to the primary bus. Accordingly, the bus bridge 100 executes relay information storage processing. In T1 to T2, the CPU 301 deasserts the primary bus.

Here, assert means that the initiator occupies the bus and generates a read cycle or a write cycle.
Here, deassertion means that the read cycle or write cycle generated by the initiator is terminated with the next clock, and the occupied bus is released.

Subsequently, as shown in FIG. 10A, in T2 to T3, the bus bridge 100 determines that the data 00000002 (relay information) driven together with the write cycle.
Is stored in the register 241.
Here, the bus bridge 100 registers the register 241 in step S601.
Is determined to be a write cycle, step S602 is executed, and the relay information storage process is terminated.

Subsequently, as seen in FIG. 9A, in T3 to T6, the CPU 301 asserts the primary bus, generates a read cycle, and addresses
Drive 40000000 (address of bus target 305) to the primary bus. Accordingly, the bus bridge 100 executes the first read cycle response process. Then, the CPU 301 receives a retry from the bus bridge 100 as a response to the read cycle. In T5 to T6, the CPU 3
01 deasserts the primary bus.

Here, the bus bridge 100 determines in step S701 that it is a read cycle for the secondary bus target (bus target 305), and executes step S702. In step S702, it is determined that data to be transferred is not prepared, and step S704 is executed.
Subsequently, as seen in FIGS. 11 (a) and 11 (b), at T5 to T9, the bus bridge 100 asserts the secondary bus, generates a read cycle, and also stores the address (stored in the DS data FIFO 16). Address 40000000)
To the secondary bus. The bus bridge 100 then receives data 01234567 and data 89AB from the secondary bus target (bus target 305).
Lead CDEF. In T8 to T9, the bus bridge 100 deasserts the secondary bus.

Subsequently, as seen in FIG. 10B, at T8 to T10, the bus bridge 100 stores the read data 01234567 in the first entry of the US data FIFO 17, and the data 89ABCDEF in the second entry of the US data FIFO 17. To do.
Here, the bus bridge 100 determines in step S707 that the number of data read from the target and the received relay information are determined to match.
Steps S705 and S706 are executed, and the first read cycle response process is terminated.

Subsequently, as seen in FIG. 9B, in T9 to T13, the CPU 301
Asserts the primary bus, generates a read cycle again,
Address 40000000 (address of bus target 305) is driven to the primary bus. Accordingly, the bus bridge 100 executes the first read cycle response process again. Then, the CPU 301 reads data 01234567 and data 89ABCDEF from the bus bridge 100 (the first entry and the second entry of the US data FIFO 17). In T12 to T13, the CPU 301
Deassert the primary bus.

Here, the bus bridge 100 determines in step S701 that it is a read cycle for the secondary bus target (bus target 305), and executes step S702. In step S702, it is determined that data to be transferred is prepared, step S703 is executed, and the first read cycle response process is terminated.

The above is the operation of the bus bridge 100 by the upstream transfer process.
(Downstream transfer processing)
Next, a specific operation of the downstream transfer process will be described with reference to a timing chart.

12 to 14 are timing charts in the downstream transfer process.
FIG. 12A is a timing chart relating to the primary bus from T0 to T9, and FIG. 12B is a timing chart relating to the primary bus from T9 to T20.
As can be seen from FIGS. 12A and 12B, a timing chart of the clock (CLK), primary bus use right, address / data, phase, read / write, and bus response type is shown in order from the top.

FIG. 13A is a diagram illustrating a timing chart between the bus bridge 100 and the register 311 from T0 to T9, and FIG. 13B from T9 to T20.
As shown in FIGS. 13A and 13B, in order from the top, the clock (CLK), the address buffer 221, the register 241, the first entry of the DS data FIFO 16, the second entry of the DS data FIFO 16, and the timing of the register 231. A chart is shown.

14A is a timing chart relating to the secondary bus from T0 to T12, and FIG. 14B is a timing chart relating to the secondary bus from T12 to T20.
As seen in FIGS. 14A and 14B, a timing chart of the clock (CLK), secondary bus usage right, address / data, phase, read / write, and bus response type is shown in order from the top.

Note that the timing charts shown in FIGS. 12 to 14 are synchronized.
First, as seen in FIG. 12A, at T0 to T2, the CPU 301 asserts the primary bus, generates a write cycle, and addresses
80000000 (address of address buffer 221) and data 90000000 (register 3)
11 address) to the primary bus. Accordingly, the bus bridge 100 executes relay information storage processing. In T1 to T2, C
The PU 301 deasserts the primary bus.

Subsequently, as shown in FIG. 13A, in T <b> 1 to T <b> 2, the bus bridge 100 stores data 90000000 (address of the register 311) driven together with the write cycle in the address buffer 221.
Here, the bus bridge 100 determines in step S601 that it is a write cycle for the address buffer 221, and executes step S603.
The relay information storage process ends.

Subsequently, as seen in FIG. 12A, in T3 to T5, the CPU 301
Asserts the primary bus, generates a write cycle, and drives address 90000000 (address of register 311) and data 00000002 (relay information) to the primary bus. Accordingly, the bus bridge 100 executes relay information storage processing. In T4 to T5, the CPU 301 deasserts the primary bus.

Subsequently, as shown in FIG. 13A, in T5 to T6, the bus bridge 100 receives data 00000002 (relay information) driven together with the write cycle.
Is stored in the DS data FIFO 16. Also, the data 00000002 (relay information) driven with the write cycle is duplicated, and the duplicated data is stored in the register 231.
To remember.

Here, the bus bridge 100 determines in step S601 that it is a write cycle for the device of the secondary bus, and executes step S604. Subsequently, in step S604, it is determined that they match, and step S605 is determined.
Execute. Then, Step S606 is executed.
Subsequently, as seen in FIG. 14A, at T5 to T7, the bus bridge 100 asserts the secondary bus and generates a write cycle.
Address 90000000 (address of register 311) and data 00000002 (relay information)
And drive to the secondary bus. In T6 to T7, the bus bridge 100 deasserts the secondary bus.

Subsequently, as seen in FIG. 13A, at T7 to T8, the bus master 3
03 is the data 000000 driven to the secondary bus along with the write cycle
02 is stored in the register 311.
Here, the bus bridge 100 executes step S607 and ends the relay information storage process.

Subsequently, as seen in FIG. 14A, in T8 to T11, the bus master 303 asserts the primary bus and generates a read cycle.
Address 20000000 (partial address of memory 302) is driven to the secondary bus. Accordingly, the bus bridge 100 executes the second read cycle response process. As a response to the read cycle, the bus master 303
A retry is received from the bus bridge 100. In T10 to T11, the bus master 303 deasserts the secondary bus.

Here, the bus bridge 100 determines in step S801 that it is a read cycle for the primary bus target (memory 302), and executes step S802. In step S802, it is determined that data to be transferred is not prepared, and step S804 is executed.
Subsequently, as seen in FIG. 12B, at T10 to T14, the bus bridge 100 asserts the primary bus to generate a read cycle, and at the same time, the address 20000000 (memory 302) stored in the US data FIFO 17
To the primary bus. And bus bridge 10
0 reads data 01234567 and data 89ABCDEF from the target (memory 302) of the primary bus. Further, at T13 to T14, the bus bridge 10
0 deasserts the primary bus.

Subsequently, as seen in FIG. 13B, at T13 to T15, the bus bridge 100 stores the read data 01234567 in the first entry of the DS data FIFO 16, and the data 89ABCDEF is the second entry of the DS data FIFO 16. To store.
Here, the bus bridge 100 determines in step S807 that the number of data read from the target and the received relay information match.
Steps S805 and S806 are executed, and the second read cycle response process is terminated.

Subsequently, as seen in FIG. 14B, in T15 to T19, the bus master 303 asserts the secondary bus, generates a read cycle again, and sends the address 20000000 (partial address of the memory 302) to the secondary bus. Drive to. Accordingly, the bus bridge 100 executes the second read cycle response process again. The bus master 303 then sends the bus bridge 100 (
From the first entry and the second entry of the DS data FIFO 16), the data 012345
Lead 67 and data 89ABCDEF. In T18 to T19, the bus master 303 deasserts the secondary bus.

Here, the bus bridge 100 determines in step S801 that it is a read cycle for the primary bus target (memory 302), and executes step S802. In step S802, it is determined that data to be transferred is prepared, step S803 is executed, and the second read cycle response process is terminated.

The above is the operation of the bus bridge 100 by the downstream transfer process.
(Contrast with conventional bus bridge)
Here, the conventional bus bridge 10 and the bus bridge 100 are compared.
As an example, in the computer system 300, the bus bridge 100 is used.
A timing chart in the case where a bus bridge 10 is provided instead of FIG.

15 to 16 are timing charts in upstream transfer processing by the conventional bus bridge 10.
FIG. 15A is a timing chart relating to the primary bus to which the bus bridge 10 from T5 to T13 is connected.

As can be seen from FIGS. 15A and 15B, a timing chart of the clock (CLK), the right to use the primary bus, the address / data, the phase, the read / write, and the bus response type is shown in order from the top. .
FIG. 16A is a diagram illustrating a timing chart relating to the secondary bus to which the bus bridge 10 from T0 to T8 is connected, and FIG.

As seen in FIGS. 16A and 16B, a timing chart of the clock (CLK), the right to use the secondary bus, the address / data, the phase, the read / write, and the bus response type is shown in order from the top. .
The timing charts shown in FIGS. 15 to 16 are synchronized.
First, as seen in FIG. 15A, at T0 to T3, the CPU 31
Assert the primary bus, generate a read cycle, and address 40
Drive 000000 (the address of the bus target 35) to the primary bus. Accordingly, the bus bridge 10 stores an address, a bus command, a byte enable bit, and the like in the DS data FIFO 16. Then, the CPU 31 receives a retry as a response to the read cycle from the bus bridge 10. Further, at T2 to T3, the primary bus is deasserted.

Here, the bus bridge 10 refers to the US data FIFO 17, determines that the data to be transferred is not prepared, and responds with a retry to the read cycle.
During this time, as seen in FIGS. 16A and 16B, in T1 to T11, the bus bridge 10 asserts the secondary bus, generates a read cycle, and also has an address 40000000 (stored in the DS data FIFO 16). The address of the bus target 305 is driven to the secondary bus. Then, from the bus target 35, data 01234567, 89ABCDEF, 12345678, 9ABCDEF0, 23
Read 456789, ABCDEF01, 3456789A, BCDEF012, and read the read data to US
Store in the data FIFO 17. In T11-12, the secondary bus is deasserted.

During this time, as seen in FIG.
Asserts the primary bus, generates a read cycle again,
Address 40000000 (address of bus target 34) is driven to the primary bus. Then, data 01234567 and data 89ABCDEF are read from the bus bridge 10. In T9 to T10, the CPU 301 deasserts the primary bus.

As described above, when the bus bridge 10 and the bus bridge 100 are compared, FIGS.
6, the bus bridge 10 transfers data of two entries to the CPU 301.
When data is transferred to the bus target, 8-entry data is read from the bus target. On the other hand, as shown in FIGS. 9 to 11, the bus bridge 100 only reads the 2-entry data from the bus target when transferring the 2-entry data to the CPU 301. As a result, it can be seen that the bus bridge 100 is shorter during the period of occupying the target-side bus.

(Embodiment 2)
Embodiment 2 of the present invention will be described below with reference to the drawings. In addition,
The same components and operations as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 17 is a block diagram of a bus bridge according to the second embodiment.

As seen in the figure, the bus bridge 120 has a primary bus interface 101 and a bus arbiter 1 as compared with the bus bridge 100 in the first embodiment.
3 and the primary bus interface 1 instead of the register block 111
21, a bus arbiter 123, and a register block 131.
FIG. 18 shows the primary bus interface 121 and the register block 13.
1 is a detailed block diagram of FIG.

As seen in the figure, the primary bus interface 121 includes an address decoder 206 instead of the address decoder 203.
The register block 131 includes registers 251 to 262 associated with each device of the secondary bus, and a selector 271 that selects an output of those registers.
, 272.

The registers 251 to 262 hold data (relay information) driven by the initiator of either the primary bus or the secondary bus together with the write cycle generated for each register. And the registers 251 and 25
2 is connected to the selector 271, respectively, and holds the data stored in the selector 27.
Output to 1. In addition, the registers 261 and 262 are connected to the selector 272 and output the held data to the selector 272.

The selector 271 includes the registers 251 and 252 and the primary bus master 20.
1 is connected. Then, according to the control signal output from the bus arbiter 103, one of the outputs of the registers 251 and 252 is selected and output to the primary bus master 201.
The selector 272 includes the registers 261 and 262 and the secondary bus master 21.
1 is connected. Then, according to the control signal output from the address decoder 206, one of the outputs of the registers 261 and 262 is selected and output to the secondary bus master 211.

The address decoder 206 further outputs a control signal to the selector 272.
The relay information output to the secondary bus master 211 is controlled in accordance with the address driven with the read cycle (target address of the secondary bus).
The bus arbiter 123 further outputs a control signal to the selector 271. Then, the relay information output to the primary bus master 201 is controlled according to the initiator having the right to use the secondary bus.

The register 251 is assigned an address 80000004, and the register 252 is assigned an address 80000008. The register 261 is assigned an address 8000000C, and the register 262 is assigned an address 80000010.
(Operation of the bus bridge 120)
The operation of the bus bridge 120 configured as described above will be described.

(Data relay processing in the bus bridge 120)
FIG. 19 is a flowchart of data relay processing in the bus bridge 120.
As shown in the figure, the data relay process 1900 is compared with the data relay process 500 in the relay information storage process (step S503), the first read cycle response process (step S505), and the second read cycle response process ( Step S507)
The relay information storage process (step S1903), the first read cycle response process (step S1905), and the second read cycle response process (step S1907) are executed instead of.

The relay information storage process (step S1903) is the relay information storage process (step S1).
503), instead of step S602, the data (relay information) driven together with the write cycle is stored in the register 261 when it is a write cycle for the register 261, and is the write cycle for the register 262 Is stored in the register 262.

(First read cycle response process)
FIG. 20 is a flowchart of the first read cycle response process in the bus bridge 120.
As can be seen from the figure, the first read cycle response process (step S1905).
Compared with the first read cycle response process (step S505), step S7
Instead of 05, the following steps S2001 to S2004 are executed.

The address decoder 206 executes the following processing according to the address driven with the read cycle (step S2001).
If the address driven with the read cycle is the address of the bus target 305, the address decoder 206 outputs a control signal for selecting the output of the register 261 to the selector 272 (step S2002). Alternatively, if it is the address of the bus target 306, the address decoder 20
6 outputs a control signal for selecting the output of the register 262 to the selector 272 (step S2003).

The secondary bus master 211 receives the relay information output from the selector 272, generates a read cycle for the secondary bus, and drives the address stored in the DS data FIFO 16 to the secondary bus (
Step S2004).
(Second read cycle response process)
FIG. 21 is a flowchart of the second read cycle response process in the bus bridge 120.

As can be seen from the figure, the second read cycle response process (step S1907).
Compared with the second read cycle response process (step S507), step S8 is performed.
Instead of 05, the following steps S2101 to S2104 are executed.
The bus arbiter 123 executes the following process according to the initiator having the right to use the secondary bus (step S2101).

If the initiator having the right to use the secondary bus is the bus master 303, the bus arbiter 123 outputs a control signal for selecting the output of the register 251 to the selector 271 (step S2102). Alternatively, in the case of the bus master 304, the bus arbiter 123 outputs a control signal for selecting the output of the register 252 to the selector 271 (step S2103).

The primary bus master 201 receives the relay information output from the selector 271, generates a read cycle for the primary bus, and drives the address stored in the US data FIFO 17 to the primary bus (
Step S2104).
The flowchart of the data relay process in the bus bridge 120 has been described above.

(Other)
Note that default relay information (for example, 8 entries) may be recorded in all the registers constituting the register block in the initial state and when data is read from the target and the read cycle is completed.
Note that the register block 111 may include a register for each master or for each target.

The total number of targets connected to the i-th bus of the bus bridge connected to a plurality of buses is T [i], and the total number of masters connected to the i-th bus is M [i]. The total number of devices that can become masters among all devices connected to the bus bridge is M, and R [i], which is the number of registers corresponding to the i-th bus, is expressed by the following (formula-1) It may be based on.

(Formula-1) R [i] = (M−M [i]) × T [i] (i = 1, 2,...)
The bus bridge may be formed as a full custom LSI (Large Scale Integration) or VHDL (Very high speed integrated circuit).
It is described in ASIC (Application Specific I / F) by a program described in a hardware description language (Hardware Description Language) such as it Hardware Description Language) / Verilog-HDL.
ntegrated Circuit) Semi-custom LSI, FPGA (Field Programma)
It may be formed in a programmable device such as a ble Gate Array) / CPDL (Complex Programmable Logic Device). Further, it may be formed by a net list logically synthesized from an HDL program.

In addition, an HDL program or a netlist is stored in an optical recording medium (for example, a CD
-ROM), magnetic recording medium (eg, hard disk), magneto-optical recording medium (eg, MO), semiconductor memory (eg, ROM), etc. The computer may download to the programmable device via a download cable. In addition, an HDL program or a netlist is recorded on a computer-readable recording medium such as a hard disk provided on general hardware such as a computer connected via a network, and then transmitted via a transmission path such as a network. In another computer read in this manner, the program may be downloaded to the programmable device via a download cable. HD
The data synthesized from the L program is recorded in the serial ROM, and the FPG
You may download directly to A.

  The bus bridge according to the present invention is used in the information industry field as a device for relaying data between devices connected to different buses in a computer system incorporated in information equipment.

2 is a block diagram of a bus bridge in the first embodiment. FIG. 2 is a detailed block diagram of a primary bus interface 101, a secondary bus interface 102, and a register block 111. FIG. FIG. 1 is a configuration diagram of a computer system including a bus bridge 100 as an example. As an example, it is a diagram showing a memory map of addresses assigned to devices and registers in the computer system 300. FIG. 3 is a flowchart of data relay processing in the bus bridge 100. 5 is a flowchart of relay information storage processing in the bus bridge 100. 3 is a flowchart of first read cycle response processing in the bus bridge 100. 4 is a flowchart of second read cycle response processing in the bus bridge 100. (A) is a figure from T0 to T8, (b) is a figure which shows the timing chart regarding the primary bus from T7 to T15. (A) is a figure from T0 to T8, (b) is a figure which shows the timing chart regarding the bus bridge 100 from T7 to T15. (A) is a figure from T0 to T8, (b) is a figure which shows the timing chart regarding the secondary bus from T7 to T15. (A) is a figure from T0 to T9, (b) is a figure which shows the timing chart regarding the primary bus from T9 to T20. (A) is a figure from T0 to T9, (b) is a diagram showing a timing chart between the bus bridge 100 and the register 311 from T9 to T20. (A) is a figure from T0 to T12, (b) is a figure which shows the timing chart regarding the secondary bus from T12 to T20. (A) is a figure from T0 to T8, (b) is a figure which shows the timing chart regarding the primary bus from T5 to T13. (A) is a figure from T0 to T8, (b) is a figure which shows the timing chart regarding the secondary bus to T5-T13. FIG. 6 is a block diagram of a bus bridge in the second embodiment. 3 is a detailed block diagram of a primary bus interface 121 and a register block 131. FIG. 5 is a flowchart of data relay processing in the bus bridge 120. 5 is a flowchart of first read cycle response processing in the bus bridge 120. 10 is a flowchart of second read cycle response processing in the bus bridge 120. It is a block diagram of the conventional bus bridge.

Explanation of symbols

100 bus bridge 101 primary bus interface 102 secondary bus interface 104 configuration register 111 register block 201 primary bus master 202 primary bus target 203 address decoder 211 secondary bus master 212 secondary bus target 221 address buffer 231 241 register 301 CPU
302 Memory 303, 304 Bus Master 305, 306 Bus Target 311 Register 10 Bus Bridge 11 Primary Bus Interface 12 Secondary Bus Interface 13 Bus Arbiter 14 Configuration Register 15 Data FIFO
16 DS data FIFO
17 US Data FIFO

Claims (15)

A bus bridge that relays data between a master and a target that are connected to different buses, with a device that is a supply destination of data to be relayed as a master, a device that is a supply source of data to be relayed as a target,
Recording means for recording relay information indicating the amount of data to be relayed in an externally writable internal storage area;
Storage means for storing data read from the target in a temporary storage area;
Until the amount of data indicated in the relay information recorded in the internal storage area is stored in the temporary storage area, the bus to which the target is connected is occupied and data is continuously read out. A bus bridge comprising: control means for releasing an occupied bus when data is stored. The buses connected to the bus bridge are connected to a plurality of devices that can be either masters or targets,
The internal storage area includes a primary partial storage area corresponding to each bus,
The recording means includes
Record the relay information in the primary partial storage area corresponding to the bus to which the target is connected,
The control means includes a master function unit corresponding to each bus,
Each master function section
The bus bridge according to claim 1, wherein the amount of data indicated in the relay information recorded in the primary partial storage area corresponding to the bus to which the target is connected is read from the target. A primary partial storage area corresponding to a bus to which a device that can be a plurality of targets is connected,
A secondary partial storage area corresponding to each device that can be a target connected to the bus,
The recording means includes
Record the relay information in a secondary partial storage area corresponding to a device that can be a target,
Each master function section
The bus bridge according to claim 2, wherein the amount of data indicated in the relay information recorded in the secondary partial storage area corresponding to the target is read from the target. A secondary partial storage area corresponding to a bus to which a device that can be a plurality of targets is connected,
A tertiary partial storage area corresponding to each device that can be a master that relays data read from a device that can be a target connected to the bus,
The recording means includes
Record the relay information in the tertiary partial storage area corresponding to the device that can be the master,
Each master function section
The bus bridge according to claim 2 or 3, wherein the amount of data indicated in the relay information recorded in the tertiary partial storage area corresponding to the master to which the data read from the target is relayed is read from the target. . The recording means includes
2. The bus bridge according to claim 1, wherein default relay information is recorded in the internal storage area in an initial state and when the bus is released by the control means. The relay information is
2. The bus bridge according to claim 1, wherein the bus bridge is one of the number of data in units of the number of bits of the bus width and the total size of data to be relayed. The bus bridge is
Response means for responding to a request from the master;
The response means receives a request from the master.
(a) If it is a write request to the internal storage area, the data written in the internal storage area is recorded as relay information in the recording means,
(b) If it is a read request to the target, determine whether the data to be output to the master is recorded in the temporary storage area, and (b1) if it is recorded, it is recorded. Output data to the master, (b2) if not recorded, notify the master to request the read request again,
The bus bridge according to claim 1, wherein the data output to the master is read by the control means. A plurality of devices that can be either masters or targets are connected to a plurality of buses connected to the bus bridge, and identification information for identifying the devices is assigned to each device,
The internal storage area includes an identification information storage area,
The recording means records the identification information in the identification information storage area;
The response means is further responsive to a request from the device,
The request from the device is
(c) If it is a write request to the identification information storage area, the data written in the identification information storage area is recorded as identification information in a recording means,
(d) In the case of a write request to the device corresponding to the identification information recorded in the identification information storage area, the data to be output from the bus bridge to the device corresponding to the identification information as relay information, recording means The bus bridge according to claim 7, wherein the bus bridge is recorded. The bus bridge is connected to a first bus to which a central processing unit as a master and an internal storage device as a target are connected, and a second bus to which a plurality of devices as masters and targets are connected. And
The internal storage area is
A first primary partial storage area in which relay information indicating the amount of data read from the target connected to the first bus is recorded;
A second primary partial storage area in which relay information indicating the amount of data to be read from the target connected to the second bus is recorded;
The temporary storage area is
A first temporary storage area in which data read from the target of the second bus is recorded;
A second temporary storage area in which data read from the target of the first bus is recorded,
The recording means includes
A first selector for connecting to the first primary partial storage area and selecting relay information recorded in the first primary partial storage area;
A second selector connected to the second primary partial storage area and selecting relay information recorded in the second primary partial storage area;
The bus bridge is
A bus arbiter that outputs to the first selector a control signal for selecting relay information corresponding to a device that can be a master of the second bus;
An address decoder for outputting a control signal for selecting relay information corresponding to a device that can be a target of the second bus to the second selector;
The control means includes
The relay information recorded in the first primary partial storage area is connected to the first bus until the amount of data indicated by the relay information selected by the first selector is recorded in the first temporary storage area. A first master function unit for reading data from the target
Until the amount of data indicated in the relay information selected by the second selector among the relay information recorded in the second primary partial storage area is stored in the second temporary storage area, The bus bridge according to claim 1, further comprising: a second master function unit that reads data from a connected target. A master that is a device to which data to be relayed is supplied;
A data relay method in a target that is a device serving as a source of data to be relayed and a bus bridge that relays data between a master and a target connected to different buses,
Passing relay information from the master to the bus bridge indicating the amount of data relayed to the master;
Passing a read request to the target from the master to the bus bridge;
In the bus bridge, when the data to be output to the master is stored, the stored data is passed from the bus bridge to the master, and when not stored, the data is passed to the bus bridge. Occupies the bus to which the target is connected until the amount of data indicated in the relay information is stored, reads data continuously, and releases the occupied bus when the amount of data is stored A data relay method comprising the steps of: A master that is a device to which data to be relayed is supplied;
A data relay method in a target that is a device serving as a source of data to be relayed and a bus bridge that relays data between a master and a target connected to different buses,
Passing a request for relaying supply information indicating the amount of data supplied from the target to the master from a device other than the master to the bus bridge;
In the bus bridge, the supply information is duplicated, and the duplicated supply information is recorded as relay information indicating the amount of data read from the target;
Passing a read request to the target from the master to the bus bridge;
In the bus bridge, when data to be output to the master is stored, the stored data is passed from the bus bridge to the master, and when not stored, the data is recorded in the bus bridge. Until the amount of data indicated in the relay information is stored, the bus connected to the target is occupied, data is continuously read, and when the amount of data is stored, the occupied bus is A data relay method comprising: releasing the data. The device that is the destination of the data to be relayed is the master, the device that is the source of the data to be relayed is the target, and the bus bridge that relays the data between the master and target that are connected to different buses is the programmable device A program to form,
A recording block that records relay information indicating the amount of data to be relayed in an internal storage area writable from the outside;
A storage block for storing data read from the target in a temporary storage area;
Until the amount of data indicated in the relay information recorded in the internal storage area is stored in the temporary storage area, the bus to which the target is connected is occupied and data is continuously read out. When data is stored, a program that causes a programmable device to form a control block that releases an occupied bus. The program is
Forming a response block in response to a request from the master in a programmable device;
The response block includes a request from the master,
(a) If it is a write request to the internal storage area, the data written to the internal storage area is recorded as relay information in the recording block,
(b) If it is a read request to the target, determine whether the data to be output to the master is recorded in the temporary storage area, and (b1) if it is recorded, it is recorded. Output data to the master, (b2) if not recorded, notify the master to request the read request again,
The program according to claim 12, wherein the control block is made to read data to be output to the master. The device that is the destination of the data to be relayed is the master, the device that is the source of the data to be relayed is the target, and the bus bridge that relays the data between the master and target that are connected to different buses is the programmable device A programmable device recording medium that records a program to be formed,
A recording block that records relay information indicating the amount of data to be relayed in an internal storage area writable from the outside;
A storage block for storing data read from the target in a temporary storage area;
Until the amount of data indicated in the relay information recorded in the internal storage area is stored in the temporary storage area, the bus to which the target is connected is occupied and data is continuously read out. When data is stored, a recording medium that records a program that causes a programmable device to form a control block that releases an occupied bus. The recording medium is
Record a program that causes the programmable device to form a response block in response to a request from the master,
The response block includes a request from the master,
(a) If it is a write request to the internal storage area, the data written to the internal storage area is recorded as relay information in the recording block,
(b) If it is a read request to the target, determine whether the data to be output to the master is recorded in the temporary storage area, and (b1) if it is recorded, it is recorded. Output data to the master, (b2) if not recorded, notify the master to request the read request again,
The recording medium according to claim 14, wherein data output to the master is read by the control block.

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