JP2006012159A - Semiconductor device and IC card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the security of information stored in a semiconductor device.
Power supply voltage supply wirings 5A and 5B for supplying a driving voltage to an integrated circuit of a semiconductor chip 3 are arranged so as to cover the main surface of the semiconductor chip 3, and information stored in the semiconductor chip 3 is analyzed. Therefore, if the wirings 5A and 5B are removed, the integrated circuit does not operate and information analysis cannot be performed. Further, a processing detection circuit for detecting processing of the wirings 5A and 5B is provided. When the processing detection circuit detects the processing of the wirings 5A and 5B, the integrated circuit is reset. Thereby, the security of the information stored in the semiconductor device can be improved.
[Selection] Figure 4

Description

  The present invention relates to a semiconductor device and IC (Integrated Circuit) card technology, and more particularly to a technology effective when applied to a security technology for information stored in a semiconductor device.

  The IC card investigated by the present inventors has a high security function in which the read / write of the memory is managed by the function of a built-in CPU (Central Processing Unit) and the card itself has encryption processing, and the storage capacity is magnetic. Since it is 30 to 100 times larger than a card, it is expected as an information storage medium in, for example, finance, distribution, medical care, transportation, transportation or education. A general IC card has a structure in which a recess is formed in a part of a plastic thin plate of the size of a business card, and a packaged semiconductor chip is embedded in the recess. A surface protective film made of an insulating material is formed on the uppermost layer of the semiconductor chip so as to entirely cover the main surface of the semiconductor chip. Further, wiring such as bus lines and control lines arranged on the main surface of the semiconductor chip is covered with multilayer wiring arranged on the upper layer.

A technique for improving the security of information of a semiconductor device is described in, for example, Japanese Patent Laid-Open No. 11-145401 (Patent Document 1), and covers the element on an element formed on a silicon substrate. The structure which provides a conductor layer in is disclosed.
Japanese Patent Laid-Open No. 11-145401

  However, the present inventors have found that the IC card security technology has the following problems.

  That is, there is a case in which the semiconductor device information can be analyzed by directly applying the analysis needle to the bus line or the signal line in a state where the semiconductor device is operated after the shield layer is completely removed by the chemical. There is. Further, although the bus lines and the signal lines are covered using a multilayer wiring technology, a gap that cannot be covered due to the layout of the power supply wiring is generated at the input port of a module or the like. There is a problem that information on the semiconductor device may be analyzed by applying an analysis needle through the gap.

  Therefore, an object of the present invention is to provide a technique capable of improving the security of information stored in a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, when a predetermined wiring arranged on an upper layer of a semiconductor chip is removed or cut, it becomes impossible to analyze information stored in the semiconductor chip.

  Further, the present invention provides a processing detection circuit for detecting processing of a predetermined wiring arranged in an upper layer of a semiconductor chip.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, the security of information stored in the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  In the drawings used in the present embodiment, hatching may be added even in a plan view for easy understanding of the drawings.

  In the present embodiment, a MIS • FET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MIS • FET is abbreviated as pMIS, and an n-channel type MIS • FET. Is abbreviated as nMIS.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is an overall plan view of an IC card (semiconductor device) according to the first embodiment. FIG. 2 is a sectional view taken along line X1-X1 in FIG.

  This IC card 1 is, for example, electronic money, credit card, mobile phone, pay satellite receiver, identification card, license, insurance card, electronic medical record, electronic ticket, etc., finance, distribution, medical care, transportation, transportation or It is used as various information storage media in education. The card body 1S of the IC card 1 is made of, for example, a flat rectangular plastic thin plate. The vertical and horizontal dimensions of the card body 1S are, for example, about 85.47 to 85.72 × 53.92 × 54.03 cm, and the thickness is, for example, about 0.68 to 1.84 mm.

  A part of the main surface side of the card body 1S is provided with an information storage area IMA having a substantially planar shape. In this information storage area IMA, a groove 2 is dug in the card body 1S, and a package 4 containing a semiconductor chip (hereinafter simply referred to as a chip) 3 is embedded in the groove 2 so as to be embedded. . The vertical and horizontal dimensions of the information storage area IMA are, for example, about 11.4 × 12.6 cm.

  The chip 3 is mounted on the package substrate 4a with its main surface (device forming surface) facing the bottom of the groove 2 and its back surface bonded to the package substrate 4a. As shown in FIG. 18, an integrated circuit including a logic circuit group 3b such as a memory circuit 3a and a CPU (Central Processing Unit) for controlling the operation of the memory circuit 3a is formed on the main surface of the chip 3. . The memory circuit 3a includes a nonvolatile memory element such as an EEPROM (Electric Erasable Programmable Read Only Memory), a flash memory, a mask ROM, and / or a memory element (first element) group such as a RAM (Random Access Memory). It consists of The electrodes of the integrated circuit formed on the chip 3 are drawn out by an external terminal BP such as a bonding pad provided on the main surface of the chip 3. The bonding pads are electrically connected to lands on the main surface of the package substrate 4a through bonding wires 4b made of, for example, gold (Au). The chip 3 and the bonding wire 4b are sealed with a sealing resin 4c made of, for example, an epoxy resin. The back surface of the package substrate 4 a, that is, the surface opposite to the mounting surface of the chip 3 faces the surface side of the IC card 1. On the back surface of the package substrate 4a, a plurality of electrodes electrically connected to the electrodes on the main surface of the package substrate 4a are provided, through which data can be exchanged to the chip 3 from the outside. Yes.

  However, the mounting method of the chip 3 is not limited to the one shown in FIG. 2, and a face-down bonding method as shown in FIG. 3, for example, may be adopted. That is, the bump electrode 4d is formed on the external terminal BP, and the bump 3 is formed on the main surface of the chip 3 with the main surface (device forming surface) of the chip 3 facing the package substrate 4a. A method of mounting the chip 3 on the package substrate 4a may be employed. The integrated circuit of the chip 3 is electrically connected to the wiring of the package substrate 4a through the external terminal BP and the bump electrode 4d.

  Next, FIG. 4 shows a plan view of the uppermost wiring layer on the main surface side of the chip 3 of FIG. 2 or FIG. A semiconductor substrate (hereinafter simply referred to as a substrate) 3S constituting the chip 3 is made of, for example, a small piece of p-type silicon (Si) single crystal having a planar square shape. In the first embodiment, as shown in FIG. 4, the bonding pads BPA to BPF are arranged near the outer periphery of the chip 3. Among these, the bonding pads BPA and BPB are integrally patterned and electrically connected to the power supply voltage wirings 5A and 5B, respectively. The bonding pad BPC is a terminal for inputting a clock signal, for example. The bonding pad BPD is a terminal for inputting a predetermined control signal, for example. Furthermore, the bonding pads BPE and BPF are terminals for sending and receiving input / output signals, for example.

  The power supply voltage wirings 5 </ b> A and 5 </ b> B are arranged so as to cover the main surface of the chip 3. That is, the power supply voltage wirings 5A and 5B are arranged so as to cover the integrated circuit (memory circuit 3a and logic circuit group 3b). The power supply voltage wiring 5 </ b> A is a wiring for supplying a low-potential-side power supply voltage (GND, for example, 0 V) to the integrated circuit formed on the chip 3. The power supply voltage wiring 5B is a wiring for supplying a power supply voltage (VCC, for example, 1.8V, 3.0V, 5.0V) on the high potential side to the integrated circuit formed on the chip 3. is there. The power supply voltage wirings 5A and 5B are formed in a comb-like shape in a plane so that the respective teeth mesh with each other in the same wiring layer. The adjacent interval between the power supply voltage wirings 5A and 5B adjacent to each other is arranged to be as narrow as possible. That is, the elements on the main surface of the chip 3 are covered with the power supply voltage wirings 5A and 5B without any gaps. For this reason, in order to analyze the information of the chip 3, even if the needle contact is attempted on the signal wirings below the power supply voltage wirings 5A and 5B, the needle contact is not possible because the power supply voltage wirings 5A and 5B are obstructed. . In addition, it is very difficult to observe the signal wirings and elements under the power supply voltage wirings 5A and 5B from the outside because they are blocked by the power supply voltage wirings 5A and 5B. That is, the power supply voltage wirings 5A and 5B have a function as a shield for protecting information. Therefore, in the structure as in the first embodiment, when analyzing the information of the chip 3, the power supply voltage wirings 5A and 5B must be removed, but the power supply voltage wirings 5A and 5B are Since the wiring supplies the operating voltage to the integrated circuit of the chip 3, if the wiring is removed, the power supply voltage is not supplied to the integrated circuit. As a result, the integrated circuit does not operate and the information stored in the chip 3 It is impossible to analyze. Therefore, it is possible to improve the security of information on the IC card 1.

FIG. 5 illustrates an essential part plan view of the element region on the main surface of the chip 3 of FIG. FIG. 6 shows a cross-sectional view taken along line X2-X2 of FIG. A field insulating film 6 is formed in the isolation region on the main surface of the substrate 3S. The field insulating film 6 is made of, for example, silicon oxide (SiO ₂ or the like) formed by a selective oxidation (LOCOS: Local Oxidization of Silicon) method. Instead of the field insulating film 6, a groove-type isolation part (SGI; Shallow Groove Isolation) may be formed. This groove type separation portion is formed by embedding an insulating film such as a silicon oxide film in a groove formed in the main surface of the substrate 3S. An active region is formed in a region surrounded by the field insulating film 6 and the groove-type isolation portion.

An n well and a p well PWL are formed from the main surface of the substrate 3S to a predetermined depth. The n well contains, for example, phosphorus (P) or arsenic (As), and the p well PWL contains, for example, boron (B) or boron difluoride (BF ₂ ). A pMIS (second element) Qp and a well power supply region NWP are arranged in the active region surrounded by the field insulating film 6 in the n-well region. The pMISQp and the well power supply region NWP are separated via the field insulating film 6.

The pMISQp includes a p-type semiconductor region 7a for a source, a p-type semiconductor region 7b for a drain, a gate insulating film 8, and a gate electrode 9. The p-type semiconductor regions 7a and 7b contain, for example, boron (B). The gate insulating film 8 is made of, for example, silicon oxide. However, the material of the gate insulating film 8 is not limited to this, and can be variously changed. For example, the gate insulating film 8 may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film 8 and the substrate 3S may be employed. Since the silicon oxynitride film has a higher effect of suppressing the generation of interface states in the film and reducing the number of electron traps compared to the silicon oxide film, the hot carrier resistance of the gate insulating film 8 can be improved. Resistance can be improved. In addition, since the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film, the use of the silicon oxynitride film causes a threshold value due to diffusion of impurities in the gate electrode material to the substrate 3S side. Voltage fluctuation can be suppressed. In order to form the silicon oxynitride film, for example, the substrate 3S may be heat-treated in a nitrogen-containing gas atmosphere such as NO, NO _2, or NH ₃ . Further, after the gate insulating film 8 made of silicon oxide is formed on the surface of the substrate 3S, the substrate 3S is heat-treated in the nitrogen-containing gas atmosphere described above, and nitrogen is segregated at the interface between the gate insulating film 8 and the substrate 3S. The same effect as above can be obtained. The gate electrode 9 is made of, for example, low resistance polycrystalline silicon. However, the present invention is not limited to this, and various modifications can be made. For example, a so-called polycide gate electrode structure in which a silicide layer such as cobalt silicide (CoSix) is provided on a low-resistance polycrystalline silicon film or a low-resistance multi-layer structure. A so-called polymetal gate electrode structure in which a metal film such as tungsten is provided on a crystalline silicon film via a barrier metal layer such as tungsten nitride (WN) may be employed. The well power supply region NWP is a power supply region for applying a back bias voltage to the n well, and contains, for example, phosphorus or arsenic at a higher concentration than the n well in the upper portion of the n well. Is formed.

  In the active region surrounded by the field insulating film 6 in the region of the p well PWL, an nMIS (second element) Qn and a well power supply region PWP are arranged. The nMISQn and the well power feeding region PWP are separated via the field insulating film 6.

  The nMISQn includes an n-type semiconductor region 10a for source, an n-type semiconductor region 10b for drain, a gate insulating film 8, and a gate electrode 9. The n-type semiconductor regions 10a and 10b contain, for example, phosphorus or arsenic. Since the structures of the gate insulating film 8 and the gate electrode 9 of nMISQn are the same as those described for pMISQp, description thereof is omitted. The gate electrode 9 of the pMISQp and the gate electrode 9 of the nMISQn are integrally patterned and electrically connected. The gate electrode 9 is an input of a CMIS inverter circuit composed of pMISQp and nMISQn. The well power supply region PWP is a power supply region for applying a back bias voltage to the p well PWL, and boron or boron difluoride, for example, has a higher concentration than the p well PWL above the p well PWL. It is formed by being contained in.

  An integrated circuit (memory circuit 3a and logic circuit group 3b) is configured by pMISQp and / or nMISQn.

  An interlayer insulating film 11a made of, for example, a silicon oxide film is deposited on the main surface of the substrate 3S. On the interlayer insulating film 11a, first layer wirings 12a to 12f made of a metal film such as aluminum (Al) or an aluminum alloy are formed. The first layer wiring 12a is electrically connected to the gate electrode 9 through a plug in the contact hole CNT. First-layer wiring 12b is electrically connected to p-type semiconductor region 7b and n-type semiconductor region 10b for drains of pMISQp and nMISQn through plug PL1 in contact hole CNT. That is, the first layer wiring 12b is an output of the CMIS inverter circuit. The first layer wiring 12c is electrically connected to the p-type semiconductor region 7a of pMISQp through a plug in the contact hole CNT. The first layer wiring 12d is electrically connected to the well power supply region NWP through a plug in the contact hole CNT. The first layer wiring 12e is electrically connected to the nMISQn n-type semiconductor region 10a through the plug PL1 in the contact hole CNT. The first layer wiring 12f is electrically connected to the well power supply region PWP through the plug PL1 in the contact hole CNT. The plug PL1 is made of a metal film such as aluminum, an aluminum alloy, or tungsten.

  Further, an interlayer insulating film 11b made of, for example, a silicon oxide film is deposited on the interlayer insulating film 11a, thereby covering the first layer wirings 12a to 12f. On the interlayer insulating film 11b, second layer wirings 13a to 13d made of a metal film such as aluminum or an aluminum alloy are formed. The second layer wiring 13a is electrically connected to the first layer wiring 12e through the plug PL2 in the through hole TH1 drilled in the interlayer insulating film 11b. The second layer wiring 13b is electrically connected to the first layer wiring 12b through the plug PL2 in the through hole TH1 drilled in the interlayer insulating film 11b. The second layer wiring 13c is electrically connected to the first layer wiring 12f through the plug PL2 in the through hole TH1 drilled in the interlayer insulating film 11b.

  Further, an interlayer insulating film 11c made of, for example, a silicon oxide film is deposited on the interlayer insulating film 11b, thereby covering the second layer wirings 13a to 13d. A third layer wiring 14 made of a metal film such as aluminum or an aluminum alloy is formed on the interlayer insulating film 11c. The third-layer wiring 14 forms the power supply voltage wirings 5A and 5B described above. In FIG. 6, a power supply voltage wiring 5B on the low potential side is illustrated. The third layer wiring 14 is electrically connected to the second layer wirings 13a and 13c through the plug PL3 in the through hole TH2. That is, the low-potential-side power supply voltage wiring 5A is electrically connected to the nMISQn source n-type semiconductor region 10a and the power supply region PWP. The high-potential-side power supply voltage wiring 5B is electrically connected to the p-type semiconductor region 7a for the source of pMISQp and the power supply region NWP. Further, a surface protective film 15 is deposited on the interlayer insulating film 11c. Here, the surface protective film 15 is configured by depositing, for example, an insulating film 15b made of a polyimide resin on an insulating film 15a made of a silicon nitride film formed by, for example, a plasma CVD (Chemical Vapor Deposition) method. Yes. The power supply voltage wirings 5A and 5B may be configured to supply a power supply voltage to the MIS • FET and well region near the lower portion thereof. In this case, when a part of the power supply voltage wiring 5A, 5B is cut or removed, the portion near the lower portion of the removed part and the wiring 5A, 5B that is no longer electrically connected to the bonding pads BPA, BPB. The power supply voltage is not supplied to the integrated circuits 3a and 3b, the integrated circuit does not operate, and the information stored in the chip 3 cannot be analyzed.

(Embodiment 2)
FIG. 7 shows a plan view of a modification of the chip 3 constituting the IC card according to another embodiment of the present invention.

  In the second embodiment, as shown in FIG. 7, the planar shape of the power supply voltage wirings 5A and 5B is a substantially ladder shape. That is, each of the power supply voltage wirings 5A and 5B extends in a direction intersecting with two wiring portions extending in parallel with each other in the vertical direction in FIG. 7, and has a predetermined length along the vertical direction in FIG. A plurality of wiring portions arranged at intervals are connected at their intersections.

  However, in the second embodiment, the power supply voltage wirings 5A and 5B are formed in different wiring layers via an interlayer insulating film. Here, the case where the high-potential-side power supply voltage wiring 5B is arranged above the low-potential-side power supply voltage wiring 5A is illustrated. Further, the planar positions of the wirings 5A and 5B are shifted so that a part of the power supply voltage wiring 5B is disposed in the gap between the power supply voltage wirings 5A. That is, also in the second embodiment, the elements on the main surface of the chip 3 are covered with the power supply voltage wirings 5A and 5B without any gaps. For this reason, in order to analyze the information of the chip 3, even if the needle contact is attempted on the signal wirings below the power supply voltage wirings 5A and 5B, the needle contact is not possible because the power supply voltage wirings 5A and 5B are obstructed. . In addition, it is very difficult to observe the signal wirings and elements under the power supply voltage wirings 5A and 5B from the outside because they are blocked by the power supply voltage wirings 5A and 5B. For this reason, also in the second embodiment, when analyzing the information of the chip 3, the power supply voltage wirings 5A and 5B must be removed. If so, the first embodiment has been described. For the same reason as described above, the integrated circuit does not operate, and the information stored in the chip 3 cannot be analyzed. Therefore, it is possible to improve the security of information on the IC card 1.

(Embodiment 3)
FIG. 8 shows a plan view of a modification of the chip 3 constituting the IC card according to another embodiment of the present invention.

  In the third embodiment, as shown in FIG. 8, the planar shape of the power supply voltage wirings 5A and 5B is a lattice shape. That is, each of the power supply voltage wirings 5A and 5B includes a plurality of wiring portions extending in parallel with each other in the vertical direction of FIG. 8 and a plurality of wiring portions extending in a direction intersecting with the wiring portions. It is configured by connecting with.

  Also in the third embodiment, the power supply voltage wirings 5A and 5B are formed in different wiring layers. Here, the case where the high-potential-side power supply voltage wiring 5B is arranged on the upper layer of the low-potential-side power supply voltage wiring 5A is illustrated. Also in the third embodiment, the planar positions of the wirings 5A and 5B are shifted so that a part of the power supply voltage wiring 5B is disposed in the gap between the power supply voltage wirings 5A. ing. Thereby, also in this Embodiment 3, it becomes possible to acquire the effect similar to the effect obtained in the said Embodiment 1,2.

(Embodiment 4)
FIG. 9 shows a plan view of a modification of the chip 3 constituting the IC card according to another embodiment of the present invention. FIG. 10 is a sectional view taken along line X3-X3 in FIG.

  In the fourth embodiment, as shown in FIG. 9, the power supply voltage wiring 5A on the low potential side is a solid wiring. That is, the power supply voltage wiring 5 </ b> A is formed in a planar rectangular shape so as to cover most of the main surface of the chip 3. Of course, the power supply voltage wiring 5B on the high potential side may be a solid wiring. Here, the power supply voltage wiring 5B on the high potential side is provided in a wiring layer below the power supply voltage wiring 5A on the low potential side. The high-potential-side power supply voltage wiring 5B is not a solid wiring because of the arrangement of the through-hole TH3 that pulls down the low-potential-side power supply voltage wiring 5A to the lower layer. It is considered as wiring.

  Also in this fourth embodiment, it is possible to obtain the same effect as in the first and second embodiments.

(Embodiment 5)
FIG. 11 shows a plan view of an example of a chip 3 constituting an IC card according to another embodiment of the present invention. A plurality of circuit blocks 16 </ b> A to 16 </ b> D are arranged on the main surface of the chip 3. In the circuit block 16A, a RAM (Random Access Memory) such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), or an FRAM (Ferroelectric Random Access Memory) is formed. In the circuit block 16B, for example, an EEPROM (Electric Erasable Programmable Read Only Memory) is formed. In the circuit block 16B, various types of information in the finance, distribution, medical care, transportation, transportation, education, etc. are stored. For example, a CPU (Central Processing Unit) is formed in the circuit block 16C. The operation of the integrated circuit in the chip 3 is controlled by the circuit block 16C. For example, a ROM (Read Only Memory) is formed in the circuit block 16D. Information such as a program necessary for the operation of the integrated circuit is stored in the circuit block 16D. A wiring region 17 is arranged between the adjacent circuit blocks 16A to 16D. In the wiring region 17, signal wirings such as bus wirings 18a and 18b and control signal wirings 18c to 18e are arranged. The bus wirings 18a and 18b are wirings constituted by a group of a plurality of signal wirings arranged adjacent to each other at almost equal intervals.

  In the fifth embodiment, the power supply voltage wirings 5A and 5B are arranged so as to partially cover the area LA indicated by the broken line of the wiring area 17. That is, the power supply voltage wirings 5A and 5B are partially arranged so as to cover signal wirings used for information analysis such as the bus wirings 18a and 18b and the control signal wirings 18c to 18e.

  Also in the fifth embodiment, as in the first to fourth embodiments, the power supply voltage wirings 5A and 5B must be removed for information analysis. Therefore, the integrated circuit does not operate and the information stored in the chip 3 cannot be analyzed. Therefore, it is possible to improve the security of information on the IC card 1.

  In the fifth embodiment, power supply voltage wirings 5A and 5B that function as shields may be partially arranged, and the other regions may be used for power supply voltages for the other circuit blocks 16A to 16D. It can be used as a wiring area or a signal wiring area. Therefore, even if the power supply voltage wirings 5A and 5B functioning as shields are arranged, the degree of freedom of wiring of the entire chip 3 can be secured.

(Embodiment 6)
FIG. 12 shows a plan view of an example of a chip 3 constituting an IC card according to another embodiment of the present invention. On the main surface of the chip 3, a plurality of circuit cells 19 are regularly arranged in the vertical and horizontal directions in FIG. A plurality of elements are arranged in the circuit cell 19.

  In the first to fifth embodiments, the technology for protecting the information on the chip 3 has been described on the assumption that the entire power supply voltage wirings 5A and 5B functioning as shields are removed. As a method of this, it is also conceivable to perform information analysis by partially removing the power supply voltage wirings 5A and 5B using an energy beam such as FIB (Focused Ion Beam). Therefore, in the sixth embodiment, as a measure for preventing information analysis by such partial processing, for example, a plurality of processing detection circuits 20 are arranged on the main surface of the chip 3.

  When the processing detection circuit 20 processes (completely cuts or partially cuts) the power supply voltage wirings 5A, 5B or the specific wiring formed on the chip 3 described in the first to fifth embodiments, Is detected, and the integrated circuit of the chip 3 is reset to prevent the integrated circuit from operating, thereby preventing information analysis. By disposing such a processing detection circuit 20, information analysis of the IC card 1 can be prevented, so that security can be improved.

  In the sixth embodiment, a plurality of the processing detection circuits 20 are irregularly distributed in the main surface of the chip 3. Thereby, it is possible to make it difficult to specify the position of the processing detection circuit 20 in the chip 3. That is, when performing information analysis on such a chip 3, it is conceivable to analyze the information in the chip 3 by destroying the processing detection circuit 20 and then removing the wiring functioning as the shield. If the processing detection circuits 20 are irregularly distributed and arranged, it becomes difficult to destroy the processing detection circuits 20, and the analysis of information can be made difficult. Thereby, it is possible to further improve the security of information of the chip 3. As will be described later, when the power supply voltage wirings 5A and 5B are processed (completely cut or partly cut), the processing detection circuit 20 detects the potential (or resistance) of the power supply voltage wirings 5A and 5B. ) Change is detected. That is, the processing detection circuit 20 is a detection circuit that detects processing of the wirings 5A and 5B.

  Next, FIG. 13 shows an example of a circuit diagram of the processing detection circuit 20. Here, even if one of the low-potential-side power supply voltage (GND) wiring 5A and the high-potential-side power supply voltage (VCC) wiring 5B is processed, it is processed by one processing detection circuit 20. The circuit configuration which can be detected is illustrated.

  The processing detection circuit 20 includes high resistances R1, R2, nMISQn1, pMISQp1, an inverter circuit INV1, a NOR circuit NR1, and an inverter circuit INV2. The processing detection circuit 20 is composed of elements in the circuit cell 19, and the elements are connected by wiring below the wiring layers of the power supply voltage wirings 5A and 5B to form a circuit. The wirings 5A and 5B for the power supply voltage are inputs to the machining detection circuit 20. Further, the power supply voltages VCC1 and GND1 which are drive voltages of the machining detection circuit 20 are supplied through a path different from the power supply voltage wirings 5A and 5B. Otherwise, if one of the power supply voltages 5A and 5B is cut, the machining detection circuit 20 itself does not operate, and the function as the detection circuit is not performed. Here, the power supply voltage GND1 is the same as the voltage applied to the low-potential-side power supply voltage wiring 5A (for example, about 0V), and the power-supply voltage VCC1 is the high-potential-side power supply voltage wiring. It is the same as the voltage applied to 5B (for example, about 1.8V, 3.0V, 5.0V).

  Note that the sleep terminal SLP is electrically connected to the gate electrode of pMISQp1 via the gate electrode of nMISQn1 and the inverter circuit INV3. When a “High (hereinafter simply referred to as H)” voltage is applied to the sleep terminal SLP, nMISQn1 and pMISQp1 are turned on, and the processing detection circuit 20 operates normally. On the other hand, when a “Low (hereinafter referred to simply as L)” voltage is applied to the sleep terminal SLP, the nMISQn1 and the pMISQp1 are turned off, and the processing detection circuit 20 enters the sleep state. Reference numerals N1 to N4 indicate nodes, and reference numeral OUT indicates an output of the processing detection circuit 20.

  FIG. 14 shows the potentials of the nodes N1 to N4 and the output OUT during each operation of the processing detection circuit 20 of FIG. Mode M1 indicates the normal operation of the machining detection circuit 20. That is, the wiring 5A, 5B is not processed. In this case, since the node N1 is “L”, the node N2 is “H”, and the node N3 is “L”, the node N4 of the output of the NOR circuit NR1 becomes “H” and is inverted by the inverter circuit INV2 to detect the processing. “L” is output to the output OUT of the circuit 20. In this case, the integrated circuit of the chip 3 is not reset.

  Mode M2 shows a case where the low-potential-side wiring 5A is not cut, but the high-potential-side wiring 5B is cut. In this case, since the node N2 becomes “L” and the node N3 becomes “H”, the node N4 of the output of the NOR circuit NR1 becomes “L”, is inverted by the inverter circuit INV2, and is output to the output OUT of the processing detection circuit 20 , “H” is output. As a result, the integrated circuit of the chip 3 is reset, the integrated circuit does not operate, and information analysis cannot be performed.

  Further, mode M3 shows a case where the high potential side wiring 5B is not cut, but the low potential side wiring 5A is cut. In this case, the node N1 becomes “H” and the node N4 of the output of the NOR circuit NR1 becomes “L”, so that it is inverted by the inverter circuit INV2 and “H” is output to the output OUT of the processing detection circuit 20 The As a result, similarly to the above, the integrated circuit of the chip 3 is reset, the integrated circuit does not operate, and information analysis cannot be performed.

  Next, FIG. 15 shows an example of the layout of the power supply voltage wirings 5A and 5B functioning as the shield. FIG. 16 is a sectional view taken along line X4-X4 of FIG. Here, the machining detection circuit 20 that inputs one of the wirings 5A and 5B is illustrated, but the machining detection circuit 20 that receives both the wirings 5A and 5B as described above may be used. good.

  In the sixth embodiment, each of the wirings 5A and 5B is configured by meandering so that one wiring covers the lower wiring 18. That is, each of the wirings 5A and 5B is configured with a single stroke so that the cut wirings are completely insulated from each other when cut. And although it does not specifically limit, the process detection circuit 20 is electrically connected to the terminal. If the wirings 5A and 5B are laid out in a frame shape or a lattice shape, the power supply voltage can be supplied from the others even if a part of them is cut, and the potential of the input to the processing detection circuit 50 becomes constant. Even if the wirings 5A and 5B are processed, the processing cannot be detected. On the other hand, in the sixth embodiment, when the wirings 5A and 5B are written in a single stroke so that a part of the wirings 5A and 5B is cut with an energy beam such as FIB in information analysis, a processing detection circuit The power supply voltage cannot be applied to the input 20 and the input potential of the machining detection circuit 20 changes. As a result, the processing detection by the processing detection circuit 20 as described above can be performed, and the information stored in the chip 3 cannot be analyzed.

  Here, although not particularly limited, a case where the wirings 5A and 5B are provided in different wiring layers via an interlayer insulating film is illustrated. That is, the wiring 5A is arranged on the upper layer of the wiring 5B. The wirings 5A and 5B have a planar layout that intersects each other. That is, since the lower layer wiring 18 is covered with the power supply voltage wirings 5A and 5B without a gap, the needle contact is applied to the lower layer wiring 18 of the power supply voltage wirings 5A and 5B in order to analyze the information of the chip 3. Even if an attempt is made, the contact with the power supply voltage wirings 5A and 5B is obstructed and the needle contact cannot be made. In addition, it is very difficult to observe the signal wirings and elements under the power supply voltage wirings 5A and 5B from the outside because they are blocked by the power supply voltage wirings 5A and 5B. For this reason, also in the sixth embodiment, when analyzing the information of the chip 3, the wirings 5A and 5B for the power supply voltage must be processed. If so, the processing detection circuit 20 detects them. As a result, the integrated circuit does not operate and the information stored in the chip 3 cannot be analyzed. Therefore, it is possible to improve the security of information on the IC card 1. The wiring 18 may be a desired signal wiring such as a bus wiring (including a control bus, a data bus or an address bus) or a control wiring.

  Further, the lower-layer processing detection circuit 20 may be covered with such meandering wirings 5A and 5B. In analyzing the information stored in the chip 3, it is conceivable to destroy the processing detection circuit 20 and then remove the wirings 5A and 5B to perform information analysis. However, the processing detection circuit 20 is connected to the wiring 5A as described above. , 5B, the wiring 5A, 5B must be cut to destroy the machining detection circuit 20, so that the machining of the wiring 5A, 5B is detected before the machining detection circuit 20 is broken. Information analysis can be prevented.

  Further, such a one-stroke writing configuration of the wirings 5A and 5B can be applied even when the processing detection circuit 20 is not provided. That is, if most of the main surface or only the wiring area of the chip 3 is covered with the one-stroke-shaped wirings 5A and 5B illustrated in FIG. 16 and part of the wirings 5A and 5B is cut, the integration of the chip 3 is performed. By preventing the power supply voltage from being supplied to the circuit and preventing the integrated circuit from operating, information analysis can be prevented.

  Further, the plane pattern of the wiring 5A and the plane pattern of the wiring 5B may be different from each other. Thereby, information analysis can be made more difficult.

  In the present embodiment, the case where the wirings 5A and 5B are provided in different wiring layers is illustrated, but as shown in FIG. 40, the wirings 5A and 5B are provided in the same wiring layer. Also good. Thereby, the same effect as the present embodiment can be obtained.

  Further, as shown in FIG. 40, by configuring the wiring 5A and the wiring 5B to have different plane patterns, the information analysis can be made more difficult.

  Also, a plurality of wiring layers in which the wirings 5A and 5B shown in FIG. 40 are provided in the same layer may be laminated. That is, the wirings 5A and 5B shown in FIG. 40 are provided in each of the plurality of wiring layers. In this case, it is possible to make information analysis more difficult by configuring the planar patterns of the wirings 5A and 5B of each wiring layer to be different between the wiring layers.

In addition, it is possible to make information analysis more difficult by stacking the wiring layer having the planar pattern of FIG. 15 and the wiring layer having the planar pattern of FIG.
Further, the wiring patterns of the wirings 5A and 5B shown in FIG. 40 may be provided in the wiring layer between the wiring layer of the wiring 5B and the wiring layer of the wiring 5A shown in FIG. In this case, by configuring the plane pattern of the wiring 5B shown in FIG. 15, the plane pattern of the wiring 5A shown in FIG. 15, and the wiring patterns of the wirings 5A and 5B shown in FIG. Can be more difficult.

(Embodiment 7)
In the sixth embodiment, the case where the paths of the power supply voltage wiring functioning as the machining detection wiring and the power supply voltage wiring supplying the driving voltage of the machining detection circuit are separated has been described. In the seventh embodiment, as shown in FIG. 17, the power supply voltages GND and VCC of the wirings 5A and 5B functioning as the processing detection wiring of one processing detection circuit 20 (20a to 20d) and the other processing detection circuit 20 (20a to 20a). The supply path with the power supply voltages GND1 and VCC1 for supplying the drive voltage 20d) is integrated. That is, the machining detection input wirings 5A and 5B of one machining detection circuit 20 are the driving voltage supply wirings 5A and 5B of the other machining detection circuit 20. Further, here, the case where the processing detection circuits 20a to 20d are arranged so as to draw a loop is illustrated.

  When analyzing the information of the IC card 1, the power supply voltages GND1 and VCC1 are disconnected (or the power supply voltages GND1 and VCC1 are not supplied), the processing detection circuit 20 is disabled, and then the wirings 5A and 5B are disconnected. Can be considered. Therefore, in the seventh embodiment, when the wiring for supplying the power supply voltages GND1 and VCC1 of one processing detection circuit 20 is cut (or so that the power supply voltages GND1 and VCC1 are not supplied), it is connected to the other processing detection circuit. 20 is configured to detect. For example, when the wiring for supplying the power supply voltages GND1 and VCC1 for driving the processing detection circuit 20b is cut so as not to operate, the processing detection circuit 20a detects it and prevents the integrated circuit of the chip 3 from operating. . For this reason, the information analysis as described above can be prevented, and the security of the IC card 1 can be further improved.

  Also in the seventh embodiment, the wiring 5A, 5B may have a meandering shape as shown in FIG. Thereby, if it is going to destroy the process detection circuit 20, the process detection circuit 20 detects it, and the integrated circuit of the chip | tip 3 cannot be operated, and information analysis can be prevented.

(Embodiment 8)
In the eighth embodiment, an example will be described in which a power supply voltage wiring having a shielding function and an active shield wiring are arranged at different positions in plan view. As will be described later, the active shield is a shield as described in the sixth and seventh embodiments.

  FIG. 19 is a plan view of the chip 3 constituting the semiconductor device of the eighth embodiment. The wirings 5A and 5B in FIG. 19 are power supply voltage wirings having the shielding function described in the first to fifth embodiments. In FIG. 19, the wirings 5A and 5B are formed in the same layer (uppermost wiring layer) as in the first embodiment. However, the wirings 5A and 5B may be formed in different layers as in the second embodiment. Further, the planar shape of the wirings 5A and 5B may be the shape described in the third and fourth embodiments.

  Further, FIG. 19 illustrates an example in which the wirings 5A and 5B are arranged so as to mainly cover a part of the main surface of the chip 3 (upper side of the chip 3 in FIG. 19) and are not arranged in the area LA. Has been. The region (second region) LA exemplifies a region where signal wirings used for information analysis such as the bus wirings 18a and 18b and the control signal wirings 18c to 18e are arranged as described above. In the eighth embodiment, an active shield wiring composed of the same wiring layer as the wirings 5A and 5B is arranged in this area LA. That is, an integrated circuit (memory circuit 3a and logic circuit group 3b) is formed by power supply voltage wirings 5A and 5B having a shielding function formed in a region other than the region LA and an active shield wiring formed in the region LA. ) Is covered.

  Note that the power supply voltage wirings 5A and 5B having a shielding function may be configured by the planar patterns and a plurality of wiring layers of the wirings 5A and 5B shown in the first to fifth embodiments, or the active shield wirings may be formed. The plane pattern of the active shield wirings 5A and 5B shown in the sixth embodiment and a plurality of wiring layers may be used. That is, the power supply voltage wiring having a shield function may be constituted by a single-layer wiring layer or a plurality of wiring layers, and the active shield wiring may be constituted by a single-layer wiring layer or a plurality of wiring layers. Good. Further, the power supply voltage wiring having the shield function and the active shield wiring have at least one wiring layer in the same layer, whereby the integrated circuit (the memory circuit 3a and the logic circuit) is formed in the same wiring layer. The circuit group 3b) can be arranged so as to cover it, and information analysis can be made more difficult.

  The active shield is a shield as described in the sixth and seventh embodiments. That is, as described in the sixth embodiment, the active shield detects when a specific wiring (active shielding wiring) constituting the active shield is processed (completely cut or partially cut). Thus, the shield has a function of preventing information analysis by resetting the integrated circuit of the chip 3 so that the integrated circuit cannot operate. Signal wirings used for information analysis such as bus wirings 18a and 18b and control signal wirings 18c to 18e in the area LA are protected by this active shield system. That is, when the active shield wiring is processed by FIB (Focused Ion Beam) or the like (completely or partly cut), the potential variation in the active shield wiring is detected, and for example, the detection signal is used as an integrated circuit of the chip 3. By inputting a detection signal to a control circuit that controls the whole, the reset signal of the integrated circuit of the chip 3 is activated, and the integrated circuit of the chip 3 is brought into a reset state or the like. As a result, the integrated circuit of the chip 3 does not operate and information analysis cannot be performed. The reset state is a state where the chip does not operate, that is, a locked state. However, what is important here is to prevent the integrated circuit of the chip 3 from operating when the active shield wiring is processed, and to limit the IC card to a so-called reset state. is not. For example, when the active shield wiring is processed, the integrated circuit of the chip 3 may be set to a dead mode in which it does not operate again. As a specific example, a fuse circuit is provided as an active shield system in the chip 3 and when the wiring for the active shield is processed, the fuse of the fuse circuit is automatically cut and integrated in the chip 3. The circuit may be destroyed so that it cannot operate again (hereinafter, the same applies to reset in other embodiments).

  The active shield wiring is disposed above the signal wiring such as the bus wirings 18a and 18b and the control signal wirings 18c to 18e via an interlayer insulating film. That is, the active shield wiring is arranged at a position where it must be processed (completely or partly cut) during information analysis through the signal wiring. As a result, in order to perform information analysis through the signal wiring, it is necessary to process the wiring for the active shield, making it possible to make the information analysis of the IC card through the signal wiring more difficult. . In the eighth embodiment, the active shield wiring is formed in the same uppermost wiring layer as the wirings 5A and 5B in FIG. That is, in the eighth embodiment, by arranging different types (or techniques) of shields (shields using power supply voltage wirings 5A and 5B and active shield wirings) in the plane of the same wiring layer, Decoding of the shield system can be made difficult, and release of the shield system or operation avoidance can be made more difficult, making it possible to make information analysis of the IC card more difficult. Further, by patterning the active shield wiring when patterning the wirings 5A and 5B, the manufacturing time of the semiconductor device does not increase significantly even if various types (or methods) of shielding systems are formed. . For example, the same potential as the wirings 5A and 5B in FIG. 19 is supplied to the active shield wiring. That is, the active shield wiring includes a low-potential-side power supply voltage (GND, for example, 0 V), a high-potential-side power supply voltage (VCC, for example, 1.8 V, 3.0 V, 5.0 V) or their power supplies. A potential other than voltage is supplied. Alternatively, a low-potential-side power supply voltage is supplied to a part of the active shield wiring, and a high-potential-side power supply voltage is supplied to another part of the active shield wiring. Anyway. Further, a potential other than the power supply voltage may be supplied to a part of the active shield wiring. As described above, by arranging a plurality of types of active shield wirings having different supply potentials in the same chip 3, it is possible to make it difficult to decipher the active shield system, and to release the active shield system or avoid operation. Since it can be made difficult, it is possible to make the information analysis of the IC card more difficult.

  FIG. 20 is an explanatory diagram of an example of the active shield wirings 5C and 5D (the specific wiring and the first wiring) constituting the active shield arranged in the area LA of FIG. FIG. 21 is an enlarged plan view of the main part of FIG.

  20 and 21 illustrate an active shield having planar comb-like wirings 5C and 5D. The wirings 5C and 5D are provided above the signal wirings of the signal wirings such as the bus wirings 18a and 18b and the control signal wirings 18c to 18e via an interlayer insulating film. The wirings 5C and 5D are arranged so that the teeth of the wirings 5C and 5D mesh with each other so as to cover the signal wiring. Further, the adjacent interval between the wirings 5C and 5D is made as narrow as possible so that lower layer signal wirings such as the bus wirings 18a and 18b and the control signal wirings 18c to 18e cannot be observed (see FIG. 21). That is, the wirings 5C and 5D are formed on lower signal wirings such as the bus wirings 18a and 18b and the control signal wirings 18c to 18e, and the main extending directions of the wirings 5C and 5D are lower signal wirings. It is arranged so as to cover them so as to coincide with the main extending direction. For this reason, even if the needle contact is attempted on the signal wirings below the wires 5C and 5D in order to analyze the information of the chip 3, the wires 5C and 5D are obstructed and the needle contact cannot be performed. Therefore, in the structure as in the eighth embodiment, the wirings 5C and 5D must be removed. However, if even a part of the wirings 5C and 5D is removed, the active shield system works and the integrated circuit does not operate. Information analysis is impossible. Therefore, it is possible to improve the security of information on the IC card. In the eighth embodiment, the wirings 5C and 5D are arranged so that the signal wirings in the lower layer cannot be seen, and the wiring widths and wiring intervals of the wirings 5C and 5D are the same as those of the signal wirings in the lower layer. It is the same dimension (minimum processing dimension) as the wiring width and wiring interval. In this way, by making the active shield wirings 5C and 5D similar to the signal wirings in the lower layer, it is difficult to understand which signal wiring is the real signal wiring, so that the information analysis of the IC card is made more difficult. It is possible. For example, a low-potential-side power supply voltage (GND, for example, 0V) is applied to the wiring 5C, and a high-potential-side power supply voltage (VCC, for example, 1.8V, 3.0V, 5.0V) is applied to the wiring 5D, for example. Is applied.

  Further, as shown in FIG. 20, a plurality of machining detection circuits 20 may be electrically connected to one active shield wiring 5C, 5D. Further, the machining detection circuit 20 may be connected to any position (end, intermediate position, comb tooth position, etc.) of the active shield wirings 5c and 5d. Further, one processing detection circuit 20 may be electrically connected to both of the two wirings 5C and 5D. The arrangement position of the machining detection circuit 20, the connection position of the machining detection circuit 20 to the active shield wirings 5C and 5D, or the number of machining detection circuits 20 connected to the individual wirings 5C and 5D are irregular. Is preferred. Moreover, it is preferable that the same or different distances exist between the machining detection circuits 20 and the active shield wirings 5C and 5D. As a result, it is possible to make it difficult to obtain information (arrangement position, number, etc.) of the processing detection circuit 20, so that it is difficult to decipher the active shield system. For this reason, it is possible to make it difficult to release the active shield system and to avoid the operation, and thus it is possible to make the information analysis of the IC card more difficult. Therefore, the security of the IC card can be further improved.

(Embodiment 9)
In the ninth embodiment, an example in which a power supply voltage wiring having a shielding function and an active shield wiring are arranged at the same position in a plan view but arranged in different wiring layers in a cross section will be described. To do.

  FIG. 22 is an explanatory diagram of the layout layer structure of the semiconductor device according to the ninth embodiment, FIG. 23 is a plan view of the main part of FIG. 22, and FIG. 24 is a plan view showing the shield removed from FIG. As shown in FIG. 22, the lowermost layout layer L0 includes, for example, a plurality of integrated circuit regions having desired elements constituting cells, modules, the memory circuit 3a, the logic circuit group 3b, the processing detection circuit, and the like. Is arranged. In the wiring layer L1 above the layout layer L0, signal wirings 18 such as the bus wirings 18a and 18b and the control signal wirings 18c to 18e are arranged. Further, in the wiring layer L2 above the wiring layer L1, the active shield wiring (specific wiring, first wiring) 5E described in the sixth to eighth embodiments is arranged. Here, one meandering wiring (single-stroke wiring) is illustrated as the active shield wiring 5E. The active shield wiring 5E includes, for example, a low-potential-side power supply voltage (GND, for example, 0V), a high-potential-side power supply voltage (VCC, for example, 1.8V, 3.0V, 5.0V), or any other voltage. Is applied. A plurality of processing detection circuits 20 are electrically connected to the wiring 5E (see FIG. 23). Since the processing detection circuit 20 connected to the wiring 5E is the same as in the sixth to eighth embodiments, the description thereof is omitted. Further, the uppermost wiring layer L3 above the wiring layer L2 is provided with power supply wirings 5A and 5B having the shielding function described in the first to fifth embodiments. That is, in the ninth embodiment, power supply voltage wirings 5A and 5B having a shielding function and active shield wiring 5E are formed in different wiring layers at the same plane position. In this way, it is possible to create a multilayer wiring structure in which wirings with a shielding function are stacked in the same plane position and stacked in different wiring layers via an interlayer insulating film, or the same shielding function but different methods are arranged By doing so, it is possible to make it difficult to decipher the shield system, and it is possible to make it more difficult to release the shield system and to avoid the operation, so that it is possible to make the information analysis of the IC card more difficult. Therefore, the security of the IC card can be further improved. However, the vertical relationship of the wiring layers of the power supply voltage wirings 5A and 5B and the active shield wiring 5E may be reversed. Further, between the wiring layer L3 in which the power supply voltage wirings 5A and 5B are formed and the wiring layer L2 in which the active shield wiring 5E is formed, a power supply voltage wiring or active shield having a shielding function is provided. Another wiring layer in which the wiring for wiring is laid out may be further interposed. An interlayer insulating film made of, for example, a silicon oxide film is provided between the layout layer L0 and the wiring layer L1, between the wiring layers L1 and L2, and between the wiring layers L2 and L3. That is, the wiring formed in each of the wiring layers L0, L1, L2, and L3 and the wiring formed in the upper and lower wiring layers are electrically separated by the interlayer insulating film, and the interlayer insulating film is formed between these wirings. It is electrically connected through the formed connection hole.

  In the ninth embodiment, as shown in FIG. 23, the power supply voltage wirings 5A and 5B having a shielding function and the active shield wiring 5E are at the same position in the plane (wiring in the same wiring layer). Is arranged. A lower layer active shield wiring 5E is disposed between adjacent power supply voltage wirings 5A and 5B having a shielding function. That is, the gap between adjacent power supply voltage wirings 5A and 5B having a shield function is filled with the active shield wiring 5E below the active shield wiring 5E, as shown in FIGS. It is possible to make the signal wiring 18 such as the bus wiring and the control signal wiring below the wiring 5E less visible, and to make the information analysis by the needle pad or FIB for the wiring 18 more difficult. Can be made. Therefore, the security of the IC card can be further improved. Similarly to the eighth embodiment, the wirings 5A, 5B, and 5E have the same dimensions (minimum) as the wiring widths and wiring intervals of the wirings 5A, 5B, and 5E. Processing dimensions). As a result, similar to the eighth embodiment, it is possible to make the information analysis of the IC card more difficult.

(Embodiment 10)
In the tenth embodiment, a case will be described in which a region where a shield is arranged is subdivided into a plurality of regions, and a shield having a different shape or technique is arranged for each subdivided region.

  FIG. 25 shows a shield area SA in which the shield is arranged, and FIGS. 26 to 29 show examples of plan views of active shield wirings having different shapes.

  In the tenth embodiment, as shown in FIG. 25, the shield area (first area) SA is equally divided into, for example, nine sub-shield areas (second areas) SSA1 to SSA9. Here, a case where the shapes and areas of the sub-shield areas LA1 to LA9 are equal is illustrated. The shield area SA may be the entire main surface of the chip 3, for example, or may be the wiring area (corresponding to the area LA) or the circuit area of the chip 3 main surface. FIG. 26 illustrates active shield wirings 5C and 5D arranged in the sub shield area SSA1 of FIG. The active shield wirings 5C and 5D in FIG. 26 have the same comb-teeth shape as described in FIG. FIG. 27 exemplifies the wiring 5E for active shield arranged in the sub shield area SSA2 of FIG. The active shield wiring 5E in FIG. 27 has the same meandering shape as described in FIGS. FIG. 28 illustrates an active shield wiring (specific wiring, first wiring) 5F arranged in the sub shield area SSA3 of FIG. The active shield wiring 5F in FIG. 28 has a shape in which the meandering wiring is intricately complicated so as to cover the underlying signal wiring, elements, and the like. For example, a low-potential-side power supply voltage (GND, for example, 0V) or a high-potential-side power supply voltage (VCC, for example, 1.8V, 3.0V, 5.0V) is applied to the wiring 5F. FIG. 29 illustrates active shield wirings 5C and 5E arranged in the sub shield area SSA4 of FIG. The active shield wiring 5C in FIG. 29 has the same comb-teeth shape as described in FIG. 20, and the active shield wiring 5E in FIG. 29 has been described with reference to FIGS. The same meandering shape as The wirings 5C and 5E are arranged in such a manner that the tooth portion of the wiring 5C enters the concave gap region of the wiring 5E so as to cover the underlying signal wirings and elements. Thus, by arranging various shapes of the active shield wirings 5C, 5D, 5E, and 5F in the shield area SA, it is possible to make it difficult to decipher the shield system and to make it difficult to release the shield system and avoid operation. Therefore, the information analysis of the IC card can be made more difficult, and the security of the IC card can be further improved. The active shield wirings 5C, 5D, 5E, and 5F may be arranged in the same wiring layer or in different wiring layers. Similarly to the eighth and ninth embodiments, the wirings 5C to 5F have the same wiring width and wiring spacing as the wiring width and wiring spacing of the signal wiring 18 (minimum processing dimension). ). As a result, similar to the eighth and ninth embodiments, it is possible to make the information analysis of the IC card more difficult. Since the configuration of the machining detection circuit 20 and the arrangement state with respect to each of the wirings 5C to 5F are the same as those in the sixth to ninth embodiments, description thereof is omitted.

  Moreover, the shape of the wiring for such an active shield is not limited to the above-described shape, and may be variously changed as long as it can cover and cover the signal wiring and elements in the lower layer. The active shield wirings arranged in the sub-shield areas SSA1 to SSA9 do not necessarily have different shapes, and active shield wirings having the same shape are arranged in the different sub-shield areas SSA1 to SSA9. It may be arranged. Although only the active shield has been described here, the power supply voltage wirings 5A and 5B having the shield function described in the first to fifth embodiments are arranged in different shapes for the sub shield areas SSA1 to SSA9. Also good. Alternatively, power supply voltage wirings 5A and 5B having a shielding function may be arranged in any of the subshield areas SSA1 to SSA9, and active shield wirings may be arranged in the other subshield areas SSA1 to SSA9. This makes it difficult to decipher the shield system and makes it difficult to release the shield system and avoid operation, making it possible to make information analysis of the IC card more difficult and further improving the security of the IC card. It becomes possible.

  30 and 31 show examples of the arrangement of the active shield wirings arranged in the sub shield areas SSA1 to SSA9. FIG. 30 shows a case where one pair of wirings 5C and 5D for active shield is arranged in the sub shield area SSA1. FIG. 31 shows a case where a plurality of pairs of active shield wirings 5C and 5D are arranged in the sub shield area SSA1. In the pair of active shield wirings 5C and 5D, a pair in which upper and lower adjacent pairs in FIG. 31 are arranged asymmetrically in the vertical direction and a pair in which the pairs are arranged in the vertical direction are mixed. This makes it difficult to decipher the shield system and makes it difficult to release the shield system and avoid operation, making it possible to make information analysis of the IC card more difficult and further improving the security of the IC card. be able to.

  In each of the shields disclosed in the first to ninth embodiments, the information analysis of the IC card is further performed by arranging a shield having a different shape or method for each subdivided region as in the present embodiment. The security of the IC card can be further improved.

(Embodiment 11)
In the eleventh embodiment, a case will be described in which the planar positional relationship between the active shield wiring and the detection circuit electrically connected thereto is irregular.

  The processing detection circuit that constitutes the active shield system may be connected to the active shield wiring from anywhere, but the connection relationship between the processing detection circuit and the active shield wiring to which it is connected is decoded and processed. If the position of the detection circuit is determined, the machining detection circuit may be destroyed so that the shield function is not exhibited. Therefore, in the eleventh embodiment, the active shield wiring and the processing detection circuit electrically connected thereto are arranged so that their planar positional relationships are irregular. FIG. 32 illustrates this. FIG. 32 illustrates three sub shield areas SSA1, SSA3, SSAn and three processing detection circuits 20a1, 20a2, 20a3 (20) corresponding to each of them, and the corresponding sub shield areas and processing detection circuits With the same hatching. The processing detection circuit 20a1 connected to a predetermined active shield wiring arranged in the sub shield area SSA1 of the uppermost wiring layer L3 is not directly under the sub shield area SSA1 in the layout layer L0, and is another irregularity. It is arranged at a flat position. Similarly, with respect to the other subshield areas SSA3, SSAn, etc. of the wiring layer L3, the processing detection circuits 20a2, 20an connected to the respective active shield lines are connected to the arrangement positions of the subshield areas SSA3, SSAn. They are arranged in the layout layer L0 without regularity. Accordingly, the positions of the active shield wirings of the sub shield areas SSA1, SSA3, SSAn and the processing detection circuits 20 (20a1, 20a3, 20an) electrically connected to the respective active shield wirings. It is possible to make it difficult to decipher relationships and connection relationships, and to make it difficult to release the shield system and avoid operation, making it possible to make information analysis of IC cards more difficult and further improving the security of IC cards It becomes possible.

  In each of the sixth to tenth embodiments, an arrangement in which the planar positional relationship between the active shield wiring and the detection circuit electrically connected thereto is irregular as in the present embodiment is applied. As a result, the information analysis of the IC card can be made more difficult, and the security of the IC card can be further improved.

(Embodiment 12)
In the twelfth embodiment, an example in which a plurality of processing detection circuits are electrically connected to a predetermined active shield wiring will be described. FIG. 33 shows an example of the active shield system. Here, a plurality of sub-shield areas SSA are arranged. The sub shield area SSA is an area corresponding to the sub shield areas SSA1 to SSA9. In each sub shield area SSA, an active shield wiring is arranged. The shape of the active shield wiring in each sub shield area SSA may be the same or different. A plurality of processing detection circuits 20 are electrically connected to the active shield wiring in each sub shield area SSA. The active shield wiring and the processing detection circuit 20 are randomly connected in an intermediate wiring layer between the wiring layer in which the layout layer L0 and the main signal wiring are arranged and the wiring layer in which the active shield wiring is arranged. Has been. The connection relationship between the active shield wiring and the machining detection circuit 20 is complicated so that it is difficult to decipher. Here, the area of the sub shield area SSA is made as small as possible, and the wiring for each active shield is monitored by the plurality of processing detection circuits 20. By monitoring with a plurality of processing detection circuits 20, even if one processing detection circuit 20 is destroyed and invalidated, another processing detection circuit 20 operates, so that information on the IC card can be protected. Further, by subdividing the sub-shield area SSA into smaller areas, the overall shield wiring layout in the shield area SA and the connection relationship with the processing detection circuit 20 can be made more complex. Decryption can be made difficult, and the security of the IC card can be improved.

  In each of the sixth to eleventh embodiments, an IC card is applied by applying an arrangement in which a plurality of processing detection circuits are electrically connected to a predetermined active shield wiring as in the present embodiment. Information analysis can be made more difficult, and the security of the IC card can be further improved.

(Embodiment 13)
In the thirteenth embodiment, an example in which the potential of the active shield wiring is not constant will be described. That is, an example in which the potential of the active shield wiring is changed over time will be described.

  FIG. 34 illustrates an example of an active shield system according to the thirteenth embodiment. In this system, a predetermined potential is supplied from the potential supply circuit 25 formed on the chip 3 to the active shield wiring (the wiring 5E is illustrated in FIG. 34). The potential supply circuit 25 changes the potential supplied to the active shield wiring 5E at regular intervals in synchronization with a synchronization signal from an independent oscillator 26 formed in the chip 3. Further, the synchronization signal of the oscillator 26 is also transmitted to the machining detection circuit 20 through the synchronization signal wiring 27, and the correct / incorrect reference potential in accordance with the synchronization signal sent from the oscillator 26 also on the machining detection circuit 20 side. Is supposed to change. The correct / incorrect reference potential is a reference potential to be compared when determining whether or not the detection potential of the active shield wiring 5E detected by the processing detection circuit 20 is correct. When the correct / incorrect reference potential is equal to the detected potential (including an allowable error), the detected potential is determined to be correct. In other words, the machining detection circuit 20 compares the detected potential of the active shield wiring 5E detected at a predetermined time with the correct / incorrect reference potential to be detected at the predetermined time, and detects that each potential is different. The IC card information analysis is prevented by resetting the integrated circuit of the chip 3 so that the integrated circuit cannot operate. By changing the potential of the active shield wiring 5E in this way, it is possible to make it difficult to cancel the active shield system and to avoid operation, so that it is possible to make the information analysis of the IC card more difficult and the security of the IC card. Can be further improved. Note that the oscillator 26 operates when the power is turned on.

  In each of the sixth to twelfth embodiments, by applying a configuration in which the potential of the active shield wiring is not constant as in the present embodiment, the information analysis of the IC card can be made more difficult. The security of the IC card can be further improved.

(Embodiment 14)
In the fourteenth embodiment, another example will be described in which the potential of the active shield wiring is not made constant but is changed with time.

  In the fourteenth embodiment, the switching time of the potential of the active shield wiring is irregular. FIG. 35 illustrates an example of an active shield system according to the fourteenth embodiment. In this system, the frequency of the synchronizing signal output from the oscillator 26 is changed by turning the frequency dividing circuit 29 on (ON) or off (OFF) by the signal transmitted from the random number generating circuit 28 to the frequency dividing circuit 29. It has become. That is, in the fourteenth embodiment, the frequency of the synchronization signal output from the oscillator 26 is changed irregularly through the frequency divider 26. The potential supply circuit 25 changes the potential supplied to the active shield wiring (the wiring 5E is illustrated in FIG. 35) in synchronization with the synchronization signal from the frequency dividing circuit 29. Therefore, in the fourteenth embodiment, the potential of the active shield wiring 5E does not change every fixed time but changes every irregular time. The synchronization signal from the frequency divider 29 is also transmitted to the machining detection circuit 20 through the synchronization signal wiring 27. On the processing detection circuit 20 side, the correct / incorrect reference potential described in the thirteenth embodiment is changed in accordance with the synchronization signal sent from the frequency dividing circuit 29. Therefore, in the fourteenth embodiment, even if the potential of the active shield wiring 5E changes irregularly, the correct / incorrect reference potential of the machining detection circuit 20 can be changed accordingly. Then, the machining detection circuit 20 compares the detected potential of the active shield wiring 5E detected at a predetermined time with the correct / incorrect reference potential to be detected at the predetermined time, and detects that each potential is different. As in the thirteenth embodiment, the IC card information analysis is prevented by resetting the integrated circuit of the chip 3 so that the integrated circuit cannot operate. In this manner, by making the timing of the potential change of the active shield wiring 5E irregular, it is possible to make it difficult to read the timing of the potential change of the active shield wiring 5E, thereby releasing the active shield system and avoiding the operation. Therefore, the information analysis of the IC card can be made more difficult, and the security of the IC card can be further improved. Further, the active shield system according to the fourteenth embodiment and the active shield system according to the thirteenth embodiment may be mixed in the same chip 3. As a result, it becomes more difficult to decipher the active shield system in the chip 3, so that the security of the IC card can be further improved.

  In each of the sixth to thirteenth to thirteenth embodiments, the IC card information analysis is performed by applying a configuration in which the potential of the active shield wiring is not made constant as in the present embodiment but is changed with time. It can be made more difficult, and the security of the IC card can be further improved.

(Embodiment 15)
The fifteenth embodiment will explain still another example in which the potential of the active shield wiring is not made constant but is changed with time.

  In the fifteenth embodiment, when a signal of a predetermined frequency is supplied to the active shield wiring and the signal of that frequency cannot be detected, the integrated circuit of the chip 3 cannot be operated. ing. FIG. 36 shows an example of the active shield system of the semiconductor device of the fifteenth embodiment. A signal of a predetermined frequency generated by the oscillator 26 is transmitted to an active shield wiring (the wiring 5E is illustrated in FIG. 36). The processing detector 20 does not operate while a signal of a predetermined frequency is flowing through the active shield wiring 5E, and the potential of the active shield wiring 5E is high (DC) in a direct current (DC) manner. When it is fixed to Low, it is detected and the integrated circuit of the chip 3 is reset so that the integrated circuit cannot operate, thereby preventing information analysis of the IC card. In the case of the fifteenth embodiment, in addition to the effects obtained in the thirteenth and fourteenth embodiments, the following effects can be obtained. In other words, since the shield system has a simple configuration and is difficult to be destroyed, it is possible to make it more difficult to release the active shield system and to avoid the operation. Security can be further improved. Further, since the configuration of the shield system is simple, the manufacturing process of the semiconductor device is not complicated. Furthermore, the arrangement area of the elements and wirings for the active shield system can be reduced as compared with the thirteenth and fourteenth embodiments. Further, the active shield system of the fifteenth embodiment and the active shield systems of the thirteenth and fourteenth embodiments may be mixed in the same chip 3. As a result, it becomes more difficult to decipher the active shield system in the chip 3, so that the security of the IC card can be further improved.

  In each of the above-described sixth to fourteenth embodiments, the IC card information analysis is performed by applying a configuration in which the potential of the active shield wiring is not made constant as in the present embodiment but is changed with time. It can be made more difficult, and the security of the IC card can be further improved.

(Embodiment 16)
In the sixteenth embodiment, a case where different active shield wirings are arranged in the same wiring layer will be described. FIG. 37 shows an example of the arrangement of the active shield wirings 5C, 5D, and 5E according to the sixteenth embodiment. In the sixteenth embodiment, active shield wirings 5C, 5D, and 5E having different shapes are arranged in the same wiring layer of the chip 3. The shapes of the wirings 5C, 5D, and 5E are the same as those described in the eighth to tenth embodiments. The arrangement of the wirings 5C and 5D is the same as described in the eighth and tenth embodiments. The wiring 5E is arranged in a gap between the adjacent wirings 5C and 5D, and is arranged so as to cover the lower signal wiring 18 and elements. A plurality of processing detection circuits 20 are electrically connected to each of the wirings 5C, 5D, 5E as in the eighth to tenth embodiments. Also in the sixteenth embodiment, the security of the IC card can be improved.

  In each of the sixth to fifteenth embodiments, by applying a configuration in which different active shield wirings are arranged in the same wiring layer as in the present embodiment, it becomes more difficult to analyze the information of the IC card. The security of the IC card can be further improved.

(Embodiment 17)
In the seventeenth embodiment, another example in which the shield area is subdivided into a plurality of sub-shield areas will be described. FIG. 38 shows a plan view of an example of the shield area SA. Xa1, Xa2,... Xa6 indicate X coordinates, and Ya1, Ya2,... Ya6 indicate Y coordinates.

  Also in the seventeenth embodiment, the shield area SA is subdivided into a plurality of sub-shield areas SSA. However, the sub-shield regions SSA have different areas, and various shapes are irregularly arranged. For this reason, the arrangement configuration of the sub shield area SSA of the shield area SA is asymmetrical in the vertical and horizontal directions. In each sub shield area SSA, active shield wirings having different shapes are arranged as in the tenth embodiment. This makes it difficult to decipher the active shield system, so that the security of the IC card can be improved.

  In each of the sixth to sixteenth embodiments, by applying a configuration in which the shield area is subdivided into a plurality of sub-shield areas as in the present embodiment, the information analysis of the IC card becomes more difficult. The security of the IC card can be further improved.

(Embodiment 18)
In the eighteenth embodiment, another example in which the shield area is subdivided into a plurality of sub-shield areas will be described.

  In the eighteenth embodiment, the subdivision configuration of the shield area is changed for each chip constituting the IC card or for each manufacture of the semiconductor device. FIG. 39 shows a plan view of an example of the shield area SA. 39, the shield area SA is subdivided into a plurality of sub-shield areas SSA as in FIG. 38, but the shape and arrangement of each sub-shield area SSA are different from those in FIG. In the eighteenth embodiment, among the same wafer, the shield area SA of FIG. 38 is used for a certain chip, and the shield area SA of FIG. 39 is used for another chip. Alternatively, the shield area SA of FIG. 38 is used for all chips in a certain wafer, and the shield area SA of FIG. 39 is used for all chips in another wafer. By doing so, just because the shield system of one chip is decoded, the shield system of another chip cannot be decoded as it is. Therefore, it is possible to make it difficult to decipher the active shield system, and it is possible to improve the security of the IC card.

  In each of the sixth to seventeenth embodiments, by applying a configuration in which the shield area is subdivided into a plurality of sub-shield areas as in the present embodiment, the information analysis of the IC card is made more difficult. The security of the IC card can be further improved.

(Embodiment 19)
In the nineteenth embodiment, another example in which different shield areas are stacked in multiple layers will be described. That is, the active shield wirings in the shield areas SA of FIG. 38 and FIG. 39 are arranged in different wiring layers at the same plane position of the chip 3. As a result, the way of overlapping the active shield wirings can be further complicated when viewed in a plan view, making it difficult to decipher the active shield system. For this reason, it is possible to improve the security of the IC card.

  Also, active shield wirings of different wiring layers may be electrically connected through a through hole or the like. The through hole is a fine hole opened in an interlayer insulating film interposed between different wiring layers, and a connection conductor is embedded therein. In this case, the wiring path of the active shield system can be changed by a relatively simple method in terms of design and process by variously changing the arrangement position of the through hole for each chip. That is, at first glance, although the plane layout of the active shield wiring is the same, the wiring path of the active shield system is completely different due to the difference in the arrangement of the through holes. In addition, since the through-hole is fine, it is difficult to search for the wiring path only by looking at the plane, so that it is difficult to decipher the active shield system. Therefore, the security of the IC card can be improved.

  In each of the sixth to eighteenth embodiments, by applying a configuration in which different shield areas are stacked in layers as in the present embodiment, it is possible to make information analysis of the IC card more difficult, and the IC card. Security can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the sixth and seventh embodiments, the case where the machining detection is performed when the machining detection wiring of the machining detection circuit is cut has been described. However, the present invention is not limited to this. For example, the machining detection is performed. Even if the wiring for cutting is not completely cut but partly cut and partially connected, the fluctuation of the potential of the wiring for machining detection is detected by the processing, and the fluctuation of the potential is detected. Thus, the integrated circuit may be reset.

  In the first to seventh embodiments, the case where the present invention is applied to a so-called contact type IC card in which information in a chip is exchanged through electrodes on the back surface of the package substrate has been described. However, the present invention is not limited to this. For example, the present invention is applied to a so-called non-contact type IC card in which a coil (antenna) is provided in a card body and data is read / written without contact with a reader / writer using radio waves. It can also be applied.

  Also, by combining each of the first to nineteenth embodiments with one or more of the other first to nineteenth embodiments, the information analysis of the IC card can be made more difficult, Security can be further improved.

  In addition, the first to nineteenth embodiments are not limited to the wiring structure shown in the figure, and it is needless to say that the metal multilayer wiring structure having five to ten layers may be used.

  In the above description, the case where the invention made mainly by the present inventor is applied to an IC card which is a field of use as the background has been described. However, the present invention is not limited to this. Applicable to all things.

  To summarize this embodiment, power supply voltage supply wirings 5A and 5B for supplying a drive voltage to the integrated circuit of the semiconductor chip 3 are arranged so as to cover the main surface of the semiconductor chip 3, and the semiconductor chip 3 If the wirings 5A and 5B are removed to analyze the information stored in the integrated circuit, the integrated circuit does not operate and the information cannot be analyzed. As described above, when the predetermined wiring arranged in the upper layer of the semiconductor chip is removed or cut, it becomes impossible to analyze the information stored in the semiconductor chip, so that the information stored in the semiconductor device is stored. It becomes possible to improve the security of information.

  Further, a machining detection circuit 20 that detects the machining of the wirings 5A and 5B is provided. When the processing detection circuit 20 detects the processing of the wirings 5A and 5B, the integrated circuit is reset. Providing such a processing detection circuit makes it impossible to analyze the information stored in the semiconductor chip, so that the security of the information stored in the semiconductor device can be improved.

  The present invention can be applied to, for example, electronic money, credit cards, mobile phones, pay satellite receivers, identification cards, licenses, insurance cards, electronic medical records, electronic tickets, finance, distribution, medical care, transportation, transportation or education. It is useful as a semiconductor device used as a medium for storing various types of information, and is particularly suitable for use in an IC card.

It is a top view of the IC card (semiconductor device) which is one embodiment of this invention. It is sectional drawing of the X1-X1 line | wire of FIG. It is sectional drawing of the X1-X1 line | wire of FIG. 1 in the IC card of the modification of FIG. It is a top view of the semiconductor chip which comprises the IC card of FIG. FIG. 5 is a plan view of a principal part of an element region on the main surface of the semiconductor chip of FIG. 4. It is principal part sectional drawing of the semiconductor chip of FIG. It is a top view of the semiconductor chip which comprises the IC card (semiconductor device) which is other embodiment of this invention. It is a top view of the modification of the semiconductor chip which comprises the IC card which is other embodiment of this invention. It is a top view of the modification of the semiconductor chip which comprises the IC card which is other embodiment of this invention. It is sectional drawing of the X3-X3 line | wire of FIG. It is a top view of an example of the semiconductor chip which comprises the IC card which is other embodiment of this invention. It is a top view of an example of the semiconductor chip which comprises the IC card which is other embodiment of this invention. FIG. 13 is a circuit diagram of an example of the processing detection circuit of FIG. 12. It is explanatory drawing of operation | movement of the process detection circuit diagram of FIG. It is a principal part enlarged plan view of the semiconductor chip of FIG. It is sectional drawing of the X4-X4 line | wire of FIG. It is explanatory drawing of the connection structure of the process detection circuit of the IC card which is other embodiment of this invention. FIG. 5 is a plan view of the main surface of the semiconductor chip in FIG. 4. It is a top view of the semiconductor chip which comprises the semiconductor device which is other embodiment of this invention. It is explanatory drawing of the shield arrange | positioned at the semiconductor chip of FIG. It is a principal part enlarged plan view of FIG. It is explanatory drawing of the layout layer structure of the semiconductor device of this Embodiment 9. It is a principal part top view of FIG. It is the top view which removed and showed the wiring which has a shield function from FIG. It is a top view which shows the example of the subdivision of the area | region which arrange | positions a shield. It is a top view of an example of the wiring for active shields. It is a top view of an example of the wiring for active shields. It is a top view of an example of the wiring for active shields. It is a top view of an example of the wiring for active shields. It is a top view of the example of arrangement | positioning of the wiring for active shield for every area | region which subdivided the area | region which arrange | positions a shield. It is a top view of the example of arrangement | positioning of the wiring for active shield for every area | region which subdivided the area | region which arrange | positions a shield. It is explanatory drawing of arrangement | positioning with the wiring and detection element which comprise the shield system of the semiconductor device which is other embodiment of this invention. It is explanatory drawing of the example of the shield system of the semiconductor device which is other embodiment of this invention. It is explanatory drawing of a structural example of the shield system of the semiconductor device which is further another embodiment of this invention. It is explanatory drawing of the example of the shield system of the semiconductor device which is other embodiment of this invention. It is explanatory drawing of the example of the shield system of the semiconductor device which is other embodiment of this invention. It is a top view of an example of the wiring for shielding of the semiconductor device which is other embodiments of the present invention. It is a top view which shows the example of the subdivision of the area | region which arrange | positions a shield. It is a top view which shows the example of the subdivision of the area | region which arrange | positions a shield. It is a principal part enlarged plan view of the semiconductor chip which comprises the IC card which is other embodiment of this invention.

Explanation of symbols

1 IC card (semiconductor device)
2 groove 3 semiconductor chip 3S semiconductor substrate 4 package 4a package substrate 4b bonding wire 4c sealing resin 4d bump electrode 5A, 5B wiring for power supply voltage 6 field insulating film 7a, 7b p-type semiconductor region 8 gate insulating film 9 gate electrode 10a, 10b n-type semiconductor region 11a Interlayer insulating films 12a-12f First layer wirings 13a-13d Second layer wirings 14 Third layer wirings 15 Surface protective films 15a, 15b Insulating films 16A-16D Circuit block 17 Wiring region 18 Wiring 18a, 18b Bus wiring 18c-18e Control signal wiring 19 Circuit cell 20, 20a-20d Processing detection circuit IMA Information storage area BPA, BPB, BPC, BPD, BPE, BPF Bonding pad PWL p well NWP, PWP well feeding area PL1, PL2 plug CNT converter Kutohoru TH1~TH3 through-hole Qp, Qp1 p-channel type MIS · FET
Qn, Qn1 n-channel type MIS • FET
N1-N4 Node OUT output

Claims (61)

A semiconductor device having the following configuration;
(A) a first element formed on the main surface of the semiconductor chip and contributing to information storage;
(B) a first region disposed on the main surface of the semiconductor chip and divided into a plurality of second regions;
(C) a desired signal wiring formed in the first region;
(D) When the first wirings arranged in the plurality of second regions above the desired signal wiring and formed in different shapes are cut, it is detected. A detection circuit that disables information analysis of the first element.   2. The semiconductor device according to claim 1, wherein the first wiring is a power supply voltage wiring.   3. The semiconductor device according to claim 2, wherein the power supply voltage wiring includes a high potential power supply voltage wiring that supplies a relatively high power supply voltage and a low potential power supply that supplies a relatively low power supply voltage. And a wiring for power supply voltage.   4. The semiconductor device according to claim 2, wherein the power supply voltage wiring is configured by arranging a single wiring in a predetermined shape so as to cover the desired signal wiring. Semiconductor device.   4. The semiconductor device according to claim 2, wherein the power supply voltage wiring is constituted by a single wiring so that the cut wirings are completely insulated from each other when cut. Semiconductor device.   6. The semiconductor device according to claim 1, wherein the detection circuits are distributed and arranged in a main surface of the semiconductor chip.   7. The semiconductor device according to claim 6, wherein the detection circuit is disposed in a circuit block region on a main surface of the semiconductor chip.   8. The semiconductor device according to claim 6, wherein the detection circuit is arranged in a wiring region on a main surface of the semiconductor chip.   6. The semiconductor device according to claim 3, wherein the power supply voltage wiring is different from a power supply voltage wiring for supplying a power supply voltage for driving the detection circuit. Semiconductor device.   10. The semiconductor device according to claim 1, wherein an input wiring of a predetermined detection circuit among the detection circuits is a wiring for a power supply voltage of another detection circuit. Semiconductor device. An IC card having the following configuration;
(A) a first element formed on the main surface of the semiconductor chip and contributing to information storage;
(B) a second element formed on the main surface of the semiconductor chip;
(C) a first region disposed on the main surface of the semiconductor chip and divided into a plurality of second regions;
(D) a desired signal wiring formed in the first region;
(E) When a first wiring that is arranged in each of the plurality of second regions on the upper layer of the desired signal wiring and that has a different shape is cut, it is detected A detection circuit that disables information analysis of the first element;
(F) a package for sealing the semiconductor chip;
(G) A plate-shaped card body that houses the package in the groove. (A) a first region disposed on the main surface of the semiconductor chip and divided into a plurality of second regions;
(B) a first wiring formed in the first region;
(C) a detection circuit for detecting a change in the first wiring;
(D) a package for sealing the semiconductor chip;
(E) a plate-shaped card body that houses the package in the groove;
Have
The IC card is characterized in that the first area is divided into a plurality of second areas, and the shapes of the first wirings arranged in the respective second areas are different from each other.   13. The IC card according to claim 11, wherein the first wiring is a power supply voltage wiring.   14. The IC card according to claim 13, wherein the power supply voltage wiring includes a high potential power supply voltage wiring for supplying a relatively high power supply voltage and a low potential power supply for supplying a relatively low power supply voltage. An IC card comprising a power supply voltage wiring.   15. The IC card according to claim 13, wherein the power supply voltage wiring is configured by arranging a single wiring in a predetermined shape so as to cover the desired signal wiring. IC card to do.   15. The IC card according to claim 13, wherein the power supply voltage wiring is constituted by a single wiring so that the cut wirings are completely insulated from each other when cut. IC card.   17. The IC card according to claim 11, wherein the detection circuit is distributed and arranged in a main surface of the semiconductor chip.   18. The IC card according to claim 17, wherein the detection circuit is arranged in a circuit block region on a main surface of the semiconductor chip.   18. The IC card according to claim 17, wherein the detection circuit is arranged in a wiring region on a main surface of the semiconductor chip.   17. The IC card according to claim 13, wherein the power supply voltage wiring is different from a power supply voltage wiring that supplies a power supply voltage for driving the detection circuit. IC card to do.   21. The IC card according to claim 11, wherein an input wiring of a predetermined detection circuit among the detection circuits is a wiring for a power supply voltage of another detection circuit. IC card to do. A semiconductor device having the following configuration;
(A) a first region disposed on the main surface of the semiconductor chip;
(B) a plurality of second regions formed by dividing the first region;
(C) a first wiring disposed in each of the plurality of second regions;
(D) A detection circuit that detects processing of a first wiring arranged in a predetermined second region of the plurality of second regions of the first wiring.   23. The semiconductor device according to claim 22, wherein the semiconductor chip is disposed in the first region so as to overlap the first wiring in a wiring layer different from a wiring layer in which the first wiring is disposed. A power supply voltage wiring that contributes to driving of the integrated circuit is disposed.   24. The semiconductor device according to claim 23, wherein the first wiring pattern is disposed at a planar position corresponding to a gap between adjacent power supply voltage wiring patterns.   25. The semiconductor device according to claim 22, wherein the first wirings having different shapes are arranged in the first region, and the first wirings are arranged in the same wiring layer. Semiconductor device.   26. The semiconductor device according to claim 25, wherein the first wirings having different shapes are arranged so that a pattern of another first wiring is interposed in a gap between adjacent first wiring patterns. A semiconductor device.   26. The semiconductor device according to claim 22, wherein the shape of the first wiring arranged in each second region is different from each other.   26. The semiconductor device according to claim 22, 23, 24, or 25, wherein a first wiring arranged in another second region different from the predetermined second region, and the predetermined second region A semiconductor device having a shape different from that of the arranged first wiring.   27. The semiconductor device according to claim 22, wherein the other second region is covered with another second region different from the predetermined second region. A semiconductor device, wherein wiring for a power supply voltage contributing to driving of an integrated circuit is arranged.   30. The semiconductor device according to claim 29, wherein the first wiring and the power supply voltage wiring are arranged in the same wiring layer.   31. The semiconductor device according to claim 22, wherein a plurality of the detection circuits are electrically connected to the first wiring.   32. The semiconductor device according to claim 22, wherein the detection circuit is arranged at an irregular position with respect to a position of the first wiring to which the detection circuit is connected. Semiconductor device.   33. The semiconductor device according to claim 22, wherein a width and a pitch of the first wiring are the same as a width and a pitch of a wiring constituting the integrated circuit of the semiconductor chip. A semiconductor device.   34. The semiconductor device according to claim 22, wherein the potential of the first wiring is changed.   35. The semiconductor device according to claim 22, wherein a potential of the first wiring is irregularly changed.   36. The semiconductor device according to claim 22, wherein a signal having a predetermined frequency is caused to flow through the first wiring, and the signal having the predetermined frequency is detected by the detection circuit. A semiconductor device.   37. The semiconductor device according to claim 22, wherein the first wiring is arranged in a wiring layer that is higher than a desired signal wiring constituting the integrated circuit of the semiconductor chip. A featured semiconductor device. A semiconductor device having the following configuration;
(A) a first region disposed on the main surface of the semiconductor chip;
(B) a plurality of second regions formed by dividing the first region;
(C) a first wiring arranged in a predetermined second region of the plurality of second regions,
(D) A wiring for a power supply voltage that contributes to driving of the integrated circuit of the semiconductor chip, and the other second region so as to cover another second region of the plurality of second regions. A power supply voltage wiring formed in a region and having a shape different from that of the first wiring;
(E) A detection circuit for detecting processing of the first wiring. A semiconductor device having the following configuration;
(A) a first region disposed on the main surface of the semiconductor chip;
(B) a first wiring disposed in the first region;
(C) A wiring for a power supply voltage that contributes to driving of the integrated circuit of the semiconductor chip, in a wiring layer different from the wiring layer on which the first wiring is arranged, in plan view with the first wiring A wiring for a power supply voltage that is arranged in the first region so as to overlap and is formed in a shape different from that of the first wiring;
(D) A detection circuit for detecting processing of the first wiring. In semiconductor devices,
(A) a first region disposed on the main surface of the semiconductor chip;
(B) a first wiring disposed in the first region;
(C) having a detection circuit for detecting processing of the first wiring;
In the first region, the first wiring having a different shape is arranged,
The semiconductor device according to claim 1, wherein the first wirings having different shapes are arranged in different regions of the first region. In semiconductor devices,
(A) a first region disposed on the main surface of the semiconductor chip;
(B) a plurality of second regions formed by dividing the first region;
(C) a first wiring arranged for each of the plurality of second regions;
(D) having a detection circuit for detecting the processing of the first wiring;
The semiconductor device is characterized in that the detection circuit is arranged so that a positional relationship with a second region having the first wiring to which the detection circuit is connected is irregular. 41. The semiconductor device according to claim 40, wherein
A semiconductor device characterized in that a width and a wiring pitch of the first wiring are made the same as a width and a wiring pitch of a wiring constituting the integrated circuit of the semiconductor chip. 41. The semiconductor device according to claim 40, wherein
A semiconductor device, wherein the potential of the first wiring is changed. 41. The semiconductor device according to claim 40, wherein
A semiconductor device, wherein the potential of the first wiring is irregularly changed. 41. The semiconductor device according to claim 40, wherein
A semiconductor device, wherein a signal having a predetermined frequency is supplied to the first wiring and the signal having the predetermined frequency is detected by the detection circuit. (A) a first region disposed on the main surface of the semiconductor chip;
(B) a first wiring disposed in the first region;
(C) a detection circuit for detecting a change in the first wiring;
Have
The semiconductor device is characterized in that the first region is divided into a plurality of second regions, and the shapes of the first wirings arranged in the second regions are different from each other. The semiconductor device according to claim 46,
The semiconductor device is characterized in that the detection circuit is arranged so that a positional relationship with a second region having the first wiring to which the detection circuit is connected is irregular. (A) a first region disposed on the main surface of the semiconductor chip;
(B) a plurality of second regions formed by dividing the first region;
(C) a first wiring arranged for each of the plurality of second regions;
(D) a detection circuit that detects a change in the predetermined first wiring in a predetermined first wiring among the first wirings in the second regions;
Have
The semiconductor device is characterized in that the detection circuit is arranged so that a positional relationship with a second region having the first wiring to which the detection circuit is connected is irregular. (A) a first region disposed on the main surface of the semiconductor chip;
(B) a plurality of second regions formed by dividing the first region;
(C) a first wiring arranged for each of the plurality of second regions;
(D) a detection circuit that detects a change in the predetermined first wiring in a predetermined first wiring among the first wirings in the second regions;
Have
The shapes of the first wirings arranged in the second region are different from each other,
2. The semiconductor device according to claim 1, wherein the detection circuit is arranged so that a positional relationship with the second region having the predetermined first wiring to which the detection circuit is connected is irregular.   50. The semiconductor device according to claim 45, wherein a plurality of the detection circuits are provided for the first wiring.   51. The semiconductor device according to claim 45, wherein a width and a wiring pitch of the first wiring are set to be the same as a width and a wiring pitch of a wiring constituting the integrated circuit of the semiconductor chip. A featured semiconductor device.   52. The semiconductor device according to claim 45, wherein the potential of the first wiring is changed.   53. The semiconductor device according to claim 45, wherein the potential of the first wiring is irregularly changed.   54. The semiconductor device according to claim 45, wherein a signal having a predetermined frequency is caused to flow through the first wiring, and the signal having the predetermined frequency is detected by the detection circuit. A semiconductor device. (A) a first region disposed on the main surface of the semiconductor chip;
(B) a plurality of second regions formed by dividing the first region;
(C) a first wiring arranged for each of the plurality of second regions;
(D) a second wiring formed in a layer different from the first wiring and disposed in each of the plurality of second regions;
(E) a first detection circuit that detects a change in the predetermined first wiring in a predetermined first wiring among the first wirings in the second regions;
Have
The first detection circuit is arranged such that a positional relationship with the second region having the predetermined first wiring connected to the first detection circuit is irregular. apparatus. (A) a first region disposed on the main surface of the semiconductor chip;
(B) a plurality of second regions formed by dividing the first region;
(C) a first wiring arranged for each of the plurality of second regions;
(D) a second wiring formed in a layer different from the first wiring and disposed in each of the plurality of second regions;
(E) a first detection circuit that detects a change in the predetermined first wiring in a predetermined first wiring among the first wirings in the second regions;
Have
The shapes of the first wiring and the second wiring arranged in the second region are different from each other, and the first detection circuit includes the predetermined first wiring to which the first detection circuit is connected. The semiconductor device is arranged so that a positional relationship with the second region having the irregularity is irregular.   57. The semiconductor device according to claim 56, wherein a second detection circuit that detects a change in the predetermined second wiring is formed in a predetermined second wiring among the second wirings in each of the second regions. A semiconductor device characterized by that.   58. The semiconductor device according to claim 56, wherein the first detection circuit is arranged such that a positional relationship with the second region having the first wiring to which the detection circuit is connected is irregular. A semiconductor device characterized by comprising:   59. The semiconductor device according to claim 56, wherein a plurality of the first detection circuits are electrically connected to the first wiring. The semiconductor device according to any one of claims 56 to 59,
At least one of the first wiring and the second wiring is a power supply voltage wiring for supplying a voltage to the integrated circuit of the semiconductor chip. In semiconductor devices,
(A) a first region disposed on the main surface of the semiconductor chip;
(B) a first wiring disposed in the first region;
(C) having a detection circuit for detecting processing of the first wiring;
In the first area, first wirings having different shapes are arranged, and the first wirings having different shapes are mixedly arranged in the same area of the first area. A semiconductor device, wherein a positional relationship with a first wiring to which a circuit is connected is irregular.

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