JP2006020191A - Fir filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set delay time by unit finer than 1/2 unit of a period of a clock used for sampling in an FIR filter. <P>SOLUTION: Filter response waveform data which is the filter response waveform data of the FIR filter with j tap, 1/2<SP>i</SP>oversampling and whose sampling timing is shifted by every 1/2<SP>k</SP>of an oversampling period is stored in a filter pattern storage memory 7 for each pattern which a signal with j bit structure can take. In addition, the one coupling an output of a counter 5 which counts an oversampling clock MCLK, output of an S/P converter 6 which converts an input signal x(n) into parallel data with j bit structure and a signal indicating to what extent the delay time is set to be outputted from a delay time setting means 4, is inputted in the filter pattern storage memory 7 as a read address and data stored in the address is outputted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an FIR (Finite Impulse Response) filter that can vary the delay time of a filter output with respect to an input signal, and in particular, the delay time can be varied in a finer unit than an oversampling clock cycle. The present invention relates to an FIR filter.

  Conventionally, in the field of wireless communication, FIR filters have been used in various circuits. As for the FIR filter, the input signal and the output signal have the relationship represented by the following expression (1), and the configuration shown in FIG. 8 is known, for example (for example, Patent Document 1, Non-Patent Document 1). reference).

y (n) = h (0) x (n)
+ H (1) x (n-1)
+ H (2) x (n-2)
......
+ H (N-1) x (n-N + 1) (1)

  In Expression (1), x (n) is an input signal, x (n−1), x (n−2),..., X (n−N + 1) is a signal obtained by delaying the input signal x (n). , Y (n) are output signals, and h (0) to h (N-1) are filter coefficients.

  Referring to FIG. 8, the conventional FIR filter includes an input terminal 100 to which an input signal x (n) is input, a clock terminal 101 to which a clock CLK is input, and (N−1) pieces of shift registers. Registers 102-1 to 102- (N-1), N multipliers 103-100 to 103- (N-1), an adder 104, a DFF (Delay Flip Flop) 105, and an output signal y ( n), and an output terminal 106 from which n) is output.

  A clock CLK corresponding to the symbol rate of the input signal x (n) is input to each of the registers 102-1 to 102- (N-1). Each of the registers 102-1 to 102- (N-1) holds a signal input according to the clock CLK and outputs the held signal to the subsequent stage.

  The multiplier 103-0 multiplies the input signal x (n) and the filter coefficient h (0), and the other multipliers 103-1 to 103- (N-1) respectively register 102-1 to 102- ( The output signal of (N-1) is multiplied by the filter coefficients h (1) to h (N-1).

  The adder 104 adds the output signals of the multipliers 103-0 to 103-(N−1), and the DFF 105 holds the output signal of the adder 104 according to the clock CLK.

  With the above operation, the output signal y (n) satisfying the relationship of the above formula (1) is output from the output terminal 106.

  By the way, depending on the usage form of the FIR filter, it may be necessary to make the delay time of the filter output variable with respect to the input signal. For example, in time division multiple access (TDMA), when the base station receives an uplink signal output from the FIR filter in the terminal at a fixed timing, the arrival timing of the uplink signal to the base station is determined at the base station. In order to match the reception timing of the climb signal, it is necessary to make the delay time of the filter output variable.

  As an FIR filter that makes the delay time of the filter output variable, for example, an FIR filter having a configuration as shown in FIG. 9 can be considered.

  The difference from the FIR filter shown in FIG. 8 is that the output signal of the DFF 105, 108 is output in accordance with the inverting circuit 107 that outputs the inverted clock obtained by inverting the clock CLK, the DFF 108 that holds the output signal of the DFF 105 according to the inverted clock, and the select signal SEL. A selector 109 for selecting any one of them is added. In FIG. 9, the same reference numerals as those in FIG. 8 denote the same parts.

Since the DFF 108 holds the output signal of the DFF 105 according to the inverted clock obtained by inverting the clock CLK, if the duty ratio of the clock CLK is 50%, the output signal of the DFF 108 is the period of the clock CLK with respect to the output signal of the DFF 105. Is delayed by 1/2 of this. Therefore, in the FIR filter shown in FIG. 9, when the output signal of the DFF 105 is selected by the selector 109, a signal without delay is output from the output terminal 106, and when the output signal of the DFF 108 is selected, the clock CLK A signal delayed by ½ of the period is output from the output terminal 106.
JP 2001-285030 A Supervised by Shigeo Sakurai, “Basics of Digital Signal Processing”, first edition, 7th edition, The Institute of Electronics, Information and Communication Engineers, June 1, 1997, p51-p52

  However, the FIR filter shown in FIG. 9 has a problem that the delay time can be changed only in half units of the clock cycle used for sampling.

  Accordingly, an object of the present invention is to enable the delay time to be set in units smaller than ½ unit of the period of the clock used for sampling.

The first FIR filter according to the present invention is:
A filter pattern storage memory storing filter response waveform data of an FIR filter that performs sampling with an oversampling clock having a tap number of j and a period of 1/2 ⁱ of the symbol rate, and can take a signal of j-bit configuration A filter pattern storage memory storing filter response waveform data in which the sampling timing is shifted by 1/2 ^{k of the} oversampling period for each pattern;
a delay time setting means for outputting a delay time setting signal having a k-bit configuration;
Read-out means for reading out the filter response waveform data specified by the tap output of j-bit configuration and the delay time setting signal of k-bit configuration output from the delay time setting means from the filter pattern storage memory It is characterized by.

The second FIR filter according to the present invention is:
A filter pattern storage memory in which an output value of an FIR filter that performs sampling with an oversampling clock having a number of taps of j and a cycle of 1/2 ⁱ of the symbol rate is stored, and each pattern that can be taken by a signal having a j-bit configuration A filter pattern storage memory in which each filter output value is stored when sampling is performed with 2 ^k kinds of oversampling clocks whose phases are different by 1/2 ^k each of the oversampling period;
a delay time setting means for outputting a delay time setting signal having a k-bit configuration;
2 ⁱ filter output values stored in the filter pattern storage memory, specified by a tap output having a j-bit configuration and a delay time setting signal having a k-bit configuration output from the delay time setting means, And a reading means for sequentially reading at an oversampling period.

The third FIR filter according to the present invention is:
A counter that counts an oversampling clock having a period of 1/2 ⁱ of the symbol rate of serial input data and outputs a count value of an i-bit configuration;
a delay time setting means for outputting a delay time setting signal having a k-bit configuration;
A serial / parallel converter for converting the serial input data into parallel data having a j-bit configuration;
A filter pattern storage memory in which an output value of an FIR filter that performs sampling with an oversampling clock having a number of taps of j and a cycle of ½ ⁱ of a symbol rate is stored, and has an i-bit configuration output from the counter (I + j + k) generated by concatenating the count value, the j-bit parallel data output from the serial-parallel converter, and the k-bit delay time setting signal output from the delay time setting means. A read address having a bit structure is input, and each memory area is a filter output value for the bit pattern of the parallel data corresponding portion in the address, and the phase is 2 ^k types having different phases by 1/2 ^{k of the} oversampling period Of the oversampling clock in the part corresponding to the delay time setting signal And a filter pattern storage memory storing a filter output value at a sampling timing indicated by a bit pattern of a count value corresponding portion when sampling is performed with an oversampling clock of the type indicated by .

The fourth FIR filter according to the present invention is:
The FIR filter according to claim 3, wherein
The count value corresponding part is arranged on the least significant bit side, the delay time setting signal corresponding part is arranged on the most significant bit side, and the parallel data corresponding part is the count value corresponding part and the delay time setting signal corresponding part It is arrange | positioned between.

According to the FIR filter of the present invention, the delay time of the filter output can be set in a unit finer than a unit of 1/2 of the clock cycle used for sampling. The reason is that it includes a filter pattern storage memory storing filter response waveform data whose sampling timing is shifted by 1/2 ^{k of the} oversampling period, and is included in the filter response waveform data whose sampling timing is shifted by the delay time setting signal. This is because any one of them is selected.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of an embodiment of an FIR filter according to the present invention. The FIR filter shown in the figure is a j-tap, 2 ⁱ oversampling FIR filter, and includes an input terminal 1, a clock terminal 2, an oversampling clock terminal 3, a delay time setting means 4, a counter 5, A serial / parallel (S / P) converter 6, a filter pattern storage memory 7, a register 8, and an output terminal 9 are included.

Serial input data x (n) is input to the input terminal 1. A clock CLK having a period (T) equal to the symbol rate of the serial input data x (n) is input to the clock terminal 2. An oversampling clock MCLK is input to the oversampling clock terminal 3. The period of the oversampling clock MCLK is 1/2 ⁱ of the period T of the clock CLK, that is, T / 2 ⁱ .

The delay time setting means 4 outputs a delay time setting signal having a k-bit configuration. In the FIR filter of this embodiment, 2 ^k types of delay times can be set according to the bit pattern of the delay time setting signal.

The counter 5 counts the oversampling clock MCLK and outputs an i-bit count value. Accordingly, the counter 5 cyclically outputs count values 0, 1,..., (2 ⁱ −1).

  The serial / parallel converter 6 converts the serial input data x (n) into j-bit parallel data according to the clock CLK.

  The filter pattern storage memory 7 has an (i + j + k) -bit address input, and the i-bit count value output from the counter 5 is input to the least significant bit (first bit) to the i-th bit. The (i + 1) to (i + j) bits are input with j-bit parallel data output from the serial / parallel converter 6, and the (i + j + 1) th to (i + j + k) bits are the delay time setting means 4. A delay time setting signal having a k-bit configuration output from the terminal is input. In the following description, the portion corresponding to the count value output from the counter 5, the portion corresponding to the parallel data output from the serial / parallel converter 6 and the delay time setting means in the address of the filter pattern storage memory 7 The portions corresponding to the delay time setting signal output from 4 are referred to as a count value corresponding portion, a parallel data corresponding portion, and a delay time setting signal corresponding portion, respectively.

Further, the following data is stored in each memory area of the filter pattern storage memory 7 when the time response function of the FIR filter is F (t). The response waveform of F (t) when the bit pattern corresponding to the pattern data is input to the memory area where the delay time setting signal corresponding part = 0 (bit pattern is all “0”) and 2 ⁱ oversampling is performed. However, in the memory area where the delay time setting signal corresponding part = 1 (only the least significant bit of the bit pattern is “1”), the bit pattern corresponding to the pattern data is input and the F when 2 ⁱ oversampling is performed. The response waveform of (t−1 / (2 ⁱ × 2 ^k )) is a delay time setting signal corresponding portion = 2 ^k −1 (bit pattern is all “1”). The response waveform of F (t− (2 ^k −1) / (2 ⁱ × 2 ^k )) when 2 ⁱ oversampling is performed is stored.

In other words, each memory area of the filter pattern storage memory 7 has a filter output value for the bit pattern corresponding to the parallel data in the address that specifies the memory area, and the phase of the oversampling period. Sampling indicated by the bit pattern of the count value corresponding portion when sampling is performed with the oversampling clock of the type indicated by the delay time setting signal corresponding portion of the 2 ^k types of oversampling clocks that differ by 1/2 ^k. The filter output value at the timing is stored.

For example, when i = 2, j = 5, and k = 2, each memory area of the filter pattern storage memory 7 includes bits corresponding to parallel data in a 9-bit address that specifies the memory area. A filter output value having a pattern (bit pattern of the third bit to the seventh bit) as an input, and the phase differs by 1/2 ^k = 1/4 of the oversampling period T / 4, as shown in FIG. Corresponding to the count value when sampling is performed with the type of oversampling indicated by the delay time setting signal corresponding part (8th and 9th bits) of 2 ^k = 4 types of oversampling clocks shown in (D) The filter output value in the sampling order indicated by the portion (first and second bits) is stored.

  FIG. 3 is a diagram showing an example of the contents of the filter pattern storage memory 7 when i = 2, j = 5, and k = 2. FIG. 3 shows an example of the contents only for the memory area whose bit pattern corresponding to the parallel data is “00100”. Referring to the figure, addresses “0000010000” to “000010011” store the filter output value of the delay time “0 period” when the output of the serial / parallel converter 6 is “00100”. Also, the addresses “0110010000” to “010010011” have the filter output value of the delay time “T / 16 period” and the addresses “100010000” to “100010011” when the output of the serial-parallel converter 6 is “00100”. Is the filter output value of the delay time “2T / 16 period” when the output of the serial-parallel converter 6 is “00100”, and the output of the serial-parallel converter 6 is “1100010011”. A filter output value of delay time “3T / 16 period” at 00100 ″ is stored.

  The register 8 holds the m-bit filter output value output from the filter pattern storage memory 7 with the oversampling clock MCLK.

A filter output value of 2 ^m gradation is output from the output terminal 9.

[Description of Operation of Embodiment]
Next, the operation of the present embodiment will be described in detail. In the following description, i = 2 (4 times sampling), j = 5 (5 taps), and k = 2.

  The serial / parallel converter 6 converts the serial input data x (n) into parallel data having a 5-bit configuration in accordance with a clock CLK having a period T. The counter 5 counts the oversampling clock MCLK having a cycle T / 4 that is ¼ of the clock CLK, and cyclically outputs count values “00” to “11” having a 2-bit configuration. The delay time setting means 4 outputs a delay time setting signal having a 2-bit configuration.

  Of the address inputs of the filter pattern storage memory 7, the count value output from the counter 5 is input to the first and second bits, and the serial to parallel converter 6 outputs the third to seventh bits. Parallel data is input, and a delay time setting signal output from the delay time setting means 4 is input to the eighth and ninth bits. The filter pattern storage memory 7 outputs the filter output value stored in the memory area specified by the input address.

  For example, suppose that the parallel data “00100” is output from the serial / parallel converter 6 and the bit pattern “00” indicating the delay time “0 cycle” is output from the delay time setting unit 4 as the delay time setting signal. The filter output values a, b, c, and d stored in the addresses “0000010000”, “000000011”, “0000100101”, and “000010011” of the filter pattern storage memory 7 are sequentially read. A filter output waveform as shown in FIG. 4 appears.

  Further, for example, the parallel data identical to the above-mentioned parallel data “00100” is output from the serial / parallel converter 6, and the bit pattern “indicating the delay time“ T / 16 period ”as a delay time setting signal from the delay time setting means 4. Assuming that “01” is output, the filter output values a, b, c, and d stored in the addresses “0110010000”, “01001001”, “010010010”, “01001001” in the filter pattern storage memory 7 are sequentially read. As a result, a filter output waveform as shown in FIG.

  Further, the parallel data “00100” is output from the serial / parallel converter 6, and the bit pattern “10” indicating the delay time “2T / 16 period” is output as the delay time setting signal from the delay time setting unit 4. Then, the filter output values a, b, c, and d stored in the addresses “100010000”, “100010001”, “100010010”, and “100010011” of the filter pattern storage memory 7 are sequentially read out to the output terminal 9. Shows a filter output waveform as shown in FIG.

  Further, the parallel data identical to the parallel data “00100” described above is output from the serial / parallel converter 6, and the bit pattern “11” indicating the delay time “3T / 16 period” as the delay time setting signal from the delay time setting means 4. Is output, the filter output values a, b, c, and d stored in the addresses “1110010000”, “1100010001”, “1100010010”, and “10010011” of the filter pattern storage memory 7 are sequentially read out. A filter output waveform as shown in FIG.

  As described above, according to the present embodiment, by switching the bit pattern of the delay time setting signal between “00”, “01”, “10”, and “11”, the delay time for the input signal of the filter output is changed to “ It is possible to switch to “0 cycle”, “T / 16 cycle”, “2T / 16 cycle”, and “3T / 16 cycle”.

It is a block diagram which shows the structural example of embodiment of the FIR filter concerning this invention. It is a figure which shows four types of oversampling clock which shifted the delay time by T / 16. It is a figure which shows the example of the content of the filter pattern storage memory. It is a figure which shows a filter output waveform when delay time is made into "0 period." It is a figure which shows a filter output waveform when delay time is made into "T / 16 period." It is a figure which shows a filter output waveform when delay time is made into "2T / 16 period." It is a figure which shows a filter output waveform when delay time is set to "3T / 16 period." It is a block diagram which shows the structural example of the conventional FIR filter. FIG. 9 is a block diagram illustrating a configuration example when the delay time can be changed in the FIR filter of FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Input terminal 2 ... Clock terminal 3 ... Oversampling clock terminal 4 ... Delay time setting means 5 ... Counter 6 ... Serial parallel converter 7 ... Filter pattern storage memory 8 ... Buffer 9 ... Output terminal

Claims (4)

A filter pattern storage memory storing filter response waveform data of an FIR filter that performs sampling with an oversampling clock having a tap number of j and a period of 1/2 ⁱ of the symbol rate, and can take a signal of j-bit configuration A filter pattern storage memory storing filter response waveform data in which the sampling timing is shifted by 1/2 ^{k of the} oversampling period for each pattern;
a delay time setting means for outputting a delay time setting signal having a k-bit configuration;
Read-out means for reading out the filter response waveform data specified by the tap output of j-bit configuration and the delay time setting signal of k-bit configuration output from the delay time setting means from the filter pattern storage memory FIR filter characterized by the above. A filter pattern storage memory in which an output value of an FIR filter that performs sampling with an oversampling clock having a number of taps of j and a cycle of 1/2 ⁱ of the symbol rate is stored, and each pattern that can be taken by a signal having a j-bit configuration A filter pattern storage memory in which each filter output value is stored when sampling is performed with 2 ^k kinds of oversampling clocks whose phases are different by 1/2 ^k each of the oversampling period;
a delay time setting means for outputting a delay time setting signal having a k-bit configuration;
2 ⁱ filter output values stored in the filter pattern storage memory, specified by a tap output having a j-bit configuration and a delay time setting signal having a k-bit configuration output from the delay time setting means, A FIR filter comprising reading means for sequentially reading at an oversampling period. A counter that counts an oversampling clock having a period of 1/2 ⁱ of the symbol rate of serial input data and outputs a count value of an i-bit configuration;
a delay time setting means for outputting a delay time setting signal having a k-bit configuration;
A serial / parallel converter for converting the serial input data into parallel data having a j-bit configuration;
A filter pattern storage memory in which an output value of an FIR filter that performs sampling with an oversampling clock having a number of taps of j and a cycle of ½ ⁱ of a symbol rate is stored, and has an i-bit configuration output from the counter (I + j + k) generated by concatenating the count value, the j-bit parallel data output from the serial-parallel converter, and the k-bit delay time setting signal output from the delay time setting means. A read address having a bit structure is input, and each memory area is a filter output value for the bit pattern of the parallel data corresponding portion in the address, and the phase is 2 ^k types having different phases by 1/2 ^{k of the} oversampling period Of the oversampling clock in the part corresponding to the delay time setting signal And a filter pattern storage memory storing a filter output value at a sampling timing indicated by a bit pattern of a count value corresponding portion when sampling is performed with an oversampling clock of the type indicated by FIR filter. The FIR filter according to claim 3, wherein
The count value corresponding part is arranged on the least significant bit side, the delay time setting signal corresponding part is arranged on the most significant bit side, and the parallel data corresponding part is the count value corresponding part and the delay time setting signal corresponding part An FIR filter characterized by being arranged between the two.

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