JP2006140193A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which circuit component members are composed of a layer common to a connection conductive layer between a pad electrode and a bump electrode, and the connection conductive layer can be employed for other uses in order to enhance cost performance, and to provide its fabrication process. <P>SOLUTION: On the pad electrode 11 of a semiconductor chip 10 in which an electronic circuit is formed and having the pad electrode 11 on the surface, a connection conductive layer is formed and a bump electrode 18 is formed on the upper layer thereof. A layer common to the connection conductive layer is formed on the semiconductor chip 10 and circuit component members, e.g. a resistive element R, are formed to be connected with the connection conductive layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a packaged semiconductor device having bumps (projection electrodes) connected to an electronic circuit provided on a semiconductor chip and a manufacturing method thereof.

  In recent years, electronic products such as mobile phones and PDAs (personal digital assistants) have been reduced in size, thickness, and weight so that they are convenient to carry. While semiconductor devices have been reduced by 70% in three years, electronic circuit devices in which such semiconductor devices are mounted on a printed wiring board can also be used to mount components on a mounting board (printed wiring board). Research and development has been conducted as an important issue on how to increase the density.

  For example, the package form of a semiconductor device has shifted from a lead insertion type such as DIP (Dual Inline Package) to a surface mount type, and for further miniaturization of a semiconductor device, a semiconductor bare chip called flip chip mounting is used. A method in which bumps are formed on the substrate and mounted directly on the substrate face down is effective.

  The bumps mainly include solder bumps and gold bumps, and both are generally formed by electrolytic plating. For this purpose, a seed layer called an under bump metal (hereinafter also referred to as a UBM film) for supplying power during plating is necessary. The UBM film also functions as a connection conductive layer that connects the pad electrode and bump of the semiconductor chip.

  In the conventional technique, as described in Patent Document 1, since the bump height after plating is as high as 10 μm or more, there is a step in the wafer. For this reason, the UBM film is patterned. It was difficult. For this reason, after the plating process is completed, the exposed UBM film portion is removed by etching using the bump as a mask.

In such a method, the UBM film has only two roles for supplying power during electroplating and as an adhesive layer between the aluminum pad electrode and the bump, resulting in poor cost performance. It was.
JP 09-186163 A

  The problem to be solved is that in the prior art, the UBM film can only be removed except for the portion connecting the pad electrode and the bump, and the cost performance is poor.

  The semiconductor device of the present invention includes an electronic circuit formed thereon, a semiconductor chip having a pad electrode on the surface, a connection conductive layer formed on the pad electrode, a protruding electrode formed on the connection conductive layer, A circuit composing member formed on the semiconductor chip, including a common layer with the connection conductive layer, connected to the connection conductive layer;

  In the semiconductor device of the present invention described above, an electronic circuit is formed, a connection conductive layer is formed on a pad electrode of a semiconductor chip having a pad electrode on the surface, and a protruding electrode is formed on the upper layer. On the semiconductor chip, a circuit constituent member that includes a layer common to the connection conductive layer and is connected to the connection conductive layer is formed.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a conductive layer over the entire surface of a semiconductor chip having an electronic circuit formed thereon and having a pad electrode on the surface; And patterning the conductive layer to leave the conductive layer and patterning the conductive layer so as to include a common layer with the connection conductive layer in the circuit component forming region. Forming a circuit component connected to the layer, and forming a protruding electrode on the connection conductive layer.

  In the method for manufacturing a semiconductor device according to the present invention, an electronic circuit is formed, and a conductive layer is formed on the entire surface of a semiconductor chip having a pad electrode on the surface and covering the pad electrode. Next, a connection conductive layer is formed by patterning so as to leave a conductive layer on the pad electrode. In this step, a circuit component that is connected to the connection conductive layer is formed by patterning the conductive layer so as to include a common layer with the connection conductive layer in the circuit component formation region. Next, a protruding electrode is formed on the connection conductive layer.

  In the semiconductor device of the present invention, the circuit constituent member is composed of a common layer with the connection conductive layer (UBM film) between the pad electrode and the protruding electrode, and the connection conductive layer is effectively used for other applications. The cost performance of the connection conductive layer can be improved.

  In the method for manufacturing a semiconductor device of the present invention, a circuit constituent member is formed from a common layer with a connection conductive layer (UBM film) formed between a pad electrode and a protruding electrode, and the connection conductive layer is effectively used for other applications. Therefore, the cost performance of the connection conductive layer can be improved.

  Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1A is a plan view of a pad electrode side of a semiconductor device according to this embodiment, and FIG. 1B is an enlarged cross-sectional view taken along line AA ′ in FIG. .
For example, a pad electrode 11 made of aluminum or the like is formed on the surface of a semiconductor chip 10 on which an electronic circuit is formed, and a passivation film 12 made of silicon oxide or the like is formed on portions other than the pad electrode.
For example, a chrome layer 13 that is a high-resistance layer and a copper layer 14 that is a low-resistance layer are stacked in this order on the pad electrode 11 to form a connection conductive layer UBM.
In addition, for example, a nickel layer 15 and a gold layer 16 are laminated in this order on the connection conductive layer UBM to form a barrier metal layer BM.
Further, the region excluding the barrier metal layer BM is covered with a protective layer 17 made of photosensitive polyimide or the like, and a bump (projection electrode) 18 made of solder or the like is formed on the barrier metal layer BM.

In addition, the resistance element R, which is a circuit constituent member, is composed of the chromium layer 13p that is a layer common to the chromium layer 13 that constitutes the connection conductive layer UBM, and is patterned by extending from the pad electrode region to the outside. ing. Both ends of the resistance element R are connected to the bumps 18 as terminals via the connection conductive layer UBM (the chromium layer 13 and the copper layer 14).
Here, as shown in FIG. 1A, the chromium layer 13p serving as the resistance element R can be set to a desired resistance value by securing a distance connecting the two bumps by reciprocating a predetermined distance several times. it can. Further, the layout may be such that the two bumps are connected with the shortest distance in accordance with the resistivity of the material constituting the high resistance layer.

  The bump and pad electrodes are connected to an electronic circuit provided on the semiconductor chip, but are not connected to an electronic circuit in the semiconductor chip, but are connected to a circuit outside the chip as a mere terminal of the resistance element R. It may be configured to.

Further, in the present embodiment, the resistance element is constituted by the chromium layer of the high resistance layer, but the fuse can be constituted by using a material that is cut when a predetermined current flows.
Moreover, the structure which has a resistance element and a fuse simultaneously may be sufficient.

  The semiconductor device of the present embodiment described above uses a chromium layer having a higher resistance among the connection conductive layers provided between the pad electrode and the bump on the semiconductor chip, and / or a resistance element that is a circuit constituent member and / or The fuse is configured, and the connection conductive layer can be effectively used for other purposes as, for example, a resistance element or a fuse, so that the cost performance of the connection conductive layer can be improved.

Second Embodiment FIG. 2A is a plan view of a pad electrode side of a semiconductor device according to this embodiment, and FIG. 2B is an enlarged cross-sectional view taken along line AA ′ in FIG. .
As in the first embodiment, a pad electrode 11 is formed on the surface of the semiconductor chip 10 in the pad electrode formation region, and a connection conductive layer UBM composed of a chromium layer 13 and a copper layer 14, a nickel layer 15, and A barrier metal layer BM made of a gold layer 16 and bumps 18 made of solder or the like are formed.

In the present embodiment, the chrome layer 13 and the copper layer 14 constituting the connection conductive layer UBM are the same layer, and the chrome layer 13p and the copper layer 14p that are patterned by extending outward from the pad electrode region are used. A coil L, which is a circuit constituent member, is configured. Both ends of the coil L are connected to bumps 18 which are terminals via connection conductive layers UBM (chrome layer 13 and copper layer 14).
Here, as shown in FIG. 2A, the chromium layer 13p and the copper layer 14p serving as the coil L are laid out in a spiral shape and can be set to a desired inductance value.

  The bump and pad electrodes are connected to an electronic circuit provided in the semiconductor chip, but are not connected to the electronic circuit in the semiconductor chip, but are connected to a circuit outside the chip as a mere terminal of the coil L. It may be a configuration.

Further, in this embodiment, the coil is formed by processing spirally from the chromium layer of the high resistance layer and the copper layer of the low resistance layer, but a simple wiring can be formed instead of the spiral layout. .
Moreover, the structure which has a coil and wiring simultaneously may be sufficient.

  The semiconductor device of the present embodiment described above is a coil that is a circuit constituent member using a high-resistance chromium layer and a low-resistance copper layer among the connection conductive layers provided between the pad electrode and the bump on the semiconductor chip. And / or wiring is comprised and the connection conductive layer can be used effectively for other uses, and the cost performance of the connection conductive layer can be improved.

Third Embodiment FIG. 3A is a plan view of a pad electrode side of a semiconductor device according to the present embodiment, and FIG. 3B is an enlarged cross-sectional view taken along line AA ′ in FIG. .
As in the first embodiment, a pad electrode 11 is formed on the surface of the semiconductor chip 10 in the pad electrode formation region, and a connection conductive layer UBM composed of a chromium layer 13 and a copper layer 14, a nickel layer 15, and A barrier metal layer BM made of a gold layer 16 and bumps 18 made of solder or the like are formed.

In the present embodiment, the chrome layer 13 and the copper layer 14 constituting the connection conductive layer UBM are the same layer, and the chrome layer 13p and the copper layer 14p that are patterned by extending outward from the pad electrode region are used. The electrode E, which is a circuit constituent member, is configured. The electrode E is connected to a plurality of bumps 18g which are terminals via the connection conductive layer UBM (the chromium layer 13 and the copper layer 14).
For example, as shown in FIG. 3A, the chromium layer 13p and the copper layer 14p serving as the electrode E are formed on the entire surface including the bump 18g for ground except for the portion of the signal bump 18s not connected to the electrode E. Is formed. Moreover, you may make it coat | cover only a part of surface by the side of the pad electrode of a semiconductor chip.
When a ground potential is applied to the electrode E as described above, it can function as a shield electrode.

In the above description, the case where the ground potential is applied to the electrode E has been described. However, when the power supply potential is applied to the electrode E, the power supply of the semiconductor device can be stabilized.
Furthermore, it covers a predetermined area on the pad electrode side of the semiconductor chip, and also functions as a protective member that prevents the electrode formation region from being damaged when an impact is applied.

  The bump and pad electrodes are connected to an electronic circuit provided on the semiconductor chip, but are not connected to an electronic circuit in the semiconductor chip, but are connected to a circuit outside the chip as a mere terminal of the electrode E. It may be a configuration.

  In the conventional method, since the chip is mounted face down, crosstalk noise from the active part on the chip surface easily jumps into the substrate after mounting. However, in this embodiment, the pad By using the electrode formed on the electrode surface as a shield electrode, crosstalk noise can be prevented.

  The semiconductor device of the present embodiment described above uses a high resistance chromium layer and a low resistance copper layer among the connection conductive layers provided between the pad electrode and the bump on the semiconductor chip, and is a shield that is a circuit constituent member. An electrode such as an electrode is formed, and the connection conductive layer is effectively used for other applications, so that the cost performance of the connection conductive layer can be improved.

Fourth Embodiment A semiconductor device according to this embodiment is appropriately selected from the resistance element and fuse shown in the first embodiment, the coil and wiring shown in the second embodiment, and the electrode shown in the third embodiment. A semiconductor device having a circuit component.
Any of these circuit components can be configured using a common layer with the connection conductive layer as described above, and the cost performance of the connection conductive layer can be improved.

  In the conventional method, even in the case of a circuit in which the semiconductor chip and the resistor and the coil must be arranged at a short distance, the resistor element and the coil must be arranged on the mounting substrate, and the frequency characteristics are deteriorated. However, in the present embodiment, it is possible to provide a resistance element, a coil, or the like close to the semiconductor chip, so that deterioration of the frequency characteristics can be prevented.

Fifth Embodiment Next, the circuit component member is left together with the high resistance chromium layer and the low resistance copper layer constituting the connection conductive layer, such as the coil, wiring, or electrode described in the above embodiment. A method for manufacturing a semiconductor device for pattern formation will be described with reference to the drawings.

First, as shown in the sectional view of FIG. 4A, a pad electrode 11 made of aluminum or the like is formed on a semiconductor chip 10 on which an electronic circuit is formed.
Next, a passivation film 12 is formed by depositing silicon oxide or the like by, for example, a CVD (chemical vapor deposition) method.
Next, a resist film having a pattern for opening the pad electrode portion is patterned, and etching such as dry etching is performed to open the pad electrode 11 portion in the passivation film 12. Thereafter, the resist film is removed.
Further, the oxide or the like on the surface of the pad electrode 11 is removed by a reverse sputtering method so that a clean surface of the pad electrode 11 appears.

Next, as shown in the cross-sectional view of FIG. 4B, a chromium layer 13 and a copper layer 14 to be the connection conductive layer UBM are laminated in this order on the entire surface including the pad electrode 11 by sputtering, for example.
When both the high resistance chromium layer and the low resistance copper layer are left as circuit components as in this embodiment, the thickness of the chromium layer 13 is, for example, about 0.2 μm, and the thickness of the copper layer 14 is For example, it is about 1.0 μm.

  Next, as shown in the cross-sectional view of FIG. 4C, a plating resist film is formed to a thickness of about 7 to 10 μm by, for example, a spin coating method, and the pad electrode region is opened by a photolithography process. Exposure and development are performed to form a pattern of a plating resist film R1 for electrolytic nickel plating and flash electrolytic gold plating in the next step.

  Next, as shown in the cross-sectional view of FIG. 5A, an electrolytic nickel plating process using the connection conductive layer UBM as a seed layer is performed, and 3-5 μm above the copper layer 14 in the opening of the plating resist film R1. A nickel layer 15 having a film thickness of about a degree is formed.

  Next, as shown in the cross-sectional view of FIG. 5B, a flash electrolytic gold plating process using the connection conductive layer UBM as a seed layer is performed, and 0.03 μm above the nickel layer 15 in the opening of the plating resist film R1. A gold layer 16 for preventing oxidation is formed.

Next, as shown in the cross-sectional view of FIG. 5C, the plating resist film is removed by solvent treatment, for example.
As described above, the barrier metal layer BM including the nickel layer 15 and the gold layer 16 is formed on the connection conductive layer UBM in the pad electrode region.

Next, as shown in FIG. 6B, which is a plan view of FIG. 6A and an enlarged sectional view taken along line AA ′ in FIG. 6A, the barrier metal film BM in the pad electrode region is protected. Then, a resist film R2 is patterned as an etching mask for the copper layer 14 opened in a predetermined pattern.
The resist film R2 is formed in a pattern that protects a portion to be left as a copper layer and opens a portion from which the copper layer is removed. In this embodiment, since the chromium layer and the copper layer are left in a predetermined pattern, the copper layer is left along this pattern.
The drawing shows that the copper layer 14 to be removed is exposed from the opening of the resist film R2.

Next, as shown in FIG. 7B, which is a plan view of FIG. 7A and an enlarged sectional view taken along line AA ′ in FIG. 7A, a commercially available etching solution is used with the resist film R2 as a mask. Etching treatment such as wet etching using is performed to remove the copper layer 14 exposed from the opening of the resist film R2, and the copper layer 14 is patterned.
The drawing shows that the lower chromium layer 13 is exposed from the opening 14a of the lower copper layer 14 of the resist film R2.

Next, as shown in FIG. 8B, which is a plan view of FIG. 8A and an enlarged cross-sectional view taken along the line AA ′ in FIG. 8A, the resist film R2 is removed by, for example, a solvent treatment.
In the drawing, the lower chromium layer 13 is exposed from the opening 14 a of the copper layer 14.

Next, as shown in FIG. 9B, which is a plan view of FIG. 9A and an enlarged sectional view taken along line AA ′ in FIG. 9A, the barrier metal film BM in the pad electrode region is protected. Then, a resist film R3 is patterned as an etching mask for the chromium layer 13 that opens in a predetermined pattern.
The resist film R3 is formed in a pattern that protects a portion to be left as a chromium layer and opens a portion from which the chromium layer is removed. In the present embodiment, since the chromium layer and the copper layer are left in a predetermined pattern, the chromium layer is left along this pattern.
In the drawing, it is shown that the chromium layer 13 to be removed is exposed from the opening of the resist film R3. In this embodiment, the resist is formed so as to be opened in a pattern narrower than the opening 14a of the copper layer 14. The film R3 is patterned.

Next, as shown in FIG. 10B, which is a plan view of FIG. 10A and an enlarged cross-sectional view taken along the line AA ′ in FIG. 10A, a diluted hydrofluoric acid aqueous solution with the resist film R3 as a mask. Etching treatment such as wet etching using the above is performed to remove the portion of the chromium layer 13 exposed from the opening of the resist film R3, and the chromium layer 13 is patterned.
In the drawing, the lower passivation film 12 is exposed from the opening 13 a of the chromium layer 13.

Next, as shown in FIG. 11B, which is a plan view of FIG. 11A and an enlarged cross-sectional view taken along line AA ′ in FIG. 11A, the resist film R3 is removed by, for example, a solvent treatment.
In the drawing, the lower chromium layer 13 is exposed from the opening 14 a of the copper layer 14, and the lower passivation film 12 is exposed from the opening 13 a of the chromium layer 13.

  Next, as shown in the cross-sectional view of FIG. 12A, photosensitive polyimide (HD7010) is applied to the entire surface by a method such as spin coating, for example, to form a protective layer 17 having a thickness of 7 to 10 μm, for example. . An opening reaching the pad electrode region (barrier metal layer forming region) is formed in the protective layer 7 by processing such as pattern exposure and development.

Next, as shown in the cross-sectional view of FIG. 12B, for example, a flux is applied onto the barrier metal layer BM exposed at the opening of the protective layer 17, a solder ball is mounted, a reflow process is performed, and the flux The solder ball bumps 18 are formed on the barrier metal layer BM.
The solder ball is, for example, 350 μm in diameter and is Sn-3.0Ag-0.5Cu lead-free solder.

  In the manufacturing method of the semiconductor device of the present embodiment, a circuit constituent member such as a coil, a wiring, or an electrode is formed from a layer common to the connection conductive layer formed between the pad electrode and the protruding electrode, and the connection conductive layer is formed. Since it can be used for other applications, the cost performance of the connection conductive layer can be improved.

  In the semiconductor device manufacturing method of the present embodiment, since the thickness of the barrier metal film (nickel layer and gold layer) formed on the connection conductive layer is 10 μm or less, the connection conductive layer is patterned. In this process, the connection conductive layer can be easily patterned without the barrier metal layer being in the way.

Sixth Embodiment Next, in the above-described embodiment, a circuit configuration is left with the high resistance layer of the high resistance chromium layer and the low resistance copper layer constituting the connection conductive layer UBM as in the resistance element and the fuse. A method for manufacturing a semiconductor device in the case of patterning members will be described.

First, in the same manner as in the fifth embodiment, the pad electrode 11 and the passivation film 12 are formed on the semiconductor chip 10, and the chromium layer 13 and the copper layer 14 that become the connection conductive layer UBM are laminated on the entire surface in this order, and further connected On the upper layer of the conductive layer UBM, a nickel layer 15 and a gold layer 16 to be a barrier metal layer BM are laminated in this order in a predetermined pattern.
When only the high-resistance chrome layer is left as a circuit component as in this embodiment, the film thickness of the chrome layer 13 is, for example, about 0.8 μm. The film thickness of the copper layer 14 is not particularly limited, but is about 1.0 μm, for example.

Next, as shown in the plan view of FIG. 13A, a resist film is patterned as a copper layer etching mask, an etching process is performed to pattern the copper layer 14, and then the resist film is removed.
FIG. 13A shows a state in which only the chromium layer is left as a circuit component, so that the copper layer 14 is removed and the chromium layer 13 is exposed in the circuit formation region.

Next, as shown in the plan view of FIG. 13B, a resist film for a chromium layer etching mask is formed by patterning, an etching process is performed to pattern the chromium layer 13, and then the resist film is removed.
FIG. 13B shows a state in which the passivation layer 12 is exposed from the opening from which the chromium layer 13 is patterned and the chromium layer is removed.
In the subsequent steps, a protective film is formed and bumps are formed in the same manner as in the fifth embodiment, whereby a desired semiconductor device can be obtained.

  In the manufacturing method of the semiconductor device of the present embodiment described above, a circuit constituent member such as a resistance element or a fuse is formed from a layer common to the connection conductive layer formed between the pad electrode and the protruding electrode, and the connection conductive layer is replaced with another layer. Therefore, the cost performance of the connection conductive layer can be improved.

According to the semiconductor device and the manufacturing method thereof of the present embodiment, the following effects can be enjoyed.
1. Resistive elements, coils, and the like and the semiconductor chip can be arranged quite close to each other, which is advantageous in terms of characteristics.
2. Since a circuit such as a resistor element + coil + fuse + ground electrode can be formed on the semiconductor chip, a semiconductor device with high added value can be manufactured as compared with a semiconductor device using a normal bump forming method.
3. Since the ground electrode can be formed on the active surface, it is possible to take measures against crosstalk noise.
4). When a solid pattern is arranged on the surface of the semiconductor chip as the ground electrode, the surface can be protected from scratches from the outside.

The present invention is not limited to the above description.
For example, although a resistance element, a fuse, a coil, a wiring, and an electrode are shown as circuit constituent members, members other than those described above can be used as long as they are configured using a film common to the connection conductive layer.
In addition to the solder ball bumps, gold bumps can be used as the bumps.
In addition, various modifications can be made without departing from the scope of the present invention.

The semiconductor device of the present invention can be applied to a packaged semiconductor device having bumps and mounted face-down.
In addition, the semiconductor device manufacturing method of the present invention can be applied to manufacturing a packaged semiconductor device having bumps and mounting face down.

FIG. 1A is a plan view on the pad electrode side of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is an enlarged cross-sectional view taken along line AA ′ in FIG. . 2A is a plan view of the pad electrode side of the semiconductor device according to the second embodiment of the present invention, and FIG. 2B is an enlarged cross-sectional view taken along line AA ′ in FIG. . FIG. 3A is a plan view of the pad electrode side of the semiconductor device according to the third embodiment of the present invention, and FIG. 3B is an enlarged cross-sectional view taken along line AA ′ in FIG. . 4A to 4C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fifth embodiment of the present invention. FIGS. 5A to 5C are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the fifth embodiment of the present invention. FIG. 6A is a plan view showing a manufacturing process of a semiconductor device according to the fifth embodiment of the present invention, and FIG. 6B is an enlarged cross-sectional view taken along line AA ′ in FIG. . FIG. 7A is a plan view showing a manufacturing process of a semiconductor device according to the fifth embodiment of the present invention, and FIG. 7B is an enlarged cross-sectional view taken along line AA ′ in FIG. . FIG. 8A is a plan view showing a manufacturing process of a semiconductor device according to the fifth embodiment of the present invention, and FIG. 8B is an enlarged cross-sectional view taken along line AA ′ in FIG. . FIG. 9A is a plan view showing a manufacturing process of a semiconductor device according to the fifth embodiment of the present invention, and FIG. 9B is an enlarged cross-sectional view taken along line AA ′ in FIG. 9A. . FIG. 10A is a plan view showing a manufacturing process of a semiconductor device according to the fifth embodiment of the present invention, and FIG. 10B is an enlarged cross-sectional view taken along line AA ′ in FIG. . FIG. 11A is a plan view showing a manufacturing process of a semiconductor device according to the fifth embodiment of the present invention, and FIG. 11B is an enlarged cross-sectional view taken along line AA ′ in FIG. . FIG. 12A and FIG. 12B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fifth embodiment of the present invention. FIG. 13A and FIG. 13B are plan views showing manufacturing steps of the semiconductor device according to the sixth embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip, 11 ... Pad electrode, 12 ... Passivation film | membrane, 13, 13p ... Chrome layer, 13a ... Opening part, 14, 14p ... Copper layer, 14a ... Opening part, 15 ... Nickel layer, 16 ... Gold layer, 17 ... Protective layer, 18, 8g ... Bump, BM ... Barrier metal layer, R ... Resistance element, L ... Coil, E ... Electrode, R1-R3 ... Resist film, UBM ... Connection conductive layer (connection conductive layer)

Claims (16)

A semiconductor chip on which an electronic circuit is formed and having a pad electrode on the surface;
A connection conductive layer formed on the pad electrode;
A protruding electrode formed on the connection conductive layer;
A semiconductor device comprising: a circuit component formed on the semiconductor chip, including a common layer with the connection conductive layer, connected to the connection conductive layer. The semiconductor device according to claim 1, wherein the circuit constituent member includes a resistance element and / or a fuse. The connection conductive layer includes a low resistance layer and a high resistance layer,
The semiconductor device according to claim 2, wherein the resistance element and / or the fuse is configured from the high resistance layer. The semiconductor device according to claim 1, wherein the circuit constituent member includes a coil and / or a wiring. The connection conductive layer includes a low resistance layer and a high resistance layer,
The semiconductor device according to claim 4, wherein the coil and / or the wiring is constituted by the low resistance layer and the high resistance layer. The semiconductor device according to claim 1, wherein the circuit constituent member includes an electrode. The connection conductive layer includes a low resistance layer and a high resistance layer,
The semiconductor device according to claim 6, wherein the electrode includes the low resistance layer and the high resistance layer. The semiconductor device according to claim 1, further comprising a barrier metal layer between the connection conductive layer and the protruding electrode. Forming a conductive layer over the entire surface of the semiconductor chip on which the electronic circuit is formed and having a pad electrode on the surface;
The connection conductive layer is formed by patterning so as to leave the conductive layer on the pad electrode, and the conductive layer is patterned so as to include a common layer with the connection conductive layer in the circuit component forming region. Forming a circuit component to be connected to the connection conductive layer;
Forming a protruding electrode on the connection conductive layer;
A method for manufacturing a semiconductor device comprising: The method for manufacturing a semiconductor device according to claim 9, wherein in the step of forming the circuit constituent member, a resistance element and / or a fuse is formed as the circuit constituent member. In the step of forming the conductive layer, a low resistance layer and a high resistance layer are laminated and formed,
The method of manufacturing a semiconductor device according to claim 10, wherein in the step of forming the circuit constituent member, the resistance element and / or the fuse is formed from the high resistance layer. The method for manufacturing a semiconductor device according to claim 9, wherein a coil and / or a wiring is formed as the circuit constituent member in the step of forming the circuit constituent member. In the step of forming the conductive layer, a low resistance layer and a high resistance layer are laminated and formed,
In the step of forming the circuit constituent member, the coil and / or wiring is formed from the low resistance layer and the high resistance layer.
A method for manufacturing a semiconductor device according to claim 12. The method for manufacturing a semiconductor device according to claim 9, wherein an electrode is formed as the circuit constituent member in the step of forming the circuit constituent member. In the step of forming the conductive layer, a low resistance layer and a high resistance layer are laminated and formed,
In the step of forming the circuit constituent member, the electrode is formed from the low resistance layer and the high resistance layer.
The method for manufacturing a semiconductor device according to claim 14. A step of forming a barrier metal layer on the connection conductive layer between the step of forming the connection conductive layer and the step of forming the protruding electrode;
The method for manufacturing a semiconductor device according to claim 9, wherein in the step of forming the protruding electrode, the protruding electrode is formed on the barrier metal layer.

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