JP2006155357A - Voltage lowering circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage lowering circuit that can increase the current drive capability, reduce standby current, stabilize the internal power source voltage, and reduce the size. <P>SOLUTION: The voltage lowering circuit 1 lowers the external power source voltage VDD based on a predetermined reference voltage Vref1, and generates the internal power source voltage Vint. The voltage lowering circuit 1 comprises a negative feedback circuit having an operational amplifier 13 for generating driving voltage Vout1 according to the voltage difference between the voltage based on the internal power source voltage Vint and the reference voltage Vref1 and a driving transistor DRV1 for outputting the internal power source voltage Vint according to the driving voltage Vout1, and a control circuit 15 for generating a control signal IS1 for varying and controlling the response speed of the negative feedback circuit when the voltage difference between the internal power source voltage Vint and the reference voltage Vref1 exceeds a predetermined range. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a step-down circuit, and more particularly to a step-down circuit that steps down an external power supply voltage to a predetermined voltage and supplies it as a power supply voltage for internal circuits.

  In recent years, semiconductor devices such as SOC (System On a Chip) have been increasingly required to have high integration, low power consumption, and high speed. In such a semiconductor device, in order to reduce power consumption or protect elements constituting the internal circuit, an operation is performed to step down a power supply voltage (external power supply voltage) supplied from the outside and supply it to the internal circuit. A step-down circuit that generates a voltage (internal power supply voltage) is used. Conventionally, as such a step-down circuit, for example, one having the configuration shown in FIG. 12 is widely known.

  As shown in FIG. 12, the step-down circuit 100 is a constant voltage circuit having a voltage input voltage output type negative feedback circuit as a basic circuit, and supplies a constant current to the reference voltage generation circuit 101, the operational amplifier 102, and the operational amplifier 102. A source 103, a driving transistor DRV, resistors R1 and R2 forming a voltage dividing resistor, an output adjustment circuit 104, and a phase compensation circuit 105 are provided. Note that the phase compensation circuit 105 includes, for example, a phase compensation capacitor CC.

  The drive transistor DRV is composed of, for example, a P-channel MOS transistor, and an external power supply voltage VDD is applied to the source, and an internal power supply terminal of an internal circuit (load circuit of the step-down circuit 100) (not shown) is connected to the drain. It is connected. A phase compensation circuit 105 is connected between the gate and drain of the drive transistor DRV, and resistors R1 and R2 are connected in series with the ground potential to the drain of the drive transistor DRV.

  The output adjustment circuit 104 is composed of, for example, three-stage transistors TN51 to TN53 made of N channel type MOS transistors, and these are connected in series between the drain of the drive transistor DRV and the ground potential. The output adjustment circuit 104 adjusts the internal power supply voltage Vint output from the step-down circuit 100 based on the threshold values of the transistors TN1 to TN3.

  The reference voltage generation circuit 101 and the operational amplifier 102 use the external power supply voltage VDD as an operation power supply. The operational amplifier 102 divides the reference voltage Vref generated from the reference voltage generation circuit 101 and the internal power supply voltage Vint by resistors R1 and R2. The voltage difference from the potential of the contact A generated in this way is amplified and output. The output voltage of the operational amplifier 102 is input to the gate of the drive transistor DRV. Thus, the internal power supply voltage Vint is generated through the driving transistor DRV so as to be substantially the same voltage as the reference voltage Vref.

  In such a step-down circuit 100, the current source 103 that supplies a constant current to the operational amplifier 102 is based on an external control signal CE that controls the active state (active state) and standby state (standby state) of the internal circuit. It can be varied between active and standby. As a result, the current consumption of the step-down circuit 100 is reduced during standby, while the operation response (response speed) is increased when active.

However, along with the demand for the realization of SOC by LSI and further function expansion, LSI has recently advanced simultaneously with high-speed operation, low current consumption, improved power noise resistance, internal power supply, and IP (Intellectual Property) core size reduction. It has been. Although the step-down circuit can be viewed as one IP core, it has a power supply function and is usually positioned higher as a system core. Therefore, in a step-down circuit, 1) follow the load current associated with high-speed operation well, 2) reduce the current consumption of the step-down circuit itself, 3) generate a clean internal power supply to ensure noise resistance, and 4) It is required to be compact.

  The present invention has been made in view of such conventional circumstances, and its purpose is to focus on the development points of the above four items, and to enhance current driving capability, low standby current, stable internal power supply voltage, and The object is to provide a step-down circuit aiming at miniaturization.

  In the following, means for achieving the above object and its operation will be described.

  According to the first aspect of the present invention, in the step-down circuit that generates the internal power supply voltage obtained by stepping down the external power supply voltage based on a predetermined reference voltage and supplies the internal power supply voltage to a load circuit, the voltage based on the internal power supply voltage A negative feedback circuit comprising: an operational amplifier that generates a drive voltage according to a voltage difference between the reference voltage and a drive transistor that outputs the internal power supply voltage according to the drive voltage; and the internal power supply voltage And a control circuit that generates a control signal for variably controlling the response speed of the negative feedback circuit when the voltage difference between the reference voltage and the reference voltage exceeds a predetermined range.

  According to this configuration, based on the operation of the negative feedback circuit, the internal power supply voltage is generated so as to be a voltage that substantially matches the reference voltage. At this time, in this configuration, when the control circuit detects that the internal power supply voltage fluctuates beyond a predetermined range with respect to the reference voltage, the response speed of the negative feedback circuit is variably controlled. Thereby, for example, when the load current (current consumption of the load circuit) decreases and the internal power supply voltage is within a predetermined range with respect to the reference voltage and is stable, the response speed of the negative feedback circuit is decreased. Reduce current consumption. On the other hand, when the internal power supply voltage fluctuates beyond a predetermined range with respect to the reference voltage, the operation response can be optimized by increasing the response speed of the negative feedback circuit.

  According to a second aspect of the present invention, in the step-down circuit according to the first aspect, when the load circuit is in an active state, the control circuit can vary the response speed of the negative feedback circuit based on an external clock signal. The gist is to control.

  According to this configuration, in the active state, the response speed of the negative feedback circuit is variably controlled based on an external clock signal, so that the operation response of the negative feedback circuit during the active state can be improved. In addition, by using control based on such a clock signal instead of an external control signal that controls the active / inactive state of the load circuit, the step-down circuit can be operated to predict the operating state of the load circuit to some extent. It is possible to simultaneously reduce current consumption during the active state.

  According to a third aspect of the present invention, in the step-down circuit according to the first aspect, the response speed of the negative feedback circuit is variably controlled by controlling a current value of a current source that supplies a current to the operational amplifier. Is the gist.

  According to this configuration, the response speed of the operational amplifier can be controlled by controlling the current value of the current source that supplies current to the operational amplifier. Therefore, the response speed of the negative feedback circuit can be easily controlled.

  According to a fourth aspect of the present invention, in the step-down circuit according to the first aspect, in the control circuit, the load circuit is in an active state, and a voltage difference between the internal power supply voltage and the reference voltage is in the predetermined range. The gist of the present invention is to detect a quasi-standby state, and to control the current value of a current source that supplies current to the operational amplifier to the same current value as when the load circuit is in a standby state in the quasi-standby state .

  According to this configuration, when the quasi-standby state is detected by the control circuit, the current value of the current source of the operational amplifier is controlled to be the same as that during standby. Thereby, even in the active state, current consumption can be reduced as much as possible in the quasi-standby state.

  According to a fifth aspect of the present invention, in the step-down circuit according to the third or fourth aspect, the current source is a first current source composed of a transistor operating in a weak inversion region, and the control circuit outputs The gist is that the second current source controlled based on the control signal is connected in parallel.

  According to this configuration, when the voltage difference between the internal power supply voltage and the reference voltage is within a predetermined range, the current value of the current source of the operational amplifier is set to a minute current value flowing through the transistor controlled to perform the weak inversion operation. Be controlled. On the other hand, when the voltage difference between the internal power supply voltage and the reference voltage exceeds a predetermined range, the second current source is activated based on a control signal from the control circuit, and the current value of the current source of the operational amplifier is The current value of the second current source is controlled to a total value. Thereby, in this configuration, the current value of the current source of the operational amplifier can be variably controlled following the potential fluctuation of the internal power supply voltage.

  According to a sixth aspect of the present invention, in the step-down circuit according to the third or fourth aspect, the control circuit amplifies a voltage difference between the reference voltage and the internal power supply voltage to generate a differential amplified voltage. The gist thereof includes a dynamic amplification circuit, and a drive circuit that generates the control signal for variably controlling the current value of the current source of the operational amplifier based on the differential amplification voltage.

  According to this configuration, the control circuit controls the current value of the current source of the operational amplifier based on the differential amplification voltage generated by the differential amplification circuit according to the voltage difference between the reference voltage and the internal power supply voltage. Generate a signal.

  According to a seventh aspect of the present invention, in the step-down circuit according to any one of the first to sixth aspects, the control circuit has a voltage difference between the internal power supply voltage and the reference voltage exceeding the predetermined range. The gist of the invention is to slowly change the control signal when the state changes from the current state to the state within the predetermined range.

  According to this configuration, when the voltage difference between the internal power supply voltage and the reference voltage changes from a state exceeding a predetermined range to a state within the predetermined range, the control signal is abruptly shifted (that is, negative). An increase in the internal power supply voltage due to a rapid decrease in the response speed of the feedback circuit can be suitably suppressed.

  According to an eighth aspect of the present invention, in the step-down circuit according to any one of the first to seventh aspects, the drive transistor has a drain connected to the external power supply voltage and a source connected to the internal power supply voltage. The gist of this is that it is composed of NMOS transistors.

According to this configuration, when the internal power supply voltage increases, the gate voltage of the NMOS transistor (drive transistor) decreases accordingly, so that the drive transistor operates to decrease the drain current. If the substrate bias of the NMOS transistor is fixed, the drain current can also be reduced through the potential difference between the source and the substrate. Thereby, in this configuration, the amount of current flowing through the drive transistor can be feedback-controlled by the drive transistor itself following the potential fluctuation of the internal power supply voltage, so that the responsiveness of the negative feedback circuit can be further improved. By the way, from the point of drive capability, the element size can be set smaller when the NMOS transistor is used than when the PMOS transistor is used (in the case of the same size, the NMOS transistor can obtain a larger drive capability). This is advantageous.

  According to a ninth aspect of the present invention, in the step-down circuit according to any one of the first to eighth aspects, a transistor operating in a weak inversion region is used as a current source, and the reference voltage is based on the external power supply voltage. The gist of the present invention is to include a reference voltage generation circuit for generating

  According to this configuration, the reference voltage generation circuit can be operated with low current consumption. As a result, the power consumption of the step-down circuit can be further reduced.

  As described above, according to the present invention, it is possible to provide a step-down circuit capable of enhancing current driving capability, low standby current, stable internal power supply voltage, and downsizing.

  Hereinafter, an embodiment in which the present invention is embodied in a step-down circuit mounted on a semiconductor device will be described with reference to the drawings.

  FIG. 2 shows an overall configuration of the semiconductor device 2 on which the step-down circuit 1 according to the present embodiment is mounted.

  In the present embodiment, the semiconductor device 2 is configured as a semiconductor memory having an SRAM (Static-RAM) as an internal circuit 3. The semiconductor device 2 includes an external power supply voltage (hereinafter referred to as “external power supply voltage”). A step-down circuit 1 is mounted that generates a power supply voltage (hereinafter referred to as “internal power supply voltage”) Vint that steps down VDD and supplies it to the internal circuit 3. In such a semiconductor device 2, the internal circuit 3 can be considered as a load circuit of the step-down circuit 1 when viewed from the step-down circuit 1 side.

  FIG. 1 shows a schematic configuration of the step-down circuit 1. Note that the same components as those in FIG. 12 described above are denoted by the same reference numerals.

  The step-down circuit 1 includes a bias voltage generation circuit 11, a reference voltage generation circuit 12, an operational amplifier 13, a current source 14 of the operational amplifier 13, a drive transistor DRV1, resistors R1 and R2, a control circuit 15, an output adjustment circuit 16, and the like. Has been. In the present embodiment, the feedback circuit 19 is configured by the resistor R1 and the resistor R2.

  The bias voltage generation circuit 11 is a circuit that generates a control voltage that determines the bias current values of the reference voltage generation circuit 12 and the operational amplifier 13. In the present embodiment, the bias voltage generation circuit 11 includes a first control voltage VN that controls the bias current value of the operational amplifier 13 (specifically, the current value of the current source 14), and the bias current of the reference voltage generation circuit 12. A second control voltage VP for controlling the value is generated.

The reference voltage generation circuit 12 is a circuit that generates a reference voltage that serves as a reference when the internal power supply voltage Vint is generated by stepping down the external power supply voltage VDD by the step-down voltage circuit 1. In the present embodiment, the reference voltage generation circuit 12 includes a first reference voltage Vref1 that is a set voltage of the internal power supply voltage Vint based on the second control voltage VP generated by the bias voltage generation circuit 11. The second reference voltage Vref2 having a higher potential than the first reference voltage Vref1 is generated.

  The operational amplifier 13 is a differential amplifier that amplifies and outputs a difference between two input voltages applied to two input terminals. In the present embodiment, the operational amplifier 13 has a first reference voltage Vref1 from the reference voltage generation circuit 12 supplied to one input terminal and a feedback voltage Vfb (internal power supply voltage Vint supplied to the other input terminal). The drive voltage Vout1 is generated by amplifying the difference between the internal power supply voltage Vint and the divided voltage by the resistors R1 and R2 of the feedback circuit 19.

  The current source 14 is a circuit that supplies a bias current to the operational amplifier 13. For convenience of explanation, in FIG. 1, the operational amplifier 13 and the current source 14 are functionally shown separately, but actually, the current source 14 is provided inside the operational amplifier 13.

  As described above, the first control voltage VN generated by the bias voltage generation circuit 11 is supplied to the current source 14. In the present embodiment, the first control voltage VN is constantly applied to the current source 14 when the semiconductor device 2 is in a standby state (inactive state of the internal circuit 3) and active (internal state of the internal circuit 3). This voltage is supplied and controls to operate a MOS transistor (described later) constituting the current source 14 in a weak inversion region (also referred to as a subthreshold region).

  Here, in addition to the control by the first control voltage VN, the current source 14 of the present embodiment is generated based on the internal power supply voltage Vint by the control circuit 15 to be described later, or an external clock signal CLK or The current value is controlled by a control signal IS1 generated based on the internal clock signal QPCB. Thus, the bias current of the operational amplifier 13 is controlled to a necessary and sufficient amount for optimizing the operation response according to the occurrence of the internal power supply voltage Vint and the external or internal clock.

  That is, at the time of standby, the transistor constituting the current source 14 is operated in the weak inversion region by the first control voltage VN to reduce the current consumption of the operational amplifier 13 as much as possible, while at the time of active, the current value of the current source 14 is set to the control signal IS1. To optimize the operational response of the operational amplifier 13. Thereby, the step-down circuit 1 can flexibly cope with potential fluctuations in the internal power supply voltage Vint.

  In the present embodiment, the drive transistor DRV1 is composed of an N-channel MOS transistor (hereinafter referred to as “NMOS transistor”), more specifically, an NMOS transistor having a low threshold characteristic by channel doping or the like. The external power supply voltage VDD is applied to the drain of the drive transistor DRV1, the internal power supply terminal (supply terminal of the internal power supply voltage Vint) of the internal circuit 3 is connected to the source, and the drive voltage from the operational amplifier 13 is connected to the gate. Vout1 is supplied. The resistors R1 and R2 forming the feedback circuit 19 are connected in series between the source of the drive transistor DRV1 and the ground potential, and the potential at the connection point between the resistors R1 and R2 is the operational amplifier 13. Is input as a feedback voltage Vfb of the internal power supply voltage Vint. Although not shown, the back gate of the drive transistor DRV1 is connected to the ground potential.

In the present embodiment, a first loop for generating an internal power supply voltage is configured by a negative feedback circuit including an operational amplifier 13, a drive transistor DRV1, and a feedback circuit 19 (configured by resistors R1 and R2 in this example). Has been. The first reference voltage Vref1 and the feedback voltage Vfb are controlled by the first loop so that they substantially coincide with each other, whereby the internal power supply voltage Vin
t is controlled to a level related to the first reference voltage Vref1 through the characteristics of the feedback circuit 19 and becomes stable. In addition to the control loop (first loop) of the negative feedback circuit, when the control circuit 15 described later detects a downward fluctuation of the internal power supply voltage Vint exceeding a predetermined range with respect to the first reference voltage Vref1, an operational amplifier The second loop that is fed back from the output of 13 (drive voltage Vout1) to the operational amplifier 13 via the drive transistor DRV1, the control circuit 15, and the current source 14 also operates. Further, as will be described later, the drive transistor DRV1 functions as a negative feedback for controlling the source-drain current Ids in accordance with a change in the internal power supply voltage Vint.

  In the present embodiment, the response speed of the negative feedback circuit is variably controlled by controlling the current source 14 of the operational amplifier 13, but the method of variably controlling the response speed of the negative feedback circuit is not limited to this. . For example, a drive transistor DRV1a (not shown) having a threshold voltage lower than that of the drive transistor DRV1 (NMOS) is separately prepared. When a high response speed is required for the negative feedback circuit, the drive transistor DRV1 is replaced by the drive transistor DRV1a. Normally, when designing for the same driving capability, the driving transistor DRV1a having a low threshold voltage can be designed more compactly than the driving transistor DRV1, and therefore the response speed of the negative feedback circuit is improved by the effect of reducing the gate capacitance. Can do. In this case, switching between the drive transistor DRV1 and the drive transistor DRV1a may be performed by the control signal IS1.

  The control circuit 15 is a circuit that detects the potential of the internal power supply voltage Vint generated by the step-down circuit 1 and controls the current value of the current source 14 (that is, the current value of the operational amplifier 13) based on the detected potential. . In the present embodiment, the control circuit 15 is configured to control the current source 14 based on the first and second reference voltages Vref1 and Vref2 generated by the reference voltage generation circuit 12 and the feedback voltage Vfb of the internal power supply voltage Vint. A control signal IS1 for controlling the current value is generated.

  As shown in FIG. 1, the step-down circuit 1 according to the present embodiment includes a buffer circuit with an amplification factor “1” that outputs the second reference voltage Vref2 generated by the reference voltage generation circuit 12 without being disturbed. 17 is provided, and the control circuit 15 is supplied with the second reference voltage Vref2 through the buffer circuit 17. Hereinafter, in the present specification, the second reference voltage supplied to the control circuit 15 through the buffer circuit 17 is described as “Vref2A”. Incidentally, the current source 18 for supplying a constant current to the buffer circuit 17 is composed of a MOS transistor that performs a weak inversion operation by the first control voltage VN from the bias voltage generation circuit 11, thereby reducing the buffer circuit 17 with low power consumption. It operates with current.

  The output adjustment circuit 16 is configured by connecting three stages of transistors TN51 to TN53 made of, for example, NMOS transistors in series between the source of the transistor DRV1 and the ground potential, as in FIG. 12 described above. The output adjustment circuit 16 monitors the internal power supply voltage Vint output from the step-down circuit 1 so that it does not rise above a predetermined level. Specifically, under the condition of internal power supply voltage Vint <first reference voltage + α (where α> 0), current does not flow through each of the transistors TN51 to TN53, while otherwise, the surplus of the internal power supply voltage Vint The threshold voltage or size of each of the transistors TN51 to TN53 is set so as to discharge the charge.

  Next, the detailed configuration of each circuit constituting the step-down circuit 1 will be described.

  First, the configuration of the bias voltage generation circuit 11 will be described with reference to FIG.

  The bias voltage generation circuit 11 includes two current mirror circuits and a current source. Specifically, a pair of PMOS transistors TP1 and TP2 constituting a first current mirror circuit, a pair of NMOS transistors TN1 and TN2 constituting a second current mirror circuit, and the low threshold characteristic NMOS constituting a current source The transistor TND1 is configured.

  The sources of the transistors TP1 and TP2 are connected to the external power supply voltage VDD, and their gates are connected to each other and to the drain of the transistor TP1. The drains of the transistors TP1 and TP2 are connected to the drains of the transistors TN1 and TN2, respectively. The gates of the transistors TN1 and TN2 are connected to each other and to the drain of the transistor TN2. In other words, the first current mirror circuit and the second current mirror circuit are connected so that each other's output current is given as an input current. The source of the transistor TN1 is connected to the ground potential via the transistor TND1 forming a current source, and the source of the transistor TN2 is connected to the ground potential. The transistor TND1 is provided such that its source and its gate are connected to each other.

  In the bias voltage generation circuit 11 configured as described above, the potential at the connection point between the transistors TP1 and TN1 (the input potential of the first current mirror circuit) is output as the second control voltage VP, and the potential at the connection point between the transistors TP2 and TN2 is output. The potential is output as the first control voltage VN.

  Here, in the present embodiment, the current source of the bias voltage generation circuit 11 is configured to use the NMOS transistor TND1 having the low threshold characteristic so that the gate voltage Vgs = 0. If the gate voltage Vgs = 0 and the transistor TND1 is set to operate in the weak inversion region, it not only functions as a current source that generates a constant current independent of the external power supply voltage VDD, but also its drain current (Ids) is absolute. It exhibits temperature dependence proportional to the power of temperature T approximately to the 0.5th power and exhibits extremely stable characteristics in practice. Further, since the source-drain voltage (Vds) can be made extremely small, the lower limit of the external power supply voltage VDD at which the bias voltage generating circuit 11 operates normally is set to the theoretical limit (Vtn−Vtp; enhancement type N / PMOS threshold) of the CMOS circuit. ) Can be lowered. That is, the step-down circuit 1 can cope with a very wide external power supply voltage VDD.

  On the other hand, even if the threshold voltage of the transistor TND1 is set sufficiently low so that the transistor TND1 operates in a strong inversion linear region when the gate voltage Vgs = 0, the current source generates a constant current independent of the external power supply voltage VDD. Function. When the element size is adjusted to lower the drain current (Ids) of the transistor TND1, the transistors TN1 and TN2 eventually operate in the weak inversion region, and the drain current (Ids) is almost equal to the absolute temperature T. Shows temperature dependence proportional to -0.5. Therefore, it provides a technology that can reduce current consumption as the temperature rises, and exhibits extremely stable characteristics in practice.

  Since the drain current (Ids) depends only on the threshold value (Vt) of the transistor TND1 with respect to the process variation, it can be said that it is practical because only the threshold value (Vt) of the transistor TND1 can be managed from the viewpoint of the manufacturing process. When the transistor TND1 operates in the weak inversion region, the drain current (Ids) is proportional to the exponent of the threshold (Vt), and when operated in the strong inversion region, the drain current (Ids) is proportional to the first power of the threshold (Vt). Therefore, it is advantageous to operate the transistor TND1 in the linear region of strong inversion from the viewpoint of process variation.

  Next, the configuration of the reference voltage generation circuit 12 will be described with reference to FIG.

  The reference voltage generation circuit 12 includes current sources 31 and 32 and PMOS transistors TP3 to TP6.

  In the present embodiment, the current sources 31 and 32 are each composed of a PMOS transistor. The current source 31 is connected to the ground potential via the diode-connected transistors TP3 to TP5, and the current source 32 is Are connected to the ground potential via the transistor TP6. The potential of the connection point between the current source 31 and the transistor TP3, specifically, the total potential of | Vgs | (absolute value of the gate-source voltage) of each of the transistors TP3 to TP5 from the ground potential is first. The reference voltage Vref1 is output. The first reference voltage Vref1 is supplied to the gate of the transistor TP6, and the potential at the connection point between the transistor TP6 and the current source 32 is output as the second reference voltage Vref2.

  In the reference voltage generation circuit 12 configured in this way, the first and second reference voltages Vref1 and Vref2 are generated so that Vref2> Vref1 in the recommended operating power supply voltage range of the semiconductor device 2, as shown in FIG. Is done.

  Here, in the present embodiment, the PMOS transistors forming the current sources 31 and 32 of the reference voltage generation circuit 12 are each weakly inverted by the second control voltage VP generated by the bias voltage generation circuit 11. Be controlled. As a result, the reference voltage generation circuit 12 operates with low current consumption regardless of standby or active.

  Next, the configuration of the operational amplifier 13 will be described with reference to FIG.

  As shown in FIG. 6A, the operational amplifier 13 includes a pair of PMOS transistors TP8 and TP9 forming a current mirror circuit as a load, a pair of NMOS transistors TN3 and TN4 forming a differential pair transistor, and a current source 14. It is composed of

  The sources of the transistors TP8 and TP9 are connected to the external power supply voltage VDD, and their gates are connected to each other and to the drain of the transistor TP8. The drains of the transistors TP8 and TP9 are connected to the drains of the transistors TN3 and TN4, respectively, and the sources of the transistors TN3 and TN4 are connected to the ground potential via the current source 14. Then, the first reference voltage Vref1 is supplied to the gate of the transistor TN3, the feedback voltage Vfb of the internal power supply voltage Vint is supplied to the gate of the transistor TN4, and a voltage obtained by amplifying the difference between the first reference voltage Vref1 and the feedback voltage Vfb Is output as the drive voltage Vout1 from the connection point of the transistors TP9 and TN4.

  In this embodiment, the element size ratio of the pair of transistors TP8 and TP9 forming the current mirror circuit is set to 1: x (x> 1) between the input-side transistor TP8 and the output-side transistor TP9. The operational amplifiers 13 are configured to have electrically asymmetric characteristics by making their current drive capacities different from each other. In such a configuration, although the amplification factor of the operational amplifier 13 is reduced as compared with the case where the current driving capability of each of the transistors TP8 and TP9 is the same (that is, the element size ratio is 1: 1), the oscillation is preferably suppressed. It becomes possible. This greatly contributes to making it possible to delete the phase compensation circuit 105 (see FIG. 12), which is necessary in the conventional step-down circuit 100, in the step-down circuit 1 in the negative feedback circuit.

As shown in FIG. 7, first, the drive transistor DRV1 is constituted by the NMOS transistor having the low threshold characteristic (indicated by D-NMOS in the figure), so that the transistor D
A larger drain current Id can be obtained even with a lower gate voltage Vgs than when RV1 is configured by an enhancement type NMOS transistor (indicated by E-NMOS in the figure). That is, not only can the current driving capability of the driving transistor DRV1 be improved, but also when the same current driving capability is obtained, the element size of the driving transistor DRV1 is reduced to reduce the parasitic capacitance of the transistor DRV1. Can do. That is, the switching speed of the drive transistor DRV1 can be increased. As a result, the gate controllability (transistor switching speed) of the drive transistor DRV1 driven by the operational amplifier 13 can be improved, and the responsiveness (feedback speed) of the negative feedback circuit can be improved.

  As described above, in the present embodiment, the phase compensation circuit 105 (FIG. 12) that has conventionally required the effect of lowering the amplification factor of the operational amplifier 13 and the high-speed feedback control that is the effect of reducing the size of the drive transistor DRV1. Even if it is eliminated, it is possible to realize sufficient phase compensation, thereby stabilizing the operation of the negative feedback circuit.

  Even if the transistor DRV1 is constituted by a normal enhancement type NMOS transistor (E-NMOS) instead of the low threshold characteristic NMOS transistor (D-NMOS), the following effects can be obtained.

  That is, if an NMOS transistor is used and its source is connected to the internal power supply terminal (supply terminal of the internal power supply voltage Vint) of the internal circuit 3 to configure the transistor DRV1, for example, when the internal power supply voltage Vint rises, As a result, the gate voltage Vgs decreases, so that the transistor DRV1 operates to decrease the drain current Id. When the internal power supply voltage Vint increases in this way, the source-back gate voltage Vbs of the transistor DRV1 increases, so that the transistor DRV1 operates to decrease the drain current Id as before. Incidentally, since the output resistance of the D-NMOS can be designed to be lower than that of the E-NMOS, the D-NMOS exhibits good characteristics as a constant voltage source. That is, in such a configuration, the amount of current flowing through the transistor DRV1 can be feedback-controlled by following the potential fluctuation of the internal power supply voltage Vint. From this point of view, if the drive transistor DRV1 is constituted by an NMOS transistor, the feedback response can be improved as compared with the case where the drive transistor DRV1 is constituted by a PMOS transistor.

  Next, the configuration of the current source 14 of the operational amplifier 13 will be described with reference to FIG.

  As shown in FIG. 6B, the current source 14 is specifically configured by connecting a first current source 35 and a second current source 36 in parallel.

  The first current source 35 is constituted by an NMOS transistor TN7 in the present embodiment, and the first control voltage VN generated by the bias voltage generating circuit 11 is applied to the gate of the transistor TN7. Steadily supplied at the time of operation and when active. At this time, as described above, the transistor TN7 is controlled to perform a weak inversion operation by the first control voltage VN. Accordingly, the current value (drain current) of the first current source 35 is controlled to a minute current value.

On the other hand, the second current source 36 includes a switch element 37 and the NMOS transistor TND2 having the low threshold characteristic connected in series thereto. Note that the transistor TND2 substantially operates as the second current source 36. The switch element 37 is constituted by an NMOS transistor in the present embodiment, and the conduction is controlled based on the control signal IS1 from the control circuit 15. The transistor TND2 has a gate and a source connected to each other, a source connected to the ground potential, and a drain connected to the switch element 37. As long as the source-drain voltage Vds of the NMOS transistor TND2 having the low threshold characteristic is set within an appropriate range, the transistor TND2 operates in the saturation region at the gate voltage (gate-source voltage) Vgs = 0. An excellent current source that can stably supply a current can be configured, and a simple configuration that does not require an additional circuit that drives the current source can be achieved.

  The second current source 36 supplies a constant current flowing through the transistor TND2 to the operational amplifier 13 through the switch element 37 when the switch element 37 is turned on by the control signal IS1. Incidentally, the current value flowing through the NMOS transistor TND2 is set to a current value much larger than the current value flowing through the transistor TN7 that performs the weak inversion operation.

  As described above, the current source 14 supplies the constant current from the first current source 35 controlled to a very small current value to the operational amplifier 13 during standby, while being added to the constant current from the first current source 35 when active. Further, a constant current from the second current source 36 is supplied to the operational amplifier 13.

  Although not shown in the figure, the current source 18 of the buffer circuit 17 is composed of an NMOS transistor as in the first current source 35 described above, and this NMOS transistor is also driven by the first control voltage VN. It has become a weak inversion operation. As a result, the buffer circuit 17 is also operated with low current consumption.

  Next, the configuration of the control circuit 15 will be described with reference to FIGS.

  As shown in FIG. 8, the control circuit 15 includes a differential amplifier circuit 41, a drive circuit 42, and a waveform shaping circuit 43.

  In addition to the activation signal SLEEP, the differential amplifier circuit 41 includes a first reference voltage Vref1, a second reference voltage Vref2A, a feedback voltage Vfb of the internal power supply voltage Vint, and a control signal IS1 output from the drive circuit 42. Entered. As will be described in detail with reference to FIG. 9, the differential amplifier circuit 41 includes a first differential amplifier that uses the second reference voltage Vref2A as an operation power supply and a second difference that uses an external power supply voltage VDD as an operation power supply. The dynamic amplifier amplifies the voltage difference between the feedback voltage Vfb of the internal power supply voltage Vint and the first reference voltage Vref1, and outputs a differential amplified voltage OUT1.

  The waveform shaping circuit 43 includes an external control signal / CE (/ means negative) that controls when the semiconductor device 2 is active and standby, and an internal clock signal QPCB generated by the internal circuit 3 of the semiconductor device 2. Based on the above, the output waveform (differential amplification voltage OUT1) of the differential amplifier circuit 41 is set to a predetermined H level potential. As a result, the differential amplification voltage OUT1 is driven by a wired OR between the output of the waveform shaping circuit 43 and the output of the differential amplification circuit 41.

The waveform shaping circuit 43 generates a clock signal QPCB2 that controls the operation of the control circuit 15 based on the control signal / CE and the internal clock signal QPCB. In the present embodiment, it is assumed that the internal circuit 3 (SRAM) is an asynchronous memory, and the internal clock signal QPCB generated inside the SRAM is supplied to the waveform shaping circuit 43. When the operation of the semiconductor device 2 is controlled in synchronization with an external clock signal CLK (system clock), such as when the internal circuit 3 is a synchronous memory, this system clock is supplied instead of the internal clock signal QPCB. It is good also as composition to do.

  The drive circuit 42 generates a control signal IS1 for controlling the current value of the current source 14 based on the clock signal QPCB2 from the waveform shaping circuit 43 and the differential amplified voltage OUT1 from the differential amplifier circuit 41.

  FIG. 9 shows a detailed circuit configuration of the differential amplifier circuit 41.

  As described above, the basic configuration of the differential amplifier circuit 41 includes the first differential amplifier 51 that uses the second reference voltage Vref2A as the DC operating power supply and the second differential amplifier 52 that uses the external power supply voltage VDD as the operating power supply. And connected.

  In the present embodiment, the first differential amplifier 51 includes a pair of PMOS transistors TP12 and TP13 forming a differential pair transistor, four NMOS transistors TN8 and TN9 and NMOS transistors TN10 and TN11 formed as diodes. The second reference voltage Vref2A is supplied to the sources of the pair of transistors TP12 and TP13. The first differential amplifier 51 amplifies the difference between the first reference voltage Vref1 input to the gates of the pair of transistors TP12 and TP13 and the feedback voltage Vfb of the internal power supply voltage Vint, thereby generating transistors TP12, The potential of the connection point (node N1) of TN8 and the potential of the connection point (node N2) of the transistors TP13 and TN10 are given to the second differential amplifier 52 as differential inputs.

  In the present embodiment, the second differential amplifier 52 includes a pair of PMOS transistors TP14 and TP15 forming a current mirror circuit, a pair of NMOS transistors TN12 and TN13 forming a differential pair transistor, and NMOS transistors TN14 and TN15. It is composed of Note that the gates of the transistors TN14 and TN15 are connected to the connection point of the transistors TN8 and TN9 and the connection point of the transistors TN10 and TN11, respectively, which form the first differential amplifier 51.

  In the second differential amplifier 52, a series connection circuit of PMOS transistors TP16, TP17, TP18 and a PMOS transistor TP19 are connected between the sources of the pair of transistors TP14, TP15 forming the current mirror circuit and the external power supply voltage VDD. , TP20, TP21 are connected in parallel with the series connection circuit. When the control signal IS1 from the drive circuit 42 is at L level, the voltage that is stepped down from the external power supply voltage VDD by the threshold of the transistors TP20 and TP21 in the path of the transistors TP19, TP20, TP21, and when the control signal IS1 is at H level The full level of the external power supply voltage VDD is applied to the transistors TP14, TP15 through the paths of the transistors TP16, TP17, TP18. Incidentally, when the control signal IS1 is at the H level, the transistor TP16 is an inverted signal of the control signal IS1 by the inverter circuit INV1, the transistor TP17 is at the ground potential, and the transistor TP18 is gated by the activation signal SLEEP. The transistor TP17 is provided to suppress circuit malfunction due to the influence of instantaneous fluctuations in the external power supply voltage VDD, and the transistor TP18 is provided to inhibit circuit operation by the activation signal SLEEP. The activation signal SLEEP may be connected to the ground potential as necessary.

  In the second differential amplifier 52, the sources of the pair of transistors TN12 and TN13 forming the differential pair transistor are connected to the ground potential via the NMOS transistor TN16 and the NMOS transistor TND3 having the low threshold characteristics. . Here, the control signal IS1 output from the drive circuit 42 is supplied to the gate of the transistor TN16 via the inverter circuits INV1 and INV2.

  Since the transistors TN9 and TN14 and the transistors TN11 and TN15 are in a current mirror relationship, when the control signal IS1 is at the L level, the second differential amplifier 52 is connected to the first differential amplifier 51 by the transistors TN14 and TN15. However, when the control signal IS1 becomes H level, the bias current from the transistor TND3 (constant current source) is also taken into account. In the present embodiment, the transistor TP12 of the first differential amplifier 51 always performs a weak inversion operation, and the transistor TP13 does not move downward unless the internal power supply voltage Vint exceeds a predetermined range with respect to the first reference voltage Vref1. Since the weak inversion operation is performed, the differential amplifier circuit 41 as a whole is biased with a low current as long as the internal power supply voltage Vint is stabilized at a predetermined level.

  On the other hand, when the internal power supply voltage Vint fluctuates downward beyond a predetermined range with respect to the first reference voltage Vref1, the drain current of the transistor TP13 increases and the bias currents of the first and second differential amplifiers 51 and 52 increase. As a result, the response of the differential amplifier circuit 41 is improved. Furthermore, if the bias current from the transistor TND3 (constant current source) is set larger than the bias current from the transistors TN14 and TN15, the response of the second differential amplifier 52 is further improved when the control signal IS1 becomes H level. . Thereafter, when the control signal IS1 becomes L level, the supply of the bias current from the transistor TND3 is stopped, the bias current of the second differential amplifier 52 is lowered, and the response is also lowered.

  The second differential amplifier 52 configured as described above amplifies the voltage difference between the nodes N1 and N2 of the first differential amplifier 51 and outputs the amplified voltage as a differential amplified voltage OUT1.

  FIG. 10 shows a detailed circuit configuration of the drive circuit 42.

  The drive circuit 42 receives the differential amplified voltage OUT1 output from the differential amplifier circuit 41 at one input terminal via the inverter circuits INV3 to INV5, and is output from the waveform shaping circuit 43 to the other input terminal. A two-input NAND gate 61 for receiving the clock signal QPCB2 to be input. The drive circuit 42 operates in synchronization with the fall of the clock signal QPCB 2 when the semiconductor device 2 is active, and outputs the control signal IS 1 from the output terminal of the NAND gate 61.

  More specifically, the drive circuit 42 responds to the fall of the clock signal QPCB2 to activate the second current source 36 provided in the current source 14 (see FIG. 6B) when activated. The H level control signal IS1 is turned on. Then, after that, it is detected that the voltage difference between the first reference voltage Vref1 and the internal power supply voltage Vint is within a predetermined range (specifically, the level of the differential amplification voltage OUT1 determines the output of the inverter circuit INV5 to H The control signal IS1 is set to L level when the level reaches a level sufficient to achieve level.

  Here, when the voltage difference between the first reference voltage Vref1 and the internal power supply voltage Vint is within a predetermined range in the above active state, the supply current of the drive transistor DRV1 and the load current of the internal circuit 3 (consumption of the internal circuit 3) Current).

When the load circuit is balanced at a low load current, the internal circuit 3 is set to the standby state by the control signal / CE from the outside, or is set to the active state by the control signal / CE. This is when the internal circuit 3 has finished the data processing operation (semi-standby state). The quasi-standby state is detected when the differential amplification voltage OUT1 satisfies an input level sufficient for the output of the inverter circuit INV5 constituting the drive circuit 42 to become H level. When the quasi-standby state is detected, the control signal IS1 immediately becomes L level, and the switch element 37 constituting the current source 14 is opened (turned off) to suppress excessive current consumption. As a result, the semiconductor device 2 in which the state is set with the same low current consumption as that in the standby state defined by the control signal / CE even in the quasi-standby state is realized.

  On the other hand, when the balance is achieved at a high load current, it is a period during which the internal circuit 3 continues the data processing operation. In this case, the differential amplifier circuit 41 is set so that the control signal IS1 is held at the H level in the period tRET that is equal to or longer than the longest period tMAX in which the data processing operation of the internal circuit 3 ends. However, when this condition (tMAX ≦ tRET) is not satisfied for some reason, the internal power supply voltage Vint may rapidly increase. This problem can be solved by preventing the control signal IS1 from abruptly transitioning from the H level to the L level, that is, not abruptly reducing the operation response of the operational amplifier 13.

  In the present embodiment, a charge / discharge circuit 62 is provided in the drive circuit 42 in order to suppress a steep transition of the control signal IS1. The charge / discharge circuit 62 includes inverter circuits INV6 to INV8, a capacitor C1, PMOS transistors TP31 to TP33, and an NMOS transistor TN31. The charge / discharge circuit 62 has a function of charging the capacitor C1 to the level of the external power supply voltage VDD and a capacitor of the NAND gate 61. It has a function of designating the discharge timing of C1. The capacitor C1 is charged by the charging transistor TP31 during the period when the control signal IS1 is at the H level. The discharge timing of the capacitor C1 is the timing when the output of the inverter circuit INV7, which is the waveform shaping signal of the differential amplification voltage OUT1, turns on the transistor TN31, and the timing when the NMOS (discharge element) constituting the NAND gate 61 is turned on. It is specified in the earlier one. The transistors TP32 and TP33 are controlled by the control signal IS1 and the output of the inverter circuit INV8 which is an inverted signal thereof. Since the transition waveform from the H level to the L level of the control signal IS1 can be handled as an approximate linear waveform, the discharge time can be specified by the driving force of the capacitor C1 and the NMOS (discharging element) constituting the NAND gate 61.

  There may be a case where the internal power supply voltage Vint fluctuates below a predetermined range with respect to the first reference voltage Vref1 for some reason in the standby state or the semi-standby state. At this time, when the level of the differential amplification voltage OUT1 becomes a level sufficient to bring the output of the inverter circuit INV5 to the L level, the control signal IS1 is set to the H level to increase the bias current of the operational amplifier 13. As a result, the response of the negative feedback circuit composed of the operational amplifier 13 and the drive transistor DRV1 is enhanced, and the internal power supply voltage Vint is quickly raised to a predetermined level. After that, when the differential amplification voltage OUT1 becomes a level sufficient to bring the output of the inverter circuit INV5 to the H level, the control signal IS1 transitions approximately as a linear waveform by the charge / discharge circuit 62 and the NAND gate 61. That is, the control signal IS1 changes slowly due to the function of the charge / discharge circuit 62. As a result, the response of the negative feedback circuit is gradually lowered.

  In the present embodiment, the capacity inside the charge / discharge circuit 62 is used to change the control signal IS1 slowly, but the technical idea of the present invention is not limited to this. For example, a method may be used in which a resistor connected to a power supply via a switch is connected to the output terminal of the NAND gate 61 and the switch is controlled by a control signal IS1. Alternatively, a method of adding inductance to the output terminal of the NAND gate 61 may be used.

  FIG. 11 is a waveform diagram showing an operation example of the step-down circuit 1.

  Now, when the control signal / CE becomes L level and the internal circuit 3 (SRAM) becomes active and the internal clock signal QPCB generated in the internal circuit 3 becomes L level, the current consumption IL of the internal circuit 3 (Load current) increases, and the internal power supply voltage Vint decreases and fluctuates in response to this change (two-dot chain line in broken line A in the figure).

  In the present embodiment, in order to prevent this voltage drop, control signal IS1 is raised at the falling edge of internal clock signal QPCB. That is, when active, the control signal IS1 is raised in synchronization with the fall of the internal clock signal QPCB, and the current value of the current source 14 is increased.

  After that, when the operation of the internal circuit 3 is completed (data processing operation is completed), the internal circuit 3 shifts to the semi-standby state. At this time, the consumption current IL of the internal circuit 3 is almost eliminated. In the present embodiment, this quasi-standby state is detected by the control circuit 15, and the control circuit 15 is provided on the condition that the voltage difference between the internal power supply voltage Vint and the first reference voltage Vref1 is within a predetermined range. When detecting the semi-standby state, the control signal IS1 is lowered to reduce the current consumption of the step-down circuit 1 itself.

  However, as described above, if the control signal IS1 is suddenly lowered at this time, the internal power supply voltage Vint varies in an increasing direction depending on the current consumption IL (load current) of the internal circuit 3 at that time. Occurs. Therefore, in order to avoid such fluctuations, in the present embodiment, when the quasi-standby state is detected by the control circuit 15, the control signal IS1 is supplied to the charge / discharge circuit 62 as shown in the broken line B in the figure. It was decided that the response of the negative feedback circuit would be gradually shifted to the standby level by gradually falling by the operation of. Thereby, the transient fluctuation of the internal power supply voltage Vint can be suppressed.

  As described above, the following effects can be achieved in the present embodiment.

  (1) In the present embodiment, the control circuit 15 varies the current value of the current source 14 in accordance with the voltage difference between the internal power supply voltage Vint and the first reference voltage Vref1. That is, when the voltage difference between the internal power supply voltage Vint and the first reference voltage Vref1 exceeds a predetermined range, the current value of the current source 14 is increased, and conversely, the internal power supply voltage Vint and the first reference voltage Vref1 When the voltage difference is within a predetermined range and the internal power supply voltage Vint is stable, the current value of the current source 14 is suppressed to a small current value. As a result, it is possible to improve the operation response according to the potential fluctuation of the internal power supply voltage Vint while reducing the current consumption.

  (2) In the present embodiment, when active, the current value of the current source 14 is further variably controlled based on an external clock signal (in this embodiment, the internal clock signal QPCB generated by the internal circuit 3). The configuration is as follows. Specifically, the control signal IS1 is raised in synchronization with the fall of the internal clock signal QPCB (strictly, QPCB2), and the current value of the current source 14 is increased. As a result, the operation response of the step-down circuit 1 can be optimized at the start of the active operation.

  (3) In the present embodiment, even when active, when the control circuit 15 detects that the voltage difference between the internal power supply voltage Vint and the first reference voltage Vref1 is within the predetermined range, The current value of the current source 14 is decreased. That is, when the quasi-standby state is detected by the control circuit 15 even when active, the current value of the current source 14 is decreased. Thereby, steady current consumption at the time of active can be suppressed, and current consumption at the time of active can be reduced.

(4) In the present embodiment, when the control signal IS1 is lowered in order to decrease the current value of the current source 14 when the quasi-standby state is detected, the voltage level is set by the operation of the charge / discharge circuit 62. Slowly fall (according to the discharge operation of the capacitor C1). As a result, the potential fluctuation of the internal power supply voltage Vint caused by sharply lowering the control signal IS1 (
Rise) can be suitably suppressed.

  (5) In the present embodiment, the first current source 35 and the second current source 36 connected in parallel constitute the current source 14, and the voltage difference between the internal power supply voltage Vint and the first reference voltage Vref1 is Only the first current source 35 is activated when the internal power supply voltage Vint is stable within a predetermined range. At this time, in the present embodiment, the NMOS transistor TN7 constituting the first current source 35 is weakly inverted by the first control voltage VN. Thereby, the current consumption of step-down circuit 1 when the potential of internal power supply voltage Vint is stable during standby or quasi-standby, which is the operation mode of internal circuit 3, can be reduced as much as possible.

  (6) In the present embodiment, the second current source 36 of the current source 14 is configured to have the gate voltage Vgs = 0 by using the NMOS transistor TND2 having the low threshold characteristic. With such a configuration, as long as the source-drain voltage Vds of the transistor TND2 is set within an appropriate range, the transistor TND2 operates in the saturation region at the gate voltage Vgs = 0, and thus a constant current is stably supplied. An excellent current source that can be used can be configured, and a simple configuration that does not require an additional circuit for controlling the current source can be achieved.

  (7) In the present embodiment, the drive transistor DRV1 is configured using an NMOS transistor, and the internal power supply terminal (supply terminal for the internal power supply voltage Vint) of the internal circuit 3 is connected to the source thereof. With such a configuration, it is possible to make a configuration in which the drive transistor DRV1 itself feedback-controls the amount of current flowing through the drive transistor DRV1 following the potential fluctuation of the internal power supply voltage Vint. Thereby, the responsiveness of the drive transistor DRV1 can be improved. Furthermore, in the present embodiment, the current driving capability of the driving transistor DRV1 can be improved (compared to the case of the enhancement type) by using the NMOS transistor having the low threshold characteristic. . This contributes to further reducing the element size of the drive transistor DRV1, and further reducing the parasitic capacitance of the drive transistor DRV1 to increase the response (switching speed) of the transistor DRV1. In addition, since the low threshold characteristic MOS transistor can be designed so that the output resistance is smaller than that of the enhancement type, the low threshold characteristic MOS transistor is used as an output driver of a step-down circuit as a constant voltage source. Using is an excellent choice. As a result, the response (feedback speed) of the negative feedback circuit is improved. As a result, sufficient phase compensation can be realized without the phase compensation circuit 105 (FIG. 12) required in the conventional step-down circuit. .

  (8) In the present embodiment, the element size ratio of the pair of PMOS transistors TP8 and TP9 constituting the current mirror circuit of the operational amplifier 13 is set to be 1 for the input side transistor (TP8) and the output side transistor (TP9). x (where x> 1). In such a configuration, although the amplification factor of the operational amplifier 13 decreases, the oscillation of the operational amplifier 13 (in the negative feedback circuit) can be suitably suppressed. As a result, sufficient phase compensation can be realized without the phase compensation circuit 105 required in the conventional step-down circuit.

  (9) As described in (7) above, the step-down circuit 1 can be downsized by reducing the element size of the drive transistor DRV1.

  (10) Further, as described in (7) and (8) above, by eliminating the phase compensation circuit 105 of the negative feedback circuit, the step-down circuit 1 can be further reduced in size.

(11) In the present embodiment, the current sources 31 and 32 (PMOS transistors in the present embodiment) of the reference voltage generation circuit 12 for generating the first and second reference voltages Vref1 and Vref2 are supplied from the bias voltage generation circuit 11. A weak inversion operation is performed by the second control voltage VP. As a result, the reference voltage generation circuit 12 can be operated with a low current consumption, so that the current consumption in the step-down circuit 1 can be further reduced.

  (12) In the present embodiment, the current source of the bias voltage generation circuit 11 for generating the first and second control voltages VN and VP for controlling the transistor to perform a weak inversion operation is used as the NMOS transistor TND1 having the low threshold characteristic. And the gate voltage Vgs = 0. In such a configuration, as long as the transistor TND1 operates in the weak inversion region, the temperature dependence of the drain current (Ids) of the transistor TND1 is approximately 0.5th power of the absolute temperature T. When the transistor TND1 linearly operates in the strong inversion region, the temperature dependence of the drain current (Ids) of the transistor TND1 becomes approximately −0.5 to the absolute temperature T. Overall, if the device is designed so that the transistor TND1 biased with the gate voltage Vgs = 0 operates in the relaxation region (intermediate region between the weak inversion region and the strong inversion region) due to the continuity of the physical phenomenon, It is expected that (Ids) will be extremely less dependent on the absolute temperature T. On the other hand, the only variable that must be controlled for process variations is the threshold value (Vt) of the transistor TND1. This is within practical constraints from the viewpoint of manufacturing management. In other words, even in a CMOS circuit, the first and second control voltages VN and VP can be used as gate bias potentials, and a constant current source can be easily and accurately created. Become.

  In addition, you may implement the said embodiment, changing into the following aspects (modifications).

  (Modification 1) In the above embodiment, in order to maintain the internal power supply voltage Vint at the set voltage with high accuracy, the current source is based on two types of reference voltages, the first and second reference voltages Vref1 and Vref2. Although the control signal IS1 for controlling the current value of 14 is generated, it is not always necessary to use these two types.

  (Modification 2) In the above embodiment, the drive transistor DRV1 is configured by the NMOS transistor having the low threshold characteristics, and further, the oscillation of the operational amplifier 13 is suppressed (the amplification factor of the operational amplifier 13 is suppressed). Although the negative feedback circuit configuration that enables sufficient phase compensation even without the phase compensation circuit 105 (FIG. 12) has been realized, sufficient phase compensation can be achieved only with either of the above configurations. In this case, it is not always necessary to have the above-described configurations.

  (Modification 3) In the above embodiment, the buffer circuit 17 is provided in order to improve the controllability of the step-down circuit 1. However, these may be omitted if the operation of the step-down circuit 1 is not affected.

  (Modification 4) Other design matters relating to the configuration of the step-down circuit 1 of the above embodiment can be changed as appropriate within the scope of the technical idea of the present invention.

1 is a block circuit diagram illustrating a configuration of a step-down circuit according to an embodiment. The block diagram which shows the structure of the semiconductor device provided with the step-down circuit and its load circuit (internal circuit). The circuit diagram which shows the detailed circuit structure of a bias voltage generation circuit. The circuit diagram which shows the detailed circuit structure of a reference voltage generation circuit. The characteristic view which shows the voltage characteristic of a 1st and 2nd reference voltage. It is a circuit diagram which shows the detailed circuit structure of an operational amplifier, (a) is a circuit diagram which shows an operational amplifier, (b) is a circuit diagram which shows the current source of an operational amplifier. The characteristic view which shows the Id-Vgs characteristic of the NMOS transistor which has a normal threshold value characteristic, and the NMOS transistor which has a low threshold value characteristic. The block circuit diagram which shows the detailed circuit structure of a control circuit. The circuit diagram which shows the detailed circuit structure of a differential amplifier circuit. The circuit diagram which shows the detailed circuit structure of a drive circuit. The wave form diagram which shows the operation example of a step-down circuit. The block circuit diagram which shows the structure of the conventional step-down circuit.

Explanation of symbols

  1: Step-down circuit, 2: Semiconductor device, 3: Internal circuit, 11: Bias voltage generation circuit, 12: Reference voltage generation circuit, 13: Operational amplifier, 14: Current source of operational amplifier, 15: Control circuit, 16: Output adjustment circuit 17: buffer circuit, 18: current source of buffer circuit, 19: feedback circuit, 35: first current source, 36: second current source, 37: switch element, 41: differential amplifier circuit, 42: drive circuit, 43: waveform shaping circuit, 51: first differential amplifier, 52: second differential amplifier, 62: charge / discharge circuit, 105: phase compensation circuit, C1: capacity, DRV1: drive transistor, IS1: control signal, OUT1: Differential amplification voltage, CLK: Clock signal, QPCB: Internal clock signal, SLEEP: Activation signal, VDD: External power supply voltage, Vint: Internal power supply voltage, Vout1: Drive power , VN: first control voltage, VP: second control voltage, Vref1: first reference voltage, Vref2: the second reference voltage.

Claims (9)

In a step-down circuit that generates an internal power supply voltage obtained by stepping down an external power supply voltage based on a predetermined reference voltage, and supplies the internal power supply voltage to a load circuit,
Negative feedback comprising: an operational amplifier that generates a drive voltage according to a voltage difference between the voltage based on the internal power supply voltage and the reference voltage; and a drive transistor that outputs the internal power supply voltage according to the drive voltage Circuit,
A control circuit for generating a control signal for variably controlling the response speed of the negative feedback circuit when a voltage difference between the internal power supply voltage and the reference voltage exceeds a predetermined range;
A step-down circuit comprising: The control circuit variably controls the response speed of the negative feedback circuit based on an external clock signal when the load circuit is in an active state.
The step-down circuit according to claim 1. The response speed of the negative feedback circuit is variably controlled by controlling the current value of a current source that supplies current to the operational amplifier.
The step-down circuit according to claim 1. The control circuit detects a quasi-standby state in which the load circuit is in an active state and a voltage difference between the internal power supply voltage and the reference voltage is within the predetermined range. In the quasi-standby state, a current is supplied to the operational amplifier. Controlling the current value of the current source supplying the same current value as when the load circuit is in a standby state;
The step-down circuit according to claim 1. The current source is configured by connecting in parallel a first current source configured by a transistor operating in a weak inversion region and a second current source controlled based on the control signal output from the control circuit. To be
The step-down circuit according to claim 3 or 4. The control circuit is
A differential amplifier circuit for amplifying a voltage difference between the reference voltage and the internal power supply voltage to generate a differential amplification voltage;
A drive circuit that generates the control signal for variably controlling the current value of the current source of the operational amplifier based on the differential amplification voltage;
The step-down circuit according to claim 3 or 4. The control circuit slowly changes the control signal when a voltage difference between the internal power supply voltage and the reference voltage changes from a state exceeding the predetermined range to a state within the predetermined range;
The step-down circuit according to any one of claims 1 to 6. The drive transistor is constituted by an NMOS transistor having a drain connected to the external power supply voltage and a source connected to the internal power supply voltage.
The step-down circuit according to any one of claims 1 to 7. A transistor operating in a weak inversion region has a current source, and includes a reference voltage generation circuit that generates the reference voltage based on the external power supply voltage.
The step-down circuit according to any one of claims 1 to 8.

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