JP2006164024A - On-chip bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To store an address decoding result in a relatively small FIFO size, and when access is continuously performed and the FIFO becomes full, a master device waits for the next transaction regardless of the status of a slave device or a bus. To provide an on-chip bus system that solves the problem of lowering the throughput of the entire system.
When storing a decoding result of an address necessary for connecting a master device and a slave device in a split bus write data channel in a FIFO, the contents are separated into a decoding result and an accumulated number of times. When the same decoding result continues, only the number of consecutive times for one decoding result is stored to improve the use efficiency of the FIFO.
[Selection] Figure 2

Description

  The present invention relates to an on-chip bus system that supports a split bus, and more specifically, is characterized by sequentially storing a decoding result of an address necessary for connecting a master device and a slave device of a write data channel together with an accumulated number of times. It relates to an on-chip bus system.

  In recent years, split buses that can be controlled by separating an address bus and a data bus are becoming mainstream among on-chip buses used in system LSIs. Compared with a conventional bus protocol that transmits and receives data immediately after issuing an address, once an address is issued, it is possible to read or write data at an arbitrary timing, and the latency is low as in the past. The slave device does not occupy the bus, and the bus throughput can be improved. In addition, since it is possible to continuously advance the address, the slave device can efficiently process a series of accesses. FIG. 7 shows a transfer example of the address channel and data channel of the split bus.

  Usually, the split bus is either an on-chip bus in which a master device and a slave device that perform point-to-point data communication are connected by a crossbar switch, or an on-chip bus in which multiple devices are shared by one address bus and a data bus (For example, refer to Patent Document 1). In either case, the address output from the master device is first decoded in the address channel, and the master device and slave device of the corresponding address channel are connected based on the result. In the connected address channel, the address is transferred from the master device to the slave device. Next, in the data channel, in general, in the case of writing, even if the master device outputs write data, the corresponding slave device is unknown, so it is necessary to sequentially store the results decoded by the address channel. That is, when the master device outputs write data, the stored decoding results are sequentially read, and the master device and slave device of the corresponding data channel are connected based on the results. In the connected data channel, write data is transferred from the master device to the slave device. In the case of reading, generally an ID that can be recognized by the issued master device is added to each transaction, and the slave device can recognize the corresponding master device by returning this transaction ID together with the read data. The master device and slave device of the channel are connected and can receive read data.

  FIG. 8 shows an aspect of a general on-chip bus system. Here, for ease of explanation, only the address channel and the data channel for writing are shown in the case where there are two master devices and two slave devices. In addition, here, as an example, an on-chip bus that performs point-to-point data communication using a crossbar switch is shown. The on-chip bus system 10 includes a central processing unit (CPU) 11A and a DMA controller (DMAC) 11B as master devices, a memory controller (MEMC) 12A and a programmable IO (PIO) 12B as slave devices, and a crossbar that interconnects them. The switch 13 is configured. FIG. 9 shows a state of a switch for connecting each master device and slave device in the crossbar switch 13. Each switch includes slave selection circuits 131 and 133 that connect the corresponding master device and slave device of the address channel and the write data channel, an address decoder 132 that decodes the address channel and controls the slave selection circuit 131, and an address decoder This is composed of a FIFO 134 that sequentially stores the decoding results 132 and controls the slave selection circuit 133 according to the stored contents when the master device outputs write data.

  Hereinafter, an operation in which the CPU 11A writes data to the MEMC 12A will be described. First, the CPU 11A issues a desired address to which the MEMC 12A is mapped. The issued address is passed to the crossbar switch 13 and decoded by the internal address decoder 132. Based on the decoded result, the slave selection circuit 131 for the address channel selects the MEMC 12A and connects the CPU 11A and the MEMC 12A. At this time, the decoding result is stored in the FIFO 134 at the same time. If the FIFO 134 is in a full state, the address channel is not connected to the MEMC 12A, and the issued address is waited until the FIFO 134 is vacant with the crossbar switch 13. After the connection, the crossbar switch 13 promptly transfers the address issued by the CPU 11A to the MEMC 12A. Next, the CPU 11A issues write data. The crossbar switch 13 reads the decoding result stored in the FIFO 134, and based on the decoding result, the data channel slave selection circuit 133 selects the MEMC 12A in the same manner as the address channel and connects the CPU 11A and the MEMC 12A. After the connection, the crossbar switch 13 promptly transfers the write data issued by the CPU 11A to the MEMC 12A. The write data may be issued at the same time as the address, but is waited until the decoding result is stored in the FIFO 134 and the data channel is connected to the crossbar switch 13. Further, since the master device issues write data corresponding to the order of the issued addresses, it is possible to take correspondence between the addresses and data by reading the decoding results in the order stored in the FIFO 134.

  Next, an operation in which the CPU 11A writes fixed-length burst data to the MEMC 12A will be described. The basic operation is the same as single data writing. After issuing the address, the CPU 11A issues, for example, 4-beat write data. In general, in the case of fixed-length burst transfer, the master device often issues only the head address of the address, and the FIFO 134 stores one decode result for each burst transfer. On the other hand, with respect to write data, there is a last signal indicating the end of each data transfer including normal burst transfer. By not updating the decoding result stored in the FIFO 134 until this signal is asserted, burst data can be transferred. It is possible to respond. In other words, in the case of single write, the CPU 11A asserts the last signal every time each write data is issued, so that the decode result of the FIFO 134 is read sequentially, and the slave selection circuit 133 for the data channel selects the MEMC 12A based on the decode result. Select and connect the CPU 11A and MEMC 12A. In the case of burst transfer, the same applies until the CPU 11A issues an address and stores the decoding result in the FIFO 134. Next, the CPU 11A issues burst data of 4 beats, but the slave selection circuit 133 for the data channel selects the MEMC 12A based on the decoding result of the same FIFO 134 until the last signal is asserted in the fourth data transfer and selects the CPU 11A. And MEMC 12A are connected. FIG. 10 shows an example of address channel and data channel transfers during burst transfer of the split bus, and the last signal assert timing.

As described above, even if the master device continuously issues addresses regardless of single or burst transfer, the decoding result of the address is sequentially stored in the FIFO 134, and when the master device outputs the write data, the decoding result is taken out and dealt with. By connecting a master device and a slave device to perform data writing, it is possible to perform data writing at an arbitrary timing, and it functions as a split bus. The operations of the DMAC 11B and the PIO 12B are the same. However, the normal MEMC 12A concentrates accesses from a plurality of master devices as compared to the PIO 12B which is an IO area. In other words, each master device often accesses the MEMC 12A continuously, and the same decoding result is continuously stored in the FIFO 134 of each switch of the crossbar switch 13.
JP 07-105129 A

  As described above, in the prior art, the address decoding results are sequentially stored, and when the master device outputs write data, the decoding results are extracted and the corresponding master device and slave device are connected at any timing. Data was being written. Here, it is necessary to store the address decoding results in the data channel for the number of times of address advance. Further, the stored decoding result must be held until the master device issues write data. However, the FIFO size for storing the address decoding result is relatively small, and when the access is continuously full, the master device waits for the next transaction regardless of the status of the slave device or the bus. There was a problem that the throughput of the entire system was lowered.

  In order to achieve the above object, the system according to the first aspect of the present invention includes a decoding means for decoding an address output from a master device on an on-chip bus corresponding to a split bus and a corresponding address based on a result of the decoding means. A storage means for connecting a master device and a slave device of the channel, and in the write data channel, a storage means for sequentially storing the result of the decoding means together with the cumulative number, and a master device of the corresponding data channel based on the contents of the storage means And connecting means for connecting the slave device.

  A system according to a second aspect of the present invention is characterized in that in the on-chip bus system, the system further comprises storage means for sequentially storing the transaction ID together with the cumulative number simultaneously with the result of the decoding means.

  The present invention separates the contents into the decoding result and the cumulative number when storing the decoding result of the address necessary for connecting the master device and the slave device in the data bus for writing on the split bus in the FIFO. When the same decoding result is continuous, it is possible to improve the use efficiency of the FIFO by storing only the continuous number of times for one decoding result. In particular, each master device often accesses a specific slave device such as a memory controller continuously, and since the same decoding result is continuously stored in the FIFO, the efficiency of the specification of the FIFO is further increased. It is possible to improve.

Example 1
FIG. 1 shows an embodiment of the on-chip bus system of the present invention. Here, for ease of explanation, only the address channel and the data channel for writing are shown in the case where there are two master devices and two slave devices. Also, here, as an example, an on-chip bus that performs point-to-point data communication using a crossbar switch is shown, but the bus configuration is not limited to this as in the conventional example. The on-chip bus system 10 includes a central processing unit (CPU) 11A and a DMA controller (DMAC) 11B as master devices, a memory controller (MEMC) 12A and a programmable IO (PIO) 12B as slave devices, and a crossbar that interconnects them. The switch 14 is configured. FIG. 2 shows a state of a switch for connecting each master device and slave device in the crossbar switch 14. Each switch sequentially stores the slave selection circuits 141 and 143 for connecting the corresponding master device and slave device of the address channel and the write data channel, the address decoder 142 for decoding the address channel address, and the decoding result of the address decoder 142, respectively. When the master device outputs write data, it comprises a FIFO 144 that controls the slave selection circuit 143 according to the stored contents. Further, FIG. 3 shows a uniform state of the FIFO 144. The FIFO 144 is composed of a FIFO queue, a write control circuit, and a read control circuit. The FIFO queue is composed of an area for storing a decoding result and an area for storing the cumulative number of each decoding result.

  Hereinafter, an operation in which the CPU 11A writes data to the MEMC 12A will be described. First, the CPU 11A issues a desired address to which the MEMC 12A is mapped. The issued address is passed to the crossbar switch 14 and decoded by the internal address decoder 142. Based on the decoded result, the address channel slave selection circuit 141 selects the MEMC 12A and connects the CPU 11A and the MEMC 12A. At this time, the decoding result is simultaneously stored in the FIFO 144. If the FIFO 144 is full, the address channel is not connected to the MEMC 12A, and the issued address is waited until the FIFO 144 is vacant with the crossbar switch 14. After the connection, the crossbar switch 14 promptly transfers the address issued by the CPU 11A to the MEMC 12A. Next, the CPU 11A issues write data. The crossbar switch 14 reads the decoding result stored in the FIFO 144, and based on the decoding result, the data channel slave selection circuit 143 selects the MEMC 12A and connects the CPU 11A and the MEMC 12A. After the connection, the crossbar switch 14 promptly transfers the write data issued by the CPU 11A to the MEMC 12A. The write data may be issued at the same time as the address, but is waited until the decoding result is stored in the FIFO 144 and the data channel is connected to the crossbar switch 14. The write data may be issued at the same time as the address, but is waited until the decoding result is stored in the FIFO 134 and the data channel is connected to the crossbar switch 13. Further, since the master device issues write data corresponding to the order of the issued addresses, it is possible to take correspondence between the addresses and data by reading the decoding results in the order stored in the FIFO 144.

  Next, an operation in which the CPU 11A continuously writes data to the MEMC 12A will be described. The basic operation is the same as the above-described writing. The CPU 11A issues a desired address to which the MEMC 12A is continuously mapped before issuing write data. In this case, the same decoding result is continuously written in the FIFO 144. However, if the same result is compared with the decoding result stored in advance in the FIFO 144, the decoding result is not newly written and the first decoding result is not written. Only the cumulative count value is incremented. FIG. 4 shows a flow of write operation and read operation of the FIFO 144. This operation will be described below. First, it is confirmed whether the FIFO 144 is in the FULL state (1). If it is in the FULL state, the address channel is not connected to the MEMC 12A, and the issued address is waited until the FIFO 144 is vacant with the crossbar switch 14. Next, if the FIFO 144 is not in the FULL state, the inputted decode result is compared with the latest decode result value stored in the FIFO 144 (2). At this time, if the values of the decoding results are different, the decoding result inputted as it is is written in the FIFO 144 as a cumulative number of 1 (6). If the decoding result values are the same, the cumulative number of decoding results is confirmed (3). Here, when the cumulative number is the maximum value that can be stored, the decoding result inputted as it is is newly written into the FIFO 144 as the cumulative number as 1 (6). If the cumulative number is not the maximum value that can be stored, only the cumulative number of decoding results stored in the FIFO 144 is incremented (5). However, when the same area is read simultaneously with the writing (4), the writing operation is terminated without doing anything. Therefore, when the CPU 11A issues four addresses continuously to the MEMC 12A, the content of the FIFO 144 is stored as a cumulative number of four for one decoding result writing. Subsequently, the CPU 11A issues write data corresponding to the previously issued address. First, the FIFO 144 checks whether the FIFO queue is in the EMPTY state (7). If it is in the EMPTY state, the data channel is not connected to the MEMC 12A, and the issued data is waited until the decoding result is stored in the FIFO 144 with the crossbar switch 14 and the data channel is connected. Next, if the FIFO 144 is not in the EMPTY state, the oldest decoding result is read from the FIFO 144, and the data channel slave selection circuit 143 selects the MEMC 12A based on the content, and connects the CPU 11A and the MEMC 12A. At this time, it is confirmed whether writing to the same area is performed simultaneously with reading (8). If writing is performed at the same time, the read operation is terminated without doing anything with respect to the contents of the FIFO. If writing is not performed at the same time, the cumulative number of read decoding results is confirmed (9). At this time, when the cumulative number is 2 or more, only the cumulative number is decremented with respect to the read decoding result (11). When the cumulative number is 1, the read decoding result is taken out from the FIFO. Therefore, when the CPU 11A issues four consecutive addresses to the MEMC 12A, every time the CPU 11A issues write data sequentially, the cumulative number is decremented and the decode result is taken out from the FIFO 144 together with the fourth write data issuance. .

  Next, an operation in which the CPU 11A writes fixed-length burst data to the MEMC 12A will be described. The basic operation is the same as single data writing. After issuing the address, the CPU 11A issues, for example, 4-beat write data. In general, in the case of fixed-length burst transfer, the master device often issues only the head address of the address, and the FIFO 144 stores one decoding result for each burst transfer. On the other hand, with respect to write data, there is a last signal indicating the end of each data transfer including normal burst transfer. By not updating the decoding result stored in the FIFO 144 until this signal is asserted, the burst data is also transferred. It is possible to respond. That is, in the case of single write, since the CPU 11A asserts the last signal every time each write data is issued, the decoding result of the FIFO 144 is sequentially read, and the data channel slave selection circuit 143 selects the MEMC 12A based on the decoding result. Select and connect the CPU 11A and MEMC 12A. In the case of burst transfer, the CPU 11A issues an address and the decoding result is stored in the FIFO 144. Next, the CPU 11A issues 4-beat burst data, but the slave selection circuit 143 for the data channel selects the MEMC 12A based on the decoding result of the same FIFO 144 until the last signal is asserted in the fourth data transfer and selects the CPU 11A. And MEMC 12A are connected.

  As described above, according to the present invention, even if the master device continuously issues an address regardless of single or burst transfer, the decoding result of the address channel is sequentially stored in the FIFO 144 and the master device outputs the write data. In this case, the decoding result is taken out and the corresponding master device and slave device are connected, so that data can be written at an arbitrary timing, and the function as a split bus is achieved. The operations of the DMAC 11B and the PIO 12B are the same. Further, when each master device continuously accesses a special slave device such as a memory controller, the FIFO 144 uses only one decoding result as a FIFO queue, so that the use efficiency of the FIFO can be improved. .

(Example 2)
FIG. 5 shows another embodiment of the present invention. The bus configuration is the same as in the first embodiment, and the on-chip bus system 10 includes a central processing unit (CPU) 11A and a DMA controller (DMAC) 11B as master devices, and a memory controller (MEMC) 12A and programmable IO (PIO) as slave devices. 12B, and a crossbar switch 14 for interconnecting them. Each switch sequentially stores the slave selection circuits 141 and 143 for connecting the corresponding master device and slave device of the address channel and the write data channel, the address decoder 142 for decoding the address channel address, and the decoding result of the address decoder 142, respectively. When the master device outputs write data, it comprises a FIFO 145 that controls the slave selection circuit 143 according to the stored contents. Further, FIG. 6 shows a uniform state of the FIFO 145. The FIFO 145 includes a FIFO queue, a write control circuit, and a read control circuit. The FIFO queue includes an area for storing a decoding result, an area for storing a transaction ID, and an area for storing the cumulative number of each decoding result.

  The present invention is the same as the first embodiment except that the transaction ID issued by the master device at the same time as the address is stored in the FIFO 145 together with the decoding result.

The figure which showed the one aspect | mode of the on-chip bus system of Example 1 of this invention. The figure which showed the one aspect | mode of the crossbar switch of Example 1 of this invention. The figure which showed the one aspect | mode of FIFO of Example 1 of this invention. The figure which showed the operation | movement flow of FIFO of Example 1 of this invention. The figure which showed the one aspect | mode of the crossbar switch of Example 2 of this invention. The figure which showed the one aspect | mode of FIFO of Example 2 of this invention. The figure which showed the transfer example of the general split bus | bath. The figure which showed the one aspect | mode of the general on-chip bus system. The figure which showed the one aspect | mode of the crossbar switch of a general on-chip bus | bath. The figure which showed the burst transfer example of the general split bus | bath.

Explanation of symbols

10 On-chip bus system 11A Central processing unit (CPU)
11B DMA controller (DMAC)
12A Memory controller (MEMC)
12B Programmable IO (PIO)
13 Crossbar switch 131 Slave selection circuit 132 Address decoder 133 Slave selection circuit 134 FIFO
14 Crossbar switch 141 Slave selection circuit 142 Address decoder 143 Slave selection circuit 144 FIFO
145 FIFO

Claims (2)

  In the on-chip bus corresponding to the split bus, the write data channel has decoding means for decoding the address output from the master device and connecting means for connecting the master device and slave device of the corresponding address channel based on the result of the decoding means. In the on-chip bus system, there is provided storage means for sequentially storing the result of the decoding means together with the cumulative number of times, and connection means for connecting the master device and slave device of the corresponding data channel based on the contents of the storage means.   In the on-chip bus system, an on-chip bus system comprising storage means for sequentially storing a transaction ID together with a cumulative number simultaneously with a result of the decoding means.

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