JP2006173241A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a T-shaped gate electrode having a gate length further smaller than the limit of electron beam exposure in a field-effect transistor using a nitride compound semiconductor. <P>SOLUTION: An undoped GaN layer and a first n-type AlGaN layer are formed on a sapphire substrate in that order. A second n-type 25 nm-thick AlGaN layer is formed to the side at the T-shaped lower part of a PdSi gate electrode in a regrowing manner. The gate length at the gate lower part of the T-shaped gate electrode is 100 nm or shorter. The side wall where the second n-type AlGaN layer and the T-shaped gate electrode are in contact with each other is covered with the oxide film of the AlGaN layer and an AlGaNOx layer. An air gap is formed to the side at the lower part of the T-shaped gate electrode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a field effect transistor using a nitride semiconductor that can be applied to a high-frequency transistor used in a transmission / reception circuit of a mobile phone or a millimeter wave radar, and a method for manufacturing the same.

Nitride compound semiconductors typified by GaN, so-called group III nitride semiconductors, are wide-cap semiconductors where the forbidden band width of GaN is as large as 3.4 eV at room temperature, which has a large dielectric breakdown electric field and a saturation drift velocity of electrons such as GaAs. It has the advantage of being larger than compound semiconductors or Si semiconductors. For this reason, it has been attracting attention as a high-frequency and high-power transistor, and research and development are actively conducted. In the AlGaN / GaN heterostructure, charges are generated at the heterointerface due to spontaneous polarization and piezopolarization on the (0001) plane, and a sheet carrier concentration of 1 × 10 ¹³ cm ^-2 or more can be obtained even when undoped. The use of a two-dimensional electron gas at the heterointerface and the realization of a heterojunction field effect transistor with a higher current density is also advantageous for higher output. In general, it is the most effective means to shorten the gate length in order to improve the high frequency characteristics of the field effect transistor. For example, in order to improve the maximum oscillation frequency called fmax, the mutual conductance gm corresponding to the gain is reduced. It is necessary to increase the capacitance, further reduce the capacitance around the gate, and reduce the resistance of the gate electrode. As a gate electrode structure capable of satisfying the above requirements, a T-shaped or mushroom-type gate electrode structure and process have been proposed and put to practical use in conventional GaAs and InP-based compound semiconductors. In the case of GaN-based semiconductors, there have been reported examples of studies on such T-shaped gates, and field effect transistors excellent in high-frequency characteristics such as fmax have already been reported. In GaN-based semiconductors, the parasitic resistance typified by the ohmic contact resistance of the source / drain electrodes tends to be large, so it is necessary to increase the maximum electric field under the gate to effectively use the large saturation drift velocity. If a device with a shorter gate length than conventional compound semiconductors is not realized, it will be difficult to achieve high-frequency characteristics equivalent to or exceeding those of GaAs and InP.

  Hereinafter, an example of a conventional field effect transistor structure using a nitride semiconductor having a T-shaped gate electrode will be described.

  FIG. 5 is a sectional view showing a structure of a short gate length field effect transistor using a GaN-based semiconductor in a conventional example (see Non-Patent Document 1). In the figure, 501 is a sapphire substrate, 502 is a low-temperature GaN buffer layer, 503 is an undoped GaN layer, 504 is an n-type AlGaN layer, 505 is a source electrode, 506 is a drain electrode, and 507 is a gate electrode.

Here, a low-temperature GaN buffer layer, an undoped GaN layer, and an n-type AlGaN layer are formed in this order on a sapphire substrate, and source and drain electrodes are formed on the n-type AlGaN layer. A T-shaped gate electrode is formed between the source and drain electrodes. The lower dimension of the T-shaped electrode, the so-called gate length, is about 150 nm. Here, the T-shaped gate electrode is formed by forming a three-layer resist structure, electron beam evaporation, and lift-off. The lower layer and the uppermost layer are formed by using a resist such as PMMA that can be exposed to an electron beam. Specifically, the uppermost PMMA resist is exposed to a size of about 1 μm, and the second layer PMGI resist is opened with a developer. At this time, wrinkles are formed in the uppermost PMMA resist. Subsequently, electron beam exposure is performed on the lowermost PMMA resist with a size of 150 nm in the opening. Subsequently, a Ni / Pt / Au electrode is formed by electron beam evaporation, and a T-shaped gate electrode is formed by lift-off. For element isolation, the n-type AlGaN layer other than the device region is removed by, for example, dry etching. The GaN field effect transistor having the T-shaped gate electrode has a large mutual conductance, a reduced gate peripheral capacitance, a low gate resistance, and an excellent high frequency characteristic.
YFWu et al., International Electron Devices Technical Meeting 2003 p579.

  However, in the GaN field effect transistor having a T-shaped gate electrode and the manufacturing method thereof shown in FIG. 5, even if electron beam exposure is used in the T-shaped gate formation step, the shortening of the gate length is less than 100 nm. Considering the yield and reproducibility, it is very difficult, and it is necessary to form three layers of photoresist, and there is a problem that the gate electrode formation process becomes expensive. There is also a problem that the gate electrode collapses easily and as a result, the yield is poor.

  In view of the above technical problems, the present invention reduces the size of the opening by forming a mask on the part where the gate electrode is to be formed and performing regrowth, and then performing regrowth in the form of lateral growth from the regrowth mask. In addition, a selective oxidation followed by a manufacturing method for forming a T-shaped gate electrode enables the formation of a T-shaped gate electrode having a gate length smaller than the limit of electron beam exposure, such as stepper exposure. An object of the present invention is to provide a GaN-based field effect transistor having a T-shaped gate electrode and a method for manufacturing the same.

  In order to solve the above-described problems, the field effect transistor of the present invention has a configuration described below.

  That is, a second semiconductor layer having an opening is formed on the first semiconductor layer including a heterostructure having a two-dimensional electron gas, and the second semiconductor layer is oxidized on the side wall and the upper portion. A T-shaped gate electrode is formed in contact with the first semiconductor layer exposed at the portion, and a gap is formed on the side below the T-shaped gate electrode and below the second semiconductor layer. ing. The oxide film can be formed thicker at the side wall portion, and the opening width can be made smaller than the opening size of the second semiconductor layer during regrowth. Therefore, a short gate length of about 100 nm can be realized by using, for example, stepper exposure without using electron beam exposure, so that it is possible to realize a field effect transistor having a short gate length with good reproducibility at lower cost. It becomes. Further, due to the gap, it is possible to reduce the parasitic capacitance around the gate electrode, and to realize a GaN field effect transistor having excellent high frequency characteristics, for example, a high maximum oscillation frequency and a small noise figure. Here, the gap portion may be filled with, for example, a SiN film to suppress a so-called current collapse phenomenon. Further, it may be formed such that a step is formed in the heterostructure containing the two-dimensional electron gas and the second semiconductor layer is regrown, and the series resistance is further reduced.

  Specifically, the field effect transistor of the present invention includes a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an opening formed in the second semiconductor layer. And a gate electrode provided in the opening, and a gap formed between the gate electrode and the second semiconductor layer.

  With this configuration, the gate is in contact with the first semiconductor layer with a gap on the side, and parasitic capacitance around the gate electrode is reduced, and a field effect transistor excellent in high frequency characteristics can be realized. It becomes.

  The field effect transistor of the present invention preferably further includes an insulating film formed on the second semiconductor layer and in contact with the gate electrode. According to this preferable configuration, the gate electrode can be formed so as to be sandwiched between the second semiconductor layer and the insulating film, and the gate leakage current can be reduced.

  In the field effect transistor of the present invention, it is preferable that the insulating film is an oxide film of the second semiconductor layer. According to this preferable configuration, since the insulating film formed between the gate electrode and the second semiconductor layer is formed by oxidizing the semiconductor layer, the reproducibility of the insulating film formation and the controllability of the film thickness are improved. Thus, it becomes possible to realize a field effect transistor with a high yield.

  The field effect transistor of the present invention includes a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, an opening formed in the second semiconductor layer, and the opening. A gate electrode provided in the portion, and a dielectric layer formed between the gate electrode and the second semiconductor layer.

  With this configuration, since the dielectric layer is formed between the gate electrode and the second semiconductor layer, the so-called current collapse phenomenon in which the drain current decreases during high voltage operation is suppressed, and stable high output operation is achieved. It becomes possible.

  The field effect transistor of the present invention further includes a source electrode and a drain electrode formed on the first semiconductor layer and sandwiching the gate electrode, between the source electrode and the gate electrode, and the drain electrode and the It is preferable to have an insulating film that covers the surface of the second semiconductor layer between the gate electrode. According to this preferable configuration, the surface of the second semiconductor layer between the source electrode and the drain electrode is covered with the insulating film, and it is possible to form a field effect transistor with less leakage current and high reliability.

  In the field effect transistor of the present invention, it is preferable that the thickness of the insulating film is larger at the side surface than at the upper surface of the second semiconductor layer. According to this preferable configuration, the leakage current can be further reduced, and the parasitic capacitance around the gate electrode can be reduced, so that a field effect transistor having more excellent high frequency characteristics can be realized.

  In the field effect transistor of the present invention, it is preferable that the composition ratios of constituent elements differ between the first semiconductor layer and the second semiconductor layer.

  In the field effect transistor of the present invention, it is preferable that carrier concentrations contained in the first semiconductor layer and the second semiconductor layer are different from each other. According to this preferable configuration, since the carrier concentration in the second semiconductor layer portion in contact with the source electrode and the drain electrode can be increased, the contact resistance in the ohmic electrode is reduced, the series resistance is further reduced, and the mutual conductance is reduced. A large high-performance field-effect transistor can be realized.

  The field effect transistor of the present invention includes a first semiconductor layer, a second semiconductor layer formed in a predetermined region on the first semiconductor layer and forming a heterojunction with the first semiconductor layer, A third semiconductor layer formed on the first and second semiconductor layers, an opening formed in the third semiconductor layer, and provided in the opening and in the second semiconductor layer; A gate electrode in contact therewith.

  With this configuration, it is possible to increase the carrier mobility in the channel of the transistor, and to realize a high-performance field effect transistor with a smaller series resistance and a larger mutual conductance.

  In the field effect transistor of the present invention, it is preferable that a two-dimensional electron gas is further formed at the interface of the heterojunction.

  The field effect transistor of the present invention preferably further has a gap formed between the second semiconductor layer and the third semiconductor layer.

  The field effect transistor of the present invention further includes a dielectric layer formed between the second semiconductor layer and the third semiconductor layer, and the opening is provided in the dielectric layer. preferable.

  The field effect transistor of the present invention further includes two step portions provided in the first and third semiconductor layers so as to interpose the gate electrode therebetween, and on the third semiconductor layer and the gate. It is preferable to have a source electrode and a drain electrode which are formed with electrodes interposed therebetween.

  In the field effect transistor of the present invention, it is preferable that the source electrode and the drain electrode are further disposed with the second semiconductor layer interposed therebetween. According to this preferred configuration, since the current flowing between the source and the drain flows without passing through the heterojunction potential barrier, it is possible to realize a high-performance field effect transistor having a smaller series resistance.

  In the field effect transistor of the present invention, it is preferable that the carrier concentration of the third semiconductor layer is higher than the carrier concentration of the portion of the first semiconductor layer that is in contact with the gate electrode. According to this preferred configuration, since the carrier concentration of the second semiconductor layer in contact with the source and drain electrodes is higher than that in the first semiconductor layer in contact with the gate electrode, the ohmic contact resistance is reduced and the gate leakage current is reduced. It is possible to realize a higher performance field effect transistor.

In the field effect transistor of the present invention, it is preferable that the carrier concentration of the third semiconductor layer is 1 × 10 ¹⁹ cm ⁻³ or more. According to this preferable configuration, the ohmic contact resistance is further reduced, and a field effect transistor having a smaller series resistance can be realized.

  In the field effect transistor of the present invention, it is preferable that the third semiconductor layer further has a region in which impurities are diffused and added at a high concentration below the portion in contact with the source electrode and the drain electrode. According to this preferable configuration, more impurities are added below the source / drain electrodes to reduce the ohmic contact resistance and to realize a field effect transistor having a smaller series resistance. .

In the field effect transistor of the present invention, it is preferable that the crystal defect density of the first semiconductor layer below the gate electrode is 10 ⁷ cm ² or less. According to this preferable configuration, a high-performance field-effect transistor with improved carrier mobility, lower series resistance, and higher transconductance can be realized, and more reliable field-effect transistor due to low crystal defect density. Can be realized.

  In the field effect transistor of the present invention, it is preferable that a mask layer is further formed below the gate electrode. According to this preferred configuration, the crystal defects can be reduced by lateral growth on the mask layer, the crystal defect density can be reduced regardless of the crystal defect density of the underlayer, and high performance and high reliability can be achieved. It is possible to realize a field effect transistor having the same.

  In the field effect transistor of the present invention, it is preferable that the semiconductor layer is further composed of a group III nitride semiconductor. According to this preferred configuration, a high breakdown voltage field effect transistor can be realized because of the large forbidden bandwidth and the large dielectric breakdown electric field, and the saturation drift speed is large, and a larger transconductance is obtained when the gate length is sufficiently shortened. This makes it possible to realize a higher-performance field effect transistor.

  In the field effect transistor of the present invention, it is preferable that the dielectric layer is made of SiN. According to this preferable configuration, since SiN is used as the dielectric layer, a so-called current collapse phenomenon in which the drain current decreases during high voltage operation is suppressed, and stable high output operation is possible.

  In the field effect transistor of the present invention, it is preferable that the semiconductor layer is further formed on a (0001) plane, and the gate electrode is formed in a straight line in the <11-20> direction. According to this preferable configuration, when the second semiconductor layer is formed by regrowth, the opening can be formed in a straight line, and the gate length of the gate can be formed uniformly. A field effect transistor can be realized. In addition, when a heterojunction is formed on the (0001) plane, a two-dimensional electron gas having a large sheet carrier concentration is formed due to the difference in polarization between the two layers forming the heterostructure and the heterobarrier. It is possible to realize a small field effect transistor.

  In the field effect transistor of the present invention, it is preferable that the second semiconductor layer is made of AlGaN. According to this preferable configuration, there is no hetero barrier between the second semiconductor layer and the first semiconductor layer in contact with the gate electrode, and a high-performance field effect transistor with a smaller series resistance is realized. Is possible.

  In the field effect transistor of the present invention, preferably, the first semiconductor layer is made of AlGaN, and the Al composition of the AlGaN layer of the second semiconductor layer is larger than the Al composition of the first semiconductor layer. According to this preferred configuration, since the second semiconductor layer has an Al composition larger than that of the first semiconductor layer, the sheet carrier concentration increases due to the spontaneous and piezo polarization on the side of the gate electrode, and the electric field effect has a smaller series resistance. A transistor can be realized.

In the field effect transistor of the present invention, it is preferable that the second semiconductor layer is made of Al _x Ga _1-x N (0 <x ≦ 1) and the third semiconductor layer is made of GaN. According to this preferred configuration, the third semiconductor layer is made of GaN, whereby the n-type carrier concentration can be increased, the ohmic contact resistance can be reduced, and the second semiconductor layer under the gate electrode is made Al _x Ga _1-x. By setting N (0 <x ≦ 1), a field effect transistor having a small gate leakage current can be realized.

  In the field effect transistor of the present invention, it is preferable that Si is further added to the second semiconductor layer. According to this preferred configuration, Si has a relatively shallow impurity level and lower resistance, and as a result, a field effect transistor having a smaller series resistance can be realized.

In the field effect transistor of the present invention, the semiconductor layer is further formed on a substrate, and the substrate is sapphire, SiC, GaN, AlN, MgO, LiGaO ₂ , LiAlO ₂ , or a mixed crystal of LiGaO ₂ and LiAlO _2. It is preferable that it is comprised by either. According to this preferable configuration, since a GaN-based semiconductor epitaxial growth layer having excellent crystallinity can be formed, it is possible to realize a high-performance field effect transistor with higher carrier mobility.

In the field effect transistor of the present invention, it is preferable that the mask layer further includes a SiO ₂ layer or a SiN layer. According to this preferred configuration, it is possible to realize a field effect transistor with higher performance and higher reliability without being deteriorated before and after the crystal growth temperature of the group III nitride semiconductor, easily reducing the crystal defect density. Become.

  In the field effect transistor of the present invention, the gate electrode preferably has a T-shaped cross section.

  The field effect transistor manufacturing method of the present invention includes a step of forming a first semiconductor layer on a substrate, a step of selectively forming a dielectric film mask layer on the first semiconductor layer, and the first Forming a second semiconductor layer on the semiconductor layer and the dielectric mask layer so that an opening width on the dielectric mask layer is smaller than a width of the dielectric mask layer; and A step of removing all or part of the mask layer, and a gate electrode in contact with the surface of the first semiconductor layer exposed inside the opening of the second semiconductor layer by removing the dielectric mask layer And a step of forming a source electrode and a drain electrode on the second semiconductor layer.

  With this configuration, the gate length of the gate electrode is determined by the width of the opening formed by the crystal growth of the second semiconductor layer. For example, even when the width of the dielectric film mask layer can be formed by stepper exposure, the crystal growth By controlling the time, the electron beam exposure can be reduced to such an extent that a thin gate length can be manufactured at a low cost without using the electron beam exposure.

  In the method for manufacturing a field effect transistor according to the present invention, it is preferable that the dielectric film mask layer is further removed to form a gap between the gate electrode and the first and second semiconductor layers. . According to this preferred configuration, the gate can be in contact with the first semiconductor layer in the form of a gap on the side, the parasitic capacitance around the gate electrode is reduced, and a field effect transistor excellent in high frequency characteristics is realized. It becomes possible.

  The field effect transistor manufacturing method of the present invention further selectively removes only the portion of the dielectric film mask layer exposed to the surface at the opening of the second semiconductor layer, and the gate electrode It is preferable that the dielectric mask layer is in contact with the gate electrode on the side. According to this preferred configuration, since the dielectric film mask layer is in contact with the gate electrode, a so-called current collapse phenomenon in which the drain current decreases during high voltage operation is suppressed, and stable high output operation is possible.

  The field effect transistor manufacturing method of the present invention preferably further includes a step of oxidizing the second semiconductor layer prior to the step of removing the dielectric film mask layer. According to this preferred configuration, the gate electrode can be formed on the opening formed by oxidizing the second semiconductor layer, and the gate electrode is in contact with the second semiconductor layer through the oxide film, and the gate Leakage current can be further reduced, and parasitic capacitance can be further reduced as compared with the case where the oxide film is in direct contact with the second semiconductor layer, so that it is possible to realize a field effect transistor with more excellent high frequency characteristics. .

  In the field effect transistor manufacturing method of the present invention, in the oxidation step, the thickness of the oxide layer on the side wall of the second semiconductor layer is larger than the thickness of the oxide layer above the second semiconductor layer. It is preferable to form. According to this preferred configuration, by forming the oxide film thicker, the parasitic capacitance around the gate electrode can be reduced, and a field effect transistor with better high frequency characteristics can be realized.

  The method of manufacturing a field effect transistor according to the present invention further includes a step of etching the first semiconductor layer after the step of forming the dielectric film mask layer to form two step portions having the dielectric film mask layer therebetween. And the step of forming the step in such a manner that the dielectric film mask layer is formed on the upper portion of the step between the source electrode and the drain electrode after the step of forming the two step portions. It is preferable to form the second semiconductor layer later on the first semiconductor layer and the dielectric mask layer. According to this preferred configuration, the step can be formed across the heterojunction two-dimensional electron gas, and the current can flow without going through the heterobarrier. Can be realized.

  In the method of manufacturing a field effect transistor according to the present invention, the first semiconductor layer and the second semiconductor layer may be further formed using metal organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor deposition. preferable. According to this preferred configuration, the first and second semiconductor layers can be made excellent in crystallinity and uniformity, the carrier mobility of the semiconductor layer is improved, the series resistance is lower, and the mutual conductance is reduced. A large high-performance field effect transistor can be realized.

  In the method for manufacturing a field effect transistor according to the present invention, it is preferable that the first semiconductor layer and the second semiconductor layer are made of a group III nitride semiconductor. According to this preferred configuration, the III-nitride semiconductor has a large forbidden band and a large dielectric breakdown electric field, so that a high withstand voltage field effect transistor can be realized, the saturation drift speed is large, and the gate length is sufficiently shortened. Can realize a higher performance field effect transistor such as a higher mutual conductance. A high-performance field-effect transistor with low resistance and high mutual conductance can be realized.

  As described above, according to the field effect transistor and the manufacturing method thereof of the present invention, a short gate length of about 100 nm can be realized by, for example, stepper exposure without using electron beam exposure, so reproducibility at lower cost. A field effect transistor having a good short gate length can be realized. Furthermore, by forming the gap on the side of the T-shaped gate electrode, it is possible to reduce the parasitic capacitance around the gate electrode and realize a field effect transistor having excellent high frequency characteristics. It is also possible to realize a field effect transistor with a smaller series resistance by making the regrowth layer portion a lower resistance layer. The T-shaped gate electrode is in contact with the side wall of the second semiconductor layer through the oxide film, and the entire device surface other than the electrode is covered with the oxide film. It is also possible to realize a field effect transistor with a small current.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of a field effect transistor according to a first embodiment of the present invention. In the figure, 101 is a sapphire substrate, 102 is an AlN buffer layer, 103 is an undoped GaN layer, 104 is a first n-type AlGaN layer, 105 is a second n-type AlGaN layer, 106 is an AlGaNOx oxide film layer, 107 is A void formed under the regrown layer, 108 is a Ti / Al / Ni / Au source electrode, 109 is a Ti / Al / Ni / Au drain electrode, and 110 is a PdSi gate electrode.

  In the field effect transistor shown in FIG. 1, a T-type gate electrode is formed after an n-type AlGaN layer is selectively regrown on an AlGaN / GaN heterostructure and a side wall of the regrown portion is selectively oxidized. In addition, voids are formed around the lower portion of the T-shaped gate electrode, and parasitic capacitance is reduced. Here, an AlN buffer layer 102 (layer thickness 0.5 μm), an undoped GaN layer 103 (layer thickness 3 μm), and a first n-type AlGaN layer 104 (layer thickness 25 nm) are formed in this order on a sapphire substrate 101, and further a PdSi gate. A second n-type AlGaN layer 105 (with a layer thickness of 25 nm) is formed on the side of the T-shaped lower portion of the electrode 110 so as to be regrown, and the first and second n-type AlGaN layers 104, 105 and a part of the undoped GaN layer 103 are selectively etched for element isolation, and the element surface is covered with an AlGaNOx oxide film layer 106. The side wall where the second n-type AlGaN layer 105 and the T-shaped gate electrode are in contact with each other is covered with an oxide film of the second AlGaN layer 105, that is, the AlGaNOx layer 106, and the side under the T-shaped gate electrode is shown in FIG. As shown, a gap 107 is formed. Leakage current through the second n-type AlGaN layer 105 between the gate and the source or drain electrode by forming an oxide film between the T-shaped electrode and the regrown second n-type AlGaN layer 105 For example, there is an effect of improving the breakdown voltage between the source and gate electrodes. Further, the gap reduces the parasitic capacitance between the gate and the source, improves the high frequency characteristics, and improves the maximum oscillation frequency (fmax), for example. Further, the surface portions other than the source electrode 108, the drain electrode 109, and the gate electrode 110 are all covered with the AlGaNOx oxide film layer 106, and the leak current between elements is greatly reduced.

The source electrode 108 and the drain electrode 109 are formed of Ti / Al / Ni / Au on the first n-type AlGaN layer 104 and on the side of the regrown second n-type AlGaN layer 105, respectively. Under the source electrode 108 and the drain electrode 109, Si is selectively heavily doped in the surface layer, and the ohmic contact resistance is reduced to, for example, about 2 × 10 ⁻⁶ Ωcm ² . The Al composition of the AlGaN layer is about 25%, but in order to increase the sheet carrier concentration in the two-dimensional electron gas at the AlGaN / GaN hetero interface, the Al composition should be about 40% or more. . Further, by making the Al composition of the second AlGaN layer 105 larger than that of the first AlGaN layer 104 in the first AlGaN layer 104 and the second AlGaN layer 105, the first AlGaN layer 104 In addition, the second AlGaN layer 105 does not generate an electron barrier from the source electrode 108 or the drain electrode 109 side to the channel side, and as a result, the source resistance of the field effect transistor can be reduced.

In order to further reduce the source resistance and the ohmic contact resistance of the source electrode 108 and the drain electrode 109, the second AlGaN layer 105 is preferably doped with high-concentration Si of, for example, 1 × 10 ¹⁹ cm ⁻³ or more as an impurity. . At the time of regrowth, it is desirable that the linearity of the epitaxial growth side be good, so the direction of the gate finger is preferably the <11-20> direction of the GaN layer. Since the sapphire substrate 101 and the GaN crystal grown thereon are rotated by 30 ° in the (0001) plane, it is desirable that gate fingers are formed in the <1-100> direction of the sapphire substrate 101. The element isolation is performed by combining step formation and selective oxidation. However, for example, the resistance may be increased by ion implantation of B or the like. In order to further reduce the parasitic capacitance, the height of the gap is preferably high.

  Therefore, in the present embodiment, in the n-type AlGaN / undoped GaN heterojunction field effect transistor, the T-type gate electrode is formed so as to be sandwiched between the n-type AlGaN regrowth layer and the AlGaNOx oxide film layer, and below the gate electrode. A gap is formed on the side, short gate length, low gate resistance, reduced parasitic capacitance around the gate electrode, excellent high frequency characteristics, for example, high maximum oscillation frequency, low noise figure A field effect transistor can be realized. In addition, the structure that supports the side of the T-gate with an n-type AlGaN regrowth layer covered with an oxide film realizes a field-effect transistor that does not cause the problem of T-shaped gate electrode collapse, which is a problem during mounting. It becomes possible.

The field effect transistor shown in FIG. 1 is manufactured by, for example, the manufacturing method shown in FIG. FIG. 2 is a configuration diagram showing a method for manufacturing the field effect transistor according to the first embodiment of the present invention. In the figure, 201 is a sapphire substrate, 202 is an AlN buffer layer, 203 is an undoped GaN layer, 204 is a first n-type AlGaN layer, 205 is a SiO ₂ mask, 206 is a second n-type AlGaN layer, and 207 is Si A mask, 208 is an AlGaNOx oxide film layer, 209 is a Ti / Al / Ni / Au source electrode, 210 is a Ti / Al / Ni / Au drain electrode, and 211 is a PdSi gate electrode.

First, an AlN buffer layer 202, an undoped GaN layer 203, and a first n-type AlGaN layer 204 are formed in this order on the (0001) surface of the sapphire substrate 201 by metal organic chemical vapor deposition (MOCVD). Form (FIG. 2A). In the above AlGaN / GaN heterostructure, charges are generated at the interface due to spontaneous polarization and piezopolarization on the (0001) plane, so even when AlGaN is undoped, it has a sheet carrier concentration of 1 × 10 ¹³ cm ⁻² A two-dimensional electron gas is formed. Furthermore, in the present embodiment, the sheet carrier concentration is increased by making the AlGaN layer Si-doped n-type. It may be configured to reduce the leakage current when the vicinity of the interface is undoped to prevent Si diffusion to the interface and improve carrier mobility, or the vicinity of the surface is undoped and the Schottky electrode is formed in contact with the AlGaN layer. . Specifically, an AlGaN layer having a carrier concentration of about 4 × 10 ¹⁸ cm ⁻³ is formed.

2B, the first n-type AlGaN layer 204 and the undoped GaN layer 203 in a portion other than the transistor region are formed by dry etching such as ICP (Inductive-Coupled Plasma) etching. After selectively removing the portion, for example, a 200 nm SiO ₂ mask 205 is formed by a vapor deposition method (CVD: Chemical Vapor Deposition) using SiH ₄ and O ₂ . Subsequently, the SiO ₂ mask 205 is patterned using, for example, reactive ion etching (RIE) so as to have stripe-shaped openings only in the device regions between the source and gate and between the drain and gate. Using this SiO ₂ mask 205 as a mask, for example, a second n-type AlGaN layer 206 of 50 nm is selectively grown by MOCVD. The carrier concentration in this regrowth layer is set to a high concentration of 1 × 10 ¹⁹ cm ⁻³ , for example. Here, the second n-type AlGaN layer 206 to be regrown is formed so as to grow laterally on the SiO ₂ mask, leaving a slight stripe-shaped opening as shown in FIG. Stop growing. Specifically, the SiO ₂ mask width of the portion where the gate electrode is to be formed is 1 μm, and after the re-growth of the second n-type AlGaN layer 206, the layer regrown from the source side and the layer regrown from the drain side The regrowth is stopped at a portion having a stripe-shaped opening of 200 nm (FIG. 2D).

Subsequently, the SiO ₂ mask 205 on the surface portion of the second n-type AlGaN layer 206 forming the source and drain electrodes is removed, and an Si mask 207 is formed on this portion by, for example, electron beam evaporation and a lift-off method. After the Si mask 207 is formed, the SiO ₂ mask 205 formed so as to include an element isolation step on the side of the Si mask 207 is removed with, for example, an HF solution. The epitaxial growth layer including the regrowth portion on which the SiO ₂ and Si masks are formed is heat-treated in, for example, an O ₂ atmosphere at 1000 ° C. for 4 hours to selectively oxidize the epitaxial growth layer to form an AlGaNOx layer 208 (FIG. 2 ( e)). By this oxidation process, Si diffuses from the Si mask to the second n-type AlGaN layer side, and the Si concentration on the AlGaN surface increases, so that the ohmic contact resistance of the source / drain electrodes is greatly reduced. In the oxidation step, since the oxidation rate on the (0001) plane is smaller than that on the (1-100) plane or the (11-20) plane perpendicular to the (0001) plane, the second n grown selectively. In the side wall portion of the AlGaN layer, the oxide film thickness is oxidized, for example, about 5 times thicker than that on the (0001) plane. As a result, the opening of the regrown portion of the second n-type AlGaN layer described above can be reduced to about 100 nm from 200 nm.

Subsequently, the Si mask 207 and the SiO ₂ mask 205 are wet-etched with, for example, a hydrofluoric acid solution (FIG. 2F). Here, the fluoric nitric acid does not etch the first n-type AlGaN layer 204, the second n-type AlGaN layer 206, and the AlGaNOx layer 208, so that the SiO ₂ mask 205 and the Si mask 207 can be selectively removed. Striped openings of the second n-type AlGaN layer 206 formed on the portion where the Si mask 207 has been formed as a source electrode 209 and a drain electrode 210 using, for example, Ti / Al / Ni / Au and subsequently oxidized on the surface. As shown in FIG. 2G, a T-shaped PdSi gate electrode 211 is formed. Since the T-shaped gate electrode is formed through a ridge formed by a regrowth layer by removing the SiO ₂ mask 205, the T-shaped gate electrode 211 has a side portion below the T-shaped gate electrode 211 shown in FIG. As shown in FIG. The surface of the epitaxial growth layer other than the source electrode 209, the drain electrode 210, and the gate electrode 211 is all covered with the AlGaNOx layer 208.

As described above, according to the manufacturing method of the present embodiment, for example, even when the size of the SiO ₂ mask 205 at the time of regrowth formed at the position where the gate electrode is formed is 1 μm or more, the regrowth rate and By controlling the time, the opening can be reduced to, for example, about 200 nm, and the size of the opening is reduced to about 100 nm after the oxidation step. Such a shortening of the gate length can be performed by an optical stepper rather than electron beam lithography, so that a GaN field effect transistor having a T-shaped short gate can be manufactured at a lower cost. In addition, in the T-shaped gate electrode by the manufacturing method shown in the present embodiment, a gap is formed in the side portion below the gate electrode, and the T-shaped gate electrode has a short gate length, a small parasitic capacitance, and excellent high frequency characteristics. Can be formed. Further, as described above, the entire surface of the element other than the electrodes is formed so as to be covered with the AlGaNOx layer 208, so that it is possible to realize a field effect transistor with improved element isolation characteristics and a small leakage current.

(Second Embodiment)
FIG. 3 is a cross-sectional view of a field effect transistor according to the second embodiment of the present invention. In this figure, 301 is a sapphire substrate, 302 is an AlN buffer layer, 303 is a SiO ₂ mask, 304 is an undoped GaN layer, 305 is an n-type AlGaN layer, 306 is an n-type GaN layer, 307 is an AlGaNOx oxide film layer, and 308 is Ti / Al / Ni / Au source electrode, 309 is a Ti / Al / Ni / Au drain electrode, 310 is a PdSi gate electrode, and 311 is a SiN film.

In the field effect transistor shown in FIG. 3, an n-type GaN layer is regrown on an AlGaN / GaN heterostructure in which a fine step is formed between the source and drain electrodes, and the sidewall of the regrown portion is selected. After the oxidation, a nitride semiconductor in which a T-type gate electrode is formed in an opening formed by removing a part of the SiN mask is used. Here, an SiO ₂ mask 303 is formed on the sapphire substrate 301 in a stripe shape, for example, parallel to the gate electrode, and an undoped GaN layer 304 (layer thickness 3 μm) is regrown thereon, for example, to achieve a dislocation density of 1 × 10 6. was reduced to approximately ⁶ cm ^-2, n-type AlGaN layer 305 is formed thereon (thickness 25 nm) are formed in this order, a step is formed on a part of the AlGaN / GaN structure, for example, approximately 1μm wide, the A striped SiN film 311 having an opening with a width of, for example, 100 nm is formed on the step, and the n-type GaN layer 306 is regrown so as to cover the SiN film 311, and the side wall of the regrown n-type GaN layer 306 is formed. The T-shaped PdSi gate electrode 310 is formed so as to be sandwiched between the oxide layer, that is, the AlGaNOx oxide film layer 307 and the SiN film 311.

In this embodiment, unlike the first embodiment, an AlGaN / GaN structure is selectively etched and in contact with its side surface, for example, a low resistance n-type doped with Si at a high concentration of about 1 × 10 ¹⁹ cm ^−3. Unlike the first embodiment, the GaN layer 306 is formed, and the current does not flow beyond the AlGaN / GaN heterojunction portion, so that the series resistance is further reduced. In the first embodiment, the side of the lower part of the T-shaped gate electrode, which was a gap in the first embodiment, is a SiN film 311, and the gate side is passivated by the SiN film 311. There is no so-called current collapse phenomenon in which the drain current decreases after increasing the drain voltage. Here, SiON, Al ₂ O ₃ , TiO ₂ , Ta ₂ O _5, or the like may be formed instead of SiN as long as the current collapse is effectively suppressed. In the present embodiment, it is possible to realize a field effect transistor suitable for high power operation in addition to high performance by shortening the gate length.

  Similarly to the first embodiment, the leakage current through the n-type GaN layer 306 between the gate electrode 310 and the source electrode 308 or the drain electrode 309 is caused by the AlGaNOx oxide film layer 307 formed on the side of the gate electrode 310. For example, there is an effect of improving the breakdown voltage between the source and gate electrodes. Further, since the oxidation of the side wall is larger than the oxidation rate in the (0001) plane direction, the dimension of the bottom of the T-shaped gate during the side wall oxidation process, that is, the so-called gate length is the size of the opening of the n-type GaN layer 306 during regrowth. Can be even smaller. Even when the dimension of the step is about 1 μm, an opening of about 200 nm can be formed after re-growth, and an opening of about 100 nm can be formed by selective oxidation, and the T-shaped gate electrode 310 is formed through this opening. Therefore, it is possible to realize a photolithography process for forming a short gate length of about 100 nm by stepper exposure without using, for example, electron beam (EB) drawing, greatly increasing the time required for the photolithography process. Thus, a field effect transistor having a short gate length can be manufactured at low cost.

Further, all surface portions other than the source, drain and gate electrodes are covered with the AlGaNOx oxide film layer 307, and the leak current between elements is greatly reduced. The source electrode 308 and the drain electrode 309 are made of Ti / Al / Ni / Au and are formed on the openings of the AlGaNOx oxide film layer 307 selectively formed on the n-type GaN layer 306, respectively. Under the source electrode 308 and the drain electrode 309, Si is selectively heavily doped in the surface layer, and the ohmic contact resistance is reduced to, for example, about 2 × 10 ⁻⁶ Ωcm ² . The direction of the gate finger is the <11-20> direction of the undoped GaN layer 304, and it is desirable that the linearity of the regrowth surface is further improved. As described above, compared to the first embodiment, current can flow through the two-dimensional electron gas channel without passing through the AlGaN / GaN heterobarrier, and the ionization energy of Si is smaller in GaN than in AlGaN. Since the carrier concentration can be increased and the ohmic contact resistance of the source and drain electrodes can be made smaller on GaN than on AlGaN, a field effect transistor with smaller series resistance can be realized.

  Therefore, in the present embodiment, in the n-type AlGaN / undoped GaN heterojunction field effect transistor, the T-type gate electrode is sandwiched between the n-type GaN layer 306 and the AlGaNOx oxide film layer 307, and the gate electrode is the oxide film layer and It is formed in contact with the SiN film 311. By utilizing the fact that the oxide film grows in the lateral direction during oxidation, the gate opening size can be made smaller than the gate opening size during regrowth, and the gate length can be shortened. Can be realized by a low-cost technique such as stepper exposure. The side portion of the T-shaped gate electrode 310 is covered with the SiN film 311, and the current collapse phenomenon is suppressed as compared with the case of the first embodiment, and a higher output operation is possible.

  Furthermore, the structure is such that a current flows through the high-concentration n-type GaN layer 306 and not through the heterointerface, and the n-type GaN has a lower resistivity than AlGaN and a smaller contact resistance, and therefore has a lower series resistance. A field effect transistor can be realized. Further, the entire element surface other than the electrodes is formed to be covered with the AlGaNOx oxide film layer 307, and the element isolation characteristics are also improved.

The field effect transistor shown in FIG. 3 is manufactured by, for example, the manufacturing method shown in FIG. FIG. 4 is a configuration diagram showing a method for manufacturing a field effect transistor according to the second embodiment of the present invention. In the figure, 401 is a sapphire substrate, 402 is an AlN buffer layer, 403 is an SiO ₂ mask, 404 is an undoped GaN layer, 405 is an n-type AlGaN layer, 406 is an SiN film, 407 is an n-type GaN layer, and 408 is an Si mask. , 409 are AlGaNOx oxide film layers, 410 is a Ti / Al / Ni / Au source electrode, 411 is a Ti / Al / Ni / Au drain electrode, and 412 is a PdSi gate electrode. The point that the AlGaN layer in the region where the source and drain electrodes are formed is removed and the n-type GaN is regrown before the regrowth is different from the embodiment of FIG.

First, an AlN buffer layer 402 having a thickness of 1 μm is formed on the (0001) surface of the sapphire substrate 401 by MOCVD, and an SiO ₂ mask 403 (layer thickness 100 nm) is further formed by CVD. This SiO ₂ mask 403 is patterned into a stripe shape with an opening of 10 μm width and 2 μm, for example (FIG. 4A), and an undoped GaN layer 404 (layer thickness 3 μm) is formed thereon by MOCVD, and n-type AlGaN A layer 405 (layer thickness: 25 nm) is formed in this order. Further, a SiN film 406 (layer thickness 300 nm) is formed on the n-type AlGaN layer 405 by, for example, plasma CVD (FIG. 4B). For the epitaxially grown layer covered with this SiN film 406, as shown in FIG. 4C, the SiN film 406, the n-type AlGaN layer 405, and the undoped GaN other than the transistor region between the source and drain electrodes, for example, by dry etching, as shown in FIG. After selectively removing a part of the layer 404, for example, a 50 nm n-type GaN layer 407 is selectively grown by MOCVD using the SiN film 406 as a mask. The regrowth stops when the opening width on the SiN film 406 becomes 200 nm, for example. The carrier concentration in this regrowth layer is set to a high concentration of, for example, 1 × 10 ¹⁹ cm ⁻³ (FIG. 4D).

Subsequently, the n-type GaN layer 407 and the undoped GaN layer 404 in the element isolation region are partially removed by dry etching, for example. Further, a Si mask 408 is formed on the surface portion of the n-type GaN layer 407 where the source and drain electrodes are to be formed by, for example, electron beam evaporation and a lift-off method (FIG. 4E). The n-type GaN layer 407 on which the SiN film 406 and the Si mask 408 are formed is heat-treated in an O ₂ atmosphere at 1000 ° C. for 4 hours, for example, so that the n-type GaN layer 407 is selectively oxidized to form an AlGaNOx layer 409. (FIG. 4 (f)). This oxidation process diffuses Si from the Si mask 408 to the n-type GaN layer 407 side and increases the Si concentration on the surface of the n-type GaN layer 407, so that the ohmic contact resistance of the source / drain electrodes is greatly reduced.

In the first embodiment, was to form a source and a drain electrode on the AlGaN, since in this embodiment to form the electrode on the n-type GaN layer 407, it can be further reduced ohmic contact resistance 5 × 10 ^- A contact resistance of ⁶ Ωcm ² or less can be realized. Further, the oxide film thickness is oxidized about 5 times thicker than the (0001) plane, for example, on the side wall portion of the selectively grown n-type GaN layer 407. For this reason, the width of the opening of the regrowth layer is 200 nm after the regrowth but is reduced to 100 nm.

  Subsequently, the Si mask 408 is wet etched with, for example, a hydrofluoric acid solution. Here, the etching solution is prepared so that the SiN film 406 is not etched and only the Si mask 408 is etched. Alternatively, only the Si mask 408 may be removed by dry etching. A source electrode 410 and a drain electrode 411 are formed of Ti / Al / Ni / Au, for example, on the n-type portion where the Si mask 408 has been formed (FIG. 4G).

Further, prior to the step of forming the T-shaped gate electrode 412, the SiN film 406 in the opening of the n-type GaN layer 407 covered with the AlGaNOx layer 409 is removed by RIE, and then the T-shaped gate made of PdSi. An electrode 412 is formed (FIG. 4H). For example, when RIE is performed using a mixed gas of CF ₄ and O ₂ , AlGaNOx is not removed, and only SiN can be etched.

  This manufacturing method makes it possible to produce a GaN-based field effect transistor having a T-shaped short gate with good high-frequency characteristics at a lower cost, as in the first embodiment. Since the side portions are covered with the SiN film, the current collapse phenomenon does not occur and high power operation is possible. Further, as described above, it is possible to realize a field effect transistor having a small series resistance and a small leakage current.

The sapphire substrate used in the first and second embodiments may have any plane orientation, for example, a plane orientation with an off-angle from a representative plane such as the (0001) plane. In particular, it is advantageous in that a transistor exhibiting normally-off characteristics can be easily formed on nonpolar surfaces such as the (11-20) plane and the (1-100) plane without being influenced by polarization. The substrate may be an GaN or SiC or ZnO or Si or GaAs or GaP or InP or LiGaO ₂ or LiAlO ₂ or mixed crystal thereof. The buffer layer is not limited to the AlN layer, and may be GaN or a nitride semiconductor layer having any composition ratio as long as a good GaN crystal can be formed on the buffer layer. The epitaxial growth layer of the field effect transistor shown here may include any composition ratio or any multilayer structure as long as the desired transistor characteristics can be realized, and the crystal growth method is not MOCVD, for example, molecular beam epitaxy (Molecular Beam Epitaxy). Epitaxy (MBE) or hydride vapor phase epitaxy (HVPE) may be included. The epitaxial growth layer of the field effect transistor may contain a group V element such as As or P or a group III element such as B as a constituent element.

  The field effect transistor according to the present invention is useful as a high-frequency transistor used in a mobile phone transmission / reception circuit, a millimeter wave radar, or the like.

Sectional drawing which shows the field effect transistor in the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the field effect transistor in the 1st Embodiment of this invention Sectional drawing which shows the field effect transistor in the 2nd Embodiment of this invention Sectional drawing which shows the manufacturing method of the field effect transistor in the 2nd Embodiment of this invention Sectional view of a conventional field effect transistor

Explanation of symbols

101 Sapphire substrate
102 AlN buffer layer
103 Undoped GaN layer
104 First n-type AlGaN layer
105 Second n-type AlGaN layer
106 AlGaNOx oxide layer
107 gap
108 Source electrode
109 Drain electrode
110 Gate electrode
201 Sapphire substrate
202 AlN buffer layer
203 Undoped GaN layer
204 First n-type AlGaN layer
205 SiO ₂ mask
206 Second n-type AlGaN layer
207 Si mask
208 AlGaNOx oxide layer
209 Source electrode
210 Drain electrode
211 Gate electrode
301 Sapphire substrate
302 AlN buffer layer
303 SiO ₂ mask
304 Undoped GaN layer
305 n-type AlGaN layer
306 n-type GaN layer
307 AlGaNOx oxide layer
308 Source electrode
309 Drain electrode
310 Gate electrode
311 SiN film
401 Sapphire substrate
402 AlN buffer layer
403 SiO ₂ mask
404 Undoped GaN layer
405 n-type AlGaN layer
406 SiN film
407 n-type GaN layer
408 Si mask
409 AlGaNOx oxide layer
410 Source electrode
411 Drain electrode
412 Gate electrode

Claims (37)

A first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; an opening formed in the second semiconductor layer; a gate electrode provided in the opening; A field effect transistor comprising a gap formed between the gate electrode and the second semiconductor layer. 2. The field effect transistor according to claim 1, further comprising an insulating film formed on the second semiconductor layer and in contact with the gate electrode. 3. The field effect transistor according to claim 2, wherein the insulating film is an oxide film of the second semiconductor layer. A first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; an opening formed in the second semiconductor layer; a gate electrode provided in the opening; A field effect transistor comprising a dielectric layer formed between the gate electrode and the second semiconductor layer. A source electrode and a drain electrode formed on the first semiconductor layer and sandwiching the gate electrode; and the first electrode between the source electrode and the gate electrode and between the drain electrode and the gate electrode. 5. The field effect transistor according to claim 2, further comprising an insulating film covering a surface of the semiconductor layer. 6. The field effect transistor according to claim 5, wherein the film thickness of the insulating film is larger at the side surface than at the upper surface of the second semiconductor layer. 7. The field effect transistor according to claim 1, wherein the composition ratio of constituent elements is different between the first semiconductor layer and the second semiconductor layer. 8. The field effect transistor according to any one of claims 1 to 7, wherein the first semiconductor layer and the second semiconductor layer have different carrier concentrations. A first semiconductor layer; a second semiconductor layer formed in a predetermined region on the first semiconductor layer and forming a heterojunction with the first semiconductor layer; and the first and second semiconductors A third semiconductor layer formed on the layer; an opening formed in the third semiconductor layer; and a gate electrode provided in the opening and in contact with the second semiconductor layer. A characteristic field effect transistor. The field effect transistor according to claim 9, wherein a two-dimensional electron gas is formed at an interface of the heterojunction. 10. The field effect transistor according to claim 9, further comprising a gap formed between the second semiconductor layer and the third semiconductor layer. The electric field according to claim 9, further comprising a dielectric layer formed between the second semiconductor layer and the third semiconductor layer, wherein the opening is provided in the dielectric layer. Effect transistor. Two step portions provided in the first and third semiconductor layers so as to interpose the gate electrode, and a source electrode formed on the third semiconductor layer and sandwiching the gate electrode 10. The field effect transistor according to claim 9, further comprising a drain electrode. 14. The field effect transistor according to claim 13, wherein the source electrode and the drain electrode are disposed with the second semiconductor layer interposed therebetween. 15. The carrier concentration of the third semiconductor layer is higher than a carrier concentration of a portion of the first semiconductor layer that is in contact with the gate electrode. Field effect transistor. 16. The field effect transistor according to claim 9, wherein the carrier concentration of the third semiconductor layer is 1 × 10 ¹⁹ cm ⁻³ or more. 10. The field effect transistor according to claim 9, wherein the third semiconductor layer has a region in which impurities are diffused and added at a high concentration below a portion in contact with the source electrode and the drain electrode. 18. The field effect transistor according to claim 1, wherein a crystal defect density of the first semiconductor layer below the gate electrode is 10 ⁷ cm ² or less. 19. The field effect transistor according to claim 18, wherein a mask layer is formed below the gate electrode. 20. The field effect transistor according to claim 1, wherein the semiconductor layer is made of a group III nitride semiconductor. 13. The field effect transistor according to claim 4, wherein the dielectric layer is made of SiN. 21. The field effect transistor according to claim 20, wherein the semiconductor layer is formed on a (0001) plane, and the gate electrode is formed in a straight line in the <11-20> direction. 20. The field effect transistor according to claim 1, wherein the second semiconductor layer is made of AlGaN. The field effect transistor according to claim 23, wherein the first semiconductor layer is made of AlGaN, and the Al composition of the AlGaN layer of the second semiconductor layer is larger than the Al composition of the first semiconductor layer. 20. The method according to claim 9, wherein the second semiconductor layer is made of Al _x Ga _1-x N (0 <x ≦ 1), and the third semiconductor layer is made of GaN. The field effect transistor as described. 26. The field effect transistor according to claim 20, 23, or 25, wherein Si is added to the second semiconductor layer. The semiconductor layer is formed on a substrate, and the substrate is made of any of sapphire, SiC, GaN, AlN, MgO, LiGaO ₂ , LiAlO ₂ , or a mixed crystal of LiGaO ₂ and LiAlO ₂ . The field effect transistor according to claim 20. The mask layer is a field-effect transistor of claim 19, characterized in that it comprises a SiO ₂ layer or SiN layer. 29. The field effect transistor according to claim 1, wherein a cross-sectional shape of the gate electrode is T-shaped. Forming a first semiconductor layer on the substrate; selectively forming a dielectric mask layer on the first semiconductor layer; and on the first semiconductor layer and the dielectric mask layer. Forming a second semiconductor layer so that an opening width on the dielectric mask layer is smaller than a width of the dielectric mask layer, and removing all or a part of the dielectric mask layer. Forming a gate electrode in contact with the surface of the first semiconductor layer exposed inside the opening of the second semiconductor layer by removing the dielectric mask layer, and the second semiconductor And a step of forming a source electrode and a drain electrode on the layer. 31. The field effect transistor according to claim 30, wherein a gap is formed between the gate electrode and the first semiconductor layer and the second semiconductor layer by removing the dielectric mask layer. Method. Of the dielectric film mask layer, only a portion exposed to the surface at the opening of the second semiconductor layer is selectively removed, and the dielectric film mask layer is located on the side of the gate electrode. 31. The method of manufacturing a field effect transistor according to claim 30, wherein the field effect transistor is formed so as to be in contact with an electrode. 33. The method of manufacturing a field effect transistor according to claim 30, 31 or 32, further comprising a step of oxidizing the second semiconductor layer prior to the step of removing the dielectric film mask layer. 34. The film forming method according to claim 33, wherein in the oxidation step, the oxide layer on the side wall of the second semiconductor layer is formed thicker than the oxide layer on the second semiconductor layer. A method of manufacturing a field effect transistor. Etching the first semiconductor layer after the step of forming the dielectric film mask layer to form two stepped portions having the dielectric film mask layer therebetween; 31. The method of manufacturing a field effect transistor according to claim 30, wherein the second semiconductor layer is formed on the semiconductor layer and the dielectric film mask layer. The first semiconductor layer and the second semiconductor layer are formed by metal organic vapor phase epitaxy, molecular beam epitaxy, or hydride vapor phase epitaxy. The manufacturing method of the field effect transistor as described in one. 37. The method of manufacturing a field effect transistor according to claim 30, wherein the first semiconductor layer and the second semiconductor layer are made of a group III nitride semiconductor.

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