JP2006129139A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate an internal clock by using an on-chip PLL circuit even though an external clock is stopped. <P>SOLUTION: A PLL circuit (2) has a phase comparator circuit (10) for comparing the phase of a reference clock signal with the phase of a feedback clock signal, a charge pump circuit (11) for generating an oscillation control signal that corresponds to the frequency of the reference clock signal and a phase comparison result of the phase comparator circuit, a bias circuit (15) for generating a bias signal to be added to the oscillation control signal, and an oscillation circuit (16) for forming a clock signal of a frequency corresponding to the oscillation control signal and the bias signal. The clock signal of the frequency that corresponds to a bias signal generated by the bias circuit of the PLL circuit can be formed even though the external clock is stopped. Since a necessary frequency can be determined by the bias signal, it is difficult to cause a large variation in the frequency of a clock signal generated when the clock supplied from the outside is stopped. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL circuit and a semiconductor integrated circuit, for example, a technique effective when applied to a clock pulse generator of a microcomputer.

  The microcomputer is normally operated in synchronization with a source oscillation clock by an external oscillator or a system clock supplied from the outside. However, if the clock supply is undesirably stopped due to poor connection or destruction of the oscillator, disconnection of the system clock wiring, or the like, it cannot be guaranteed what the microcomputer will do. In order to avoid this, an oscillation circuit that self-oscillates when an abnormality in a clock supplied from the outside is detected can be provided. For example, when a PLL circuit is provided in a clock pulse generator that receives a source oscillation clock or a system clock, a ring oscillator can be provided as a self-oscillation circuit. The PLL circuit is described in Patent Document 1, for example, and the ring oscillator is described in Patent Document 2, for example.

JP 2002-141798 A JP 2000-331489 A

  The present inventor has examined the provision of a transmission circuit that self-oscillates when an abnormality of an externally supplied clock is detected. According to this, when an oscillation circuit such as a ring oscillator is provided separately from the PLL circuit or the like, the circuit scale is increased correspondingly, and it is even more so that the oscillation frequency can be controlled. In addition, in the case of a circuit configuration using a CR time constant for the delay stage of the ring oscillator, the oscillation frequency tends to vary.

  An object of the present invention is to provide a semiconductor integrated circuit capable of generating an internal clock using an on-chip PLL circuit even when an externally supplied clock is stopped.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  The semiconductor integrated circuit includes a PLL circuit, a synchronization circuit that operates in response to a clock signal output from the PLL circuit, and a stationary signal instead of the reference clock signal when the stop of the reference clock signal supplied to the PLL circuit is detected. A detection circuit that supplies a PLL circuit, and the PLL circuit compares a phase of a reference clock signal with a phase of a feedback clock signal, and a frequency of the reference clock signal and the phase comparison circuit A charge pump circuit that generates an oscillation control signal according to the phase comparison result at, a bias circuit that generates a bias signal to be added to the oscillation control signal, and a clock signal having a frequency according to the oscillation control signal and the bias signal. And an oscillation circuit to be formed. According to the above-described means, a clock signal having a frequency corresponding to the bias signal generated by the bias circuit of the PLL circuit can be formed even when the clock supplied from the outside is stopped. Since the necessary frequency can be determined by the voltage of the bias signal or the like, it is difficult to cause a large variation in the frequency of the generated clock signal when the externally supplied clock is stopped.

  As a specific form of the present invention, the semiconductor integrated circuit may include a central processing unit that executes instructions as the synchronization circuit. The bias circuit may be configured to variably set the magnitude of the bias signal based on a plurality of bits of control data. At this time, it has a register for storing the control data, and the register may be made accessible by an instruction of the central processing unit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, even when the externally supplied clock is stopped, the internal clock can be generated using the on-chip PLL circuit.

  FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit (LSI) 1 is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. The semiconductor integrated circuit 1 includes a PLL circuit (PLLC) 2, a synchronization circuit (SYNC) 3 that operates in response to the clock signal CLK output from the PLL circuit 2, and a stop of the reference clock signal CLKS supplied to the PLL circuit 2. And a detection circuit (CDR) 5 capable of supplying a level fixing signal 4 (see FIG. 2) as a stationary signal to the PLL circuit 2 instead of the reference clock signal CLKS. Whether or not the level fixing signal 4 is supplied to the PLL circuit 2 instead of the reference clock signal CLKS can be selected by a selection signal 7 according to a set value of the register (REGC) 6. The register 6 is made accessible according to instruction execution of a central processing unit (CPU) 8.

  The PLL circuit 2 includes a phase comparison circuit (CMP) 10 for comparing the phase of the reference clock signal CLKS and the phase of the feedback clock signal CLKR, and the frequency of the reference clock signal CLKS and the phase of the phase comparison circuit 10. A charge pump circuit (CP) 13 that generates an oscillation control signal 12 corresponding to the comparison result 11, a bias circuit (BIAS) 15 that generates a bias signal 14, and a frequency corresponding to the oscillation control signal 12 and the bias signal 14. A voltage controlled oscillator (VCO) 16 serving as an oscillation circuit for generating a clock signal, frequency dividers (DIV) 17, 18, and 19 and selectors (SEL) 20, 21, and 22 are included. The bias circuit 15 can change the magnitude of the bias signal 14 based on the control data 23 of a plurality of bits. A register (REGB) 24 for storing the control data 23 is provided, and the register 24 is made accessible by instruction execution by a central processing unit (CPU) 8.

  The oscillation frequency of the voltage controlled oscillator 16 is 16 times the reference clock signal CLKS. The frequency divider 17 divides the frequency by 2, and the frequency dividers 18 and 19 divide the frequency by 8. The selectors 20, 21, and 22 are used to switch the signal path between the test operation and the actual operation, and the input a side is selected during the test and the input b side is selected during the actual operation.

  FIG. 2 shows an example of the detection circuit (CDR) 5. The detection circuit 5 includes a selector 30 that selects the reference clock signal CLKS or the level fixing signal 4 as an external clock signal. The selector 30 selects the reference clock signal CLKS according to the low level of the select signal 31, and selects the level fixing signal 4 according to the high level. The clock stop detection circuit (CSD) 32 detects the stop of the reference signal CLKS, and outputs a detection signal 33 that is set to a high level in response to the detection of the clock stop. The internal control signal 35 that is activated when the clock stabilization period after the cancellation of the standby state or the cancellation of the reset has elapsed is asserted, and then a high-level detection signal 33 is output from the clock stop detection circuit (CSD) 32 Then, the latch circuit 34 latches the detection signal 33. In this state, the output signal 36 of the latch circuit 34 is set to the high level. When the signal 7 is set to the high level according to the set value of the register 6, the detection result latched in the latch circuit 34 is reflected in the selection signal 31. In short, when the signal 7 is set to the high level according to the set value of the register 6 and the stop of the reference clock signal CLKS is detected, the selector 30 selects the high level fixed signal 4 instead of the reference clock signal CLKS, and the selector 30 The 30 output signals 37 are fixed at a low level.

  FIG. 3 shows an example of the charge pump circuit 13. A series circuit of the p-channel MOS transistors MP2 and MP3 and the n-channel MOS transistors MN5 and MN4 constitutes a charge pump output stage. The common drain of the MOS transistors MP3 and MN5 is used as an output terminal, and a loop filter including a resistor Rf and a capacitor Cf is disposed at the output terminal. An up signal UPB is supplied to the gate of the MOS transistor MP3, and a down signal DN is supplied to the gate of the MOS transistor MN5 to control its conductance. When the phase of the feedback clock signal CLKR is delayed with respect to the reference signal CLKS, both the up signal UPB and the down signal are controlled to a low level, and when they are advanced, both are controlled to a high level. The conductances of the MOS transistors MP2 and MN4 are controlled by reflecting the current flowing in the current source circuit constituted by MN1, MN2, MN3, MP1, MPA, MPA0 to MPA15, and MPB0 to MPB15. Reference numeral 40 denotes a pulse width detection circuit (PWDTC) capable of detecting the pulse width of the reference clock signal CLKS given as the signal 37. The pulse width detection circuit 40 controls the level of the output signal 12 to be lower by increasing the number of transistors in the MOS transistors MPB0 to MPB15 that are turned on as the pulse width of the reference clock signal CLKS is larger. When the reference clock signal CLKS is stopped and the signal 37 is fixed to the low level, all the MOS transistors MPB0 to MPB15 are turned on, the up signal UPB and the down signal DN are set to the high level, and the output signal 12 is The circuit is substantially set to the ground level Vss.

  FIG. 4 illustrates the relationship between the voltage controlled oscillator 16 and the bias circuit 15. The voltage controlled oscillator 16 includes a ring oscillator 50 whose oscillation frequency is variably controlled by conductance control of the current source transistor. In the figure, a three-stage inverting amplifier 51 in series is shown as a part of the ring oscillator 50. The conductance of the current source transistor 52 of each inverting amplifier 51 is controlled by the current flowing through the MOS transistor 53. A current that is the sum of the current 55 generated by the conversion circuit 54 that converts the output voltage 12 of the charge pump circuit 13 into a current and the current 14 supplied from the bias circuit 15 flows through the MOS transistor 53. The value of the current 14 output from the bias circuit 15 can be changed by the value of the control data 23 of a plurality of bits. The constant current source 56 is activated / deactivated by the control signal 7. When the control signal 7 is set to the high level and the detection circuit 5 makes the high level fixed signal 4 selectable, the bias circuit 15 is enabled to output the voltage 14. Even if the oscillation control signal 12 is 0 V, the ring oscillator 50 can self-oscillate (self-running oscillation) if a current flows through the MOS transistor 53 by the signal 14 from the bias circuit 15. Therefore, if the control data for setting the selection signal 7 to the high level is set in the register 6 and the control data for obtaining the frequency necessary for the free-running oscillation is set in the register 24, the reference clock signal CLKS is stopped. In addition, the supply of the clock signal CLK to the synchronization circuit 3 is maintained, and the occurrence of a situation in which the semiconductor integrated circuit 1 cannot be guaranteed to operate can be avoided. In addition, since the frequency control necessary in that case can be specified with a relatively wide range by the control data set for the register 24, it is possible to easily cope with various systems having different operation speeds. As shown in FIG. 5, when the configuration of switching to the operation of the ring oscillator 60 using the capacitive delay with respect to the supply stop of the external clock is adopted, the oscillation frequency greatly varies due to the process variation. There is no problem.

  FIG. 6 shows the timing of the self-oscillation operation when the reference clock signal CLKS is stopped at a fixed low level, and FIG. 7 shows the timing of the self-oscillation operation when the reference clock signal CLKS is stopped at a fixed high level.

  FIG. 8 illustrates a configuration of a microcomputer to which the present invention is applied. The microcomputer (MCU) 71 is formed on one semiconductor substrate such as single crystal silicon by, for example, a CMOS integrated circuit manufacturing technique. The microcomputer 71 includes a central processing unit (CPU) 72, a random access memory (RAM) 73 as a volatile memory used for a work area of the CPU 72, and a CPU bus as a first bus to which the CPU 72 and the RAM 73 are connected. (BUSc) 74, a bus controller (BSC) 75 connected to the CPU bus 74, a peripheral bus (BUSp) 76 as a second bus connected to the bus controller 75, etc. Prepare. The peripheral bus 76 includes a timer (TMR) 77, an analog / digital conversion circuit (A / D) 78, a serial interface controller (SCI) 80, an external data input / output buffer (DBUF) 81, and an external address output buffer (ABUF) 82. A system controller (SYSC) 83 is connected. The CPU 72 controls an instruction fetch, an instruction control unit that decodes the fetched instruction and controls the execution of the instruction, and an execution unit that executes an instruction by performing an address or data operation under the control of the instruction control unit. Have.

  Connected to the CPU bus 74 is a flash memory 84 as an electrically rewritable non-volatile memory that stores information according to a difference in threshold voltage. The flash memory 84 has a storage area (program area) for programs executed by the CPU 72 and a storage area (data area) for data used when the CPU 72 executes programs.

  The microcomputer has an internal voltage generation circuit (IPG) 85 and generates an internal operation power supply from the external power supply voltage VDD. When the external power supply voltage VDD is input to the internal voltage generation circuit (IPG) 85. A power-on detection signal 86 is asserted to the system controller 83. The system controller 83 inputs a mode signal MD, a reset signal / RST, and a standby signal / STB as external signals. The reset signal / RST and standby signal / STB are low enable signals. A clock pulse generator (CPG) 87 receives an oscillation clock from an oscillator or an external system clock and generates an internal clock signal CLK.

  The PLL circuit 2, the detection circuit 5, and the registers 6 and 24 are included in the CPG 87.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the semiconductor integrated circuit is not limited to a microcomputer, and can be applied to various circuits such as other logic LSIs and clock synchronous memories such as a synchronous DRAM. In addition, the circuit configurations such as the charge pump circuit and the voltage controlled oscillator are not limited to the above, and can be changed as appropriate.

It is a block diagram which shows an example of the semiconductor integrated circuit which concerns on this invention. It is a logic circuit diagram showing an example of a detection circuit for detecting a stop of a reference clock signal. It is a circuit diagram which shows an example of a charge pump circuit. It is a circuit diagram which illustrates the relation between a voltage control oscillator and a bias circuit. FIG. 6 is a logic circuit diagram showing, as a comparative example, a configuration in which switching to the operation of a ring oscillator using a capacitive delay with respect to the stop of supply of an external clock 6 is a timing chart of the self-oscillation operation when the reference clock signal CLKS is stopped at a fixed low level. 6 is a timing chart of the self-oscillation operation when the reference clock signal CLKS is stopped at a fixed high level. It is a block diagram which illustrates the composition of the microcomputer to which the present invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 PLL circuit 3 Synchronous circuit 4 Level fixed signal 5 Detection circuit 6 Register 7 Selection signal 8 Central processing unit 10 Phase comparison circuit 11 Phase comparison result 12 Oscillation control signal 13 Charge pump circuit 14 Bias signal 15 Bias circuit 16 Voltage Controlled oscillator

Claims (5)

A PLL circuit, a synchronization circuit that operates in response to a clock signal output from the PLL circuit, and a stationary signal instead of the reference clock signal when a stop of the reference clock signal supplied to the PLL circuit is detected is supplied to the PLL circuit And a detection circuit,
The PLL circuit includes a phase comparison circuit for comparing the phase of the reference clock signal and the phase of the feedback clock signal, and an oscillation control signal corresponding to the frequency of the reference clock signal and the phase comparison result in the phase comparison circuit A semiconductor integrated circuit having a charge pump circuit that generates a bias signal, a bias circuit that generates a bias signal to be added to the oscillation control signal, and an oscillation circuit that forms a clock signal having a frequency corresponding to the oscillation control signal and the bias signal.   2. The semiconductor integrated circuit according to claim 1, further comprising a central processing unit that executes instructions as the synchronization circuit.   2. The semiconductor integrated circuit according to claim 1, wherein the bias circuit is capable of variably setting the magnitude of the bias signal based on a plurality of bits of control data.   4. The semiconductor integrated circuit according to claim 3, further comprising a register for storing the control data, wherein the register is made accessible by an instruction of a central processing unit. A phase comparison circuit for comparing the phase of the reference clock signal and the phase of the feedback clock signal;
A charge pump circuit that generates an oscillation control signal according to the frequency of the reference clock signal and a phase comparison result in the phase comparison circuit;
A bias circuit that generates a bias signal to be added to the oscillation control signal;
A PLL circuit having an oscillation control signal and an oscillation circuit that forms a clock signal having a frequency corresponding to the bias signal.

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