JP2006294841A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a manufacturing method for a semiconductor device inhibiting a leakage current at a gate edge. <P>SOLUTION: The manufacturing method for the semiconductor device has: a process in which a tunnel film, a floating gate, an interlayer insulating film, and a control gate are formed successively on a semiconductor substrate; the etching process in which the control gate, the interlayer insulating film, and the floating gate are patterned by an etching and the residual film of the tunnel film is left; and an ion implanting process in which impurity ions are implanted to the semiconductor substrate through the residual film of the tunnel film. The manufacturing method further has a removing process in which the residual film of the tunnel film is removed after the ion implanting process, and the process in which a protective film is formed on the side wall of the floating gate by a thermal oxidation after the removing process. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a flash memory having a floating gate.

  A conventional flash memory manufacturing method will be described below (see, for example, Patent Document 1). First, an element isolation region is formed, and a gate pattern of a cell transistor is formed. Next, the tunnel film is etched, and impurities are ion-implanted through the remaining film into the source / drain diffusion layer. Then, a protective film is formed on the side wall of the floating gate by thermal oxidation (side wall oxidation). Further, the impurities implanted into the source / drain diffusion layers are activated by heat treatment during thermal oxidation.

JP-A-9-55442

  By ion implantation into the source / drain, impurities are also implanted into the remaining film of the tunnel film, and trap levels are generated. This trap level is not sufficiently recovered even by heat treatment during thermal oxidation. In the conventional manufacturing method, the tunnel film remaining film is left as it is, so that electrons accumulated in the floating gate leak from the gate edge portion into the semiconductor substrate through the trap level, and the accumulated data is easily volatilized. There was a problem. In particular, it has become difficult to increase the heat treatment amount / oxidation amount of thermal oxidation with miniaturization, and the problem of residual traps has become more apparent.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a method of manufacturing a semiconductor device capable of suppressing a leakage current at a gate edge portion.

  The method of manufacturing a semiconductor device according to the present invention includes a step of sequentially forming a tunnel film, a floating gate, an interlayer insulating film, and a control gate on a semiconductor substrate, and patterning the control gate, the interlayer insulating film, and the floating gate by etching. An etching process for leaving a residual film of the tunnel film, an ion implantation process for ion-implanting impurities into the semiconductor substrate through the residual film of the tunnel film, and a removal for removing the residual film of the tunnel film after the ion implantation process And a step of forming a protective film on the side wall of the floating gate by thermal oxidation after the step and the removing step. Other features of the present invention will become apparent below.

  According to the present invention, leakage current at the gate edge portion can be suppressed.

Embodiment 1 FIG.
A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.

  First, an element isolation region is formed by LOCOS (LOCal Oxidation of Silicon) technology, STI (Shallow Trench Isolation) technology, or the like (not shown). Then, as shown in FIG. 1A, a tunnel film 12, a floating gate 13, an interlayer insulating film 14, and a control gate 15 are sequentially formed on a semiconductor substrate 11 made of silicon, and a known dry etching technique is used. These films are patterned to form a laminated electrode structure. At this time, the tunnel film 12 is not completely removed, leaving a remaining film.

  Next, as shown in FIG. 1B, impurities such as arsenic (As), boron (B), and phosphorus (P) are ion-implanted into the semiconductor substrate 11 through the remaining film of the tunnel film 12. Thereafter, as shown in FIG. 1C, the remaining film of the tunnel film 12 into which the impurity has been implanted is removed.

  Next, as shown in FIG. 1 (d), high-crystalline oxidation is performed on the sidewall of the floating gate 13 by thermal oxidation such as FA (Furnace Anneal), RTP (Rapid Themal Prooess) or ISSG (In-Situ Steam Generation). A protective film 16 made of a film is formed. Further, the source / drain regions 17 are formed by activating the impurities implanted into the semiconductor substrate 11 by heat treatment during thermal oxidation.

  As described above, in the method of manufacturing the semiconductor device according to the first embodiment, the tunnel film remaining film is removed after ion implantation, and then thermal oxidation is performed. That is, the thermal oxidation is performed after removing the tunnel film residual film in which the trap level is generated by ion implantation. As a result, leakage current at the gate edge portion through the trap level of the tunnel film remaining film can be suppressed, and a flash memory having good data retention characteristics can be manufactured.

  In particular, when an ISSG process is introduced for thermal oxidation, a high-quality oxide film can be formed by high-temperature and short-time heat treatment, and gate bird's beak growth can be suppressed and controlled with high precision. In the process, high performance and quality can be achieved at the same time.

Embodiment 2. FIG.
In the second embodiment, an anisotropic dry etch process is used in removing the tunnel film residual film of the first embodiment. Thereby, as shown in FIG. 2, side etching does not occur at the interface between the floating gate and the tunnel film and at the interface between the floating gate and the interlayer insulating film. Gate bird's beak growth during thermal oxidation can be suppressed, and a decrease in cell current driving capability due to thick gate bird's beak can be suppressed.

  In addition, the gate bird's beak during thermal oxidation grows depending on the amount of oxidation starting from the side surface of the floating gate and can be adjusted at a level of several nanometers to several tens of nanometers. By increasing the thickness, the amount of leakage current passing through the tunnel film at the gate edge portion can be suppressed, and a flash memory having good data retention characteristics can be manufactured.

  In particular, when the ISSG process is applied to thermal oxidation, since the penetration depth of the gate bird's beak is shallow, the effect of suppressing the decrease in the current driving capability is great.

Embodiment 3 FIG.
In the third embodiment, a wet etch process is used in removing the tunnel film residual film of the first embodiment. As a result, as shown in FIG. 3, side etching occurs at the interface between the floating gate and the tunnel film and at the interface between the floating gate and the interlayer insulating film.

  Therefore, the gate bird's beak at the time of thermal oxidation grows from the semiconductor substrate surface, the floating gate lower surface, the floating gate upper surface, and the control gate lower surface exposed from the side surface of the floating gate. Therefore, the amount of gate bird's beak at the floating gate edge can be greatly increased, so that the amount of leakage current passing through the tunnel film at the gate edge can be suppressed, and a flash memory having good data retention characteristics is manufactured. can do.

  Although the current drive capability near the gate edge is reduced by increasing the thickness of the tunnel film by gate bird's beak, it can be an option when higher reliability is required.

Embodiment 4 FIG.
In the fourth embodiment, a combined process of anisotropic dry etching and wet etching is used in removing the remaining tunnel film of the first embodiment. Thereby, since the amount of gate bird's beak entering from the side surface of the floating gate can be controlled, desired transistor performance can be obtained. That is, it is possible to set the desired operating point by controlling the cell transistor characteristic fluctuations depending on the tunnel film thickness at the gate edge and the gate bird's beak penetration required for high reliability. In particular, when an ISSG process of high temperature and high speed oxidation is applied to thermal oxidation, the gate bird's beak can be controlled with higher accuracy.

Embodiment 5. FIG.
In Embodiment 5, after removing the tunnel film so that no remaining film remains, all or part of the ion implantation is performed, and then thermal oxidation is performed. Other steps are the same as those in the first to fourth embodiments.

  As a result, the impurities implanted into the semiconductor substrate are not removed in the tunnel film residual film removal step and remain at the necessary high concentration, so that a low resistance source / drain diffusion layer can be obtained. it can.

It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 3 of this invention.

Explanation of symbols

11 Semiconductor substrate 12 Tunnel film 13 Floating gate 14 Interlayer insulating film 15 Control gate 16 Protective film 17 Source / drain region

Claims (5)

A step of sequentially forming a tunnel film, a floating gate, an interlayer insulating film, and a control gate on a semiconductor substrate;
An etching step of patterning the control gate, the interlayer insulating film, and the floating gate by etching so that a residual film of the tunnel film remains;
An ion implantation step of ion-implanting impurities into the semiconductor substrate through the remaining film of the tunnel film;
After the ion implantation step, a removal step of removing the remaining film of the tunnel film;
And a step of forming a protective film on the sidewall of the floating gate by thermal oxidation after the removing step.   The method for manufacturing a semiconductor device according to claim 1, wherein anisotropic dry etching is used in the etching step.   The method of manufacturing a semiconductor device according to claim 1, wherein wet etching is used in the etching step.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a composite process of anisotropic dry etching and wet etching is used in the etching step. A step of sequentially forming a tunnel film, a floating gate, an interlayer insulating film, and a control gate on a semiconductor substrate;
An etching step of patterning the control gate, the interlayer insulating film, and the floating gate by etching, and removing the tunnel film so that no residual film remains;
An ion implantation step of ion-implanting impurities into the semiconductor substrate;
And a step of forming a protective film on a side wall of the floating gate by thermal oxidation after the ion implantation step.

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