JP2006202814A - Monitor fet and process for fabricating compound semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a monitor FET in which electrical characteristics can be measured normally even if the film thickness of a gate pad electrode is several tens Å. <P>SOLUTION: Under the gate pad electrode of the monitor FET, an insulation layer is not provided but a second impurity region is provided. Since gate conduction is possible even if a probe runs through the gate pad electrode, characteristics can be measured normally. Furthermore, insulation from other components can be ensured because an insulation layer is arranged around the second impurity region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a HEMT having a Pt buried gate structure in which a Pt layer thickness is reduced and a manufacturing method thereof in order to reduce Vp variation of the HEMT.

  In the wafer process, a product and a monitor are generally formed on the same wafer in the same process, and the characteristics of the product in the intermediate process are managed by measuring the monitor.

  For example, a technique is known in which a TEG (resistance monitor) and a TFT (thin film transistor) are provided on the same substrate, and the TEG is measured to predict the impurity concentration in the source / drain region of the TFT as a product (for example, Patent Documents). 1).

  In addition, there are cases in which the product transistor and the monitor transistor are formed on the same wafer in the same process, and the characteristics of the product transistor are managed by measuring the electrical characteristics of the monitor transistor during the process. .

  A conventional monitor FET will be described with reference to FIG. 12A is a plan view, and FIG. 12B is a cross-sectional view taken along the line ee of FIG. 12A.

  The monitor FET 500 manages the characteristics of the HEMT of the switch MMIC configured by, for example, the HEMT, and is formed on the same wafer as the HEMT in the same process as the manufacturing process of the HEMT.

  In the monitor FET 500, a monitor source electrode 503, a monitor drain electrode 504, and a monitor gate electrode 505 are arranged on an impurity region 501 similar to the source region and drain region of the HEMT. The monitor gate electrode 505 extends on the insulating layer 250 insulated by impurities and is connected to the gate pad electrode 506.

  At the time of measurement, the probe (needle) 10 is brought into contact with the monitor source electrode 503, the monitor drain electrode 504, and the gate pad electrode 506 of the monitor FET 500 through the opening (contact hole CH) of the insulating film 507. By measuring the characteristics of the monitor FET formed in the same process, the characteristics of the HEMT that is an actual product can be grasped.

  An example of a conventional HEMT manufacturing method will be described with reference to FIG.

  A plurality of semiconductor layers including a buffer layer 232, an electron supply layer 233, a spacer layer 234, a channel layer 235, a spacer layer 234, an electron supply layer 233, a barrier layer 236, and a cap layer (n + GaAs layer) 237 on a semi-insulating GaAs substrate 231. Are stacked.

  After a through ion implantation nitride film 2511 is formed on the entire surface of the wafer, an insulating layer is formed by an ion implantation region reaching the buffer layer 232, and an impurity region as an operation region constituting the HEMT is separated. After that, the first source electrode 315 and the drain electrode 316 are formed in contact with the cap layer 237 by the ohmic metal layer 310 (FIG. 13A).

  Next, the barrier layer 236 in the gate electrode formation region is exposed, and the gate metal layer 320 is deposited to form the gate electrode 327. Then, a protective film 2512 is formed on the entire surface. Then, a contact hole CH is formed over the source electrode 315 and the drain electrode 316 in the first layer (FIG. 13B).

Further, the pad metal layer 330 forms the first source electrode 315, the second source electrode 335 in contact with the drain electrode, the drain electrode 336, the wiring pattern, and the electrode pad (FIG. 13C) (for example, patent) Reference 2). The monitor FET is formed by the same process as this HEMT.
JP 2004-214638 A JP-A-6-84956

  In the wafer process of the switch MMIC using HEMT, when the formation process of the gate electrode 327 is finished, the basic structure as an FET is completed. Regarding the HEMT of the switch MMIC to be a product, the characteristics can be measured only after the wiring pattern forming step (FIG. 13C) using the pad metal layer 330. However, since the monitor FET 500 does not require wiring, the characteristic is measured in a process (FIG. 13B) before the wiring pattern forming process, and the data is used for grasping the process level.

  That is, after forming the contact hole CH immediately before the wiring pattern formation process (FIG. 13B), the contact hole is also formed in the monitor FET monitor source electrode 503, monitor drain electrode 504, and insulating film 507 on the gate pad electrode 506. CH is formed. Then, a probe (needle) 10 is brought into contact with each electrode exposed from the contact hole CH. Since each electrode of the monitor FET 500 can be regarded as equivalent to each electrode of the HEMT, the characteristics of the HEMT can be grasped by measuring the characteristics of the monitor FET 500.

  By the way, the gate metal layer 320 of the conventional HEMT is made of Ti / Pt / Au, and the deposited film thicknesses are 400/800/5000 mm, respectively. At the time of measurement, the probe 10 is measured with the Au layer on the outermost surface of the gate pad electrode 506 pierced as shown in FIG. 12, but when the deposited film thickness of the gate metal layer 320 is as thick as several thousand mm, The probe 10 does not break through the gate pad electrode 506, and there is no problem with the contact of the probe 10.

  On the other hand, in order to improve the characteristics of the HEMT, there is a case where Pt is adopted as the lowermost layer of the gate metal layer and a buried gate structure in which a part of Pt is buried in the substrate surface may be adopted. In this case, as will be described later, the vapor deposition film thickness of Pt is preferably 40 to 60 mm. However, in such a case, if the characteristics are measured with a probe, there is a problem that gate conduction failure occurs.

  FIG. 14 shows a gate pad electrode corresponding to the line ee in FIG. 12A when the gate metal layer has a Pt deposition thickness of several tens of mm and the total thickness of the gate metal layer 320 is 200 mm or less. FIG.

  For example, the gate metal layer 320 is made of Pt / Mo and has a deposition thickness of 40 to 60 (Pt) and 50 to (Mo), respectively. Further, a part of the lower layer Pt is buried to a depth of 120 mm from the substrate surface. In the normal measurement, the probe 10 is measured in a state where the probe 10 is pierced about 200 to 300 mm. That is, when the gate metal layer 320 is extremely thin (for example, the total film thickness is 200 mm or less), the probe 10 breaks through the gate pad electrode 506.

  In the case of a switch MMIC employing HEMT, the gate pad electrode 506 of the monitor FET 500 is an insulating layer 250 that is insulated by ion implantation of boron (B +) or the like for the purpose of ensuring insulation from other elements. ing. For this reason, when the probe 10 breaks through the gate pad electrode 506, the probe 10 stands on the insulating layer 250. That is, since the probe 10 and the gate metal layer 320 are not in contact at all, the gate continuity is poor, and there is a problem that the monitor FET cannot be measured normally.

  The present invention has been made in view of the above-mentioned various circumstances. First, a monitor that measures the electrical characteristics of a HEMT provided on a compound semiconductor substrate in which a plurality of semiconductor layers are stacked during the manufacturing process of the HEMT. A first impurity region and a second impurity region provided on the substrate; a source electrode and a drain electrode provided on the first impurity region; and the first electrode region between the source electrode and the drain electrode. This is solved by providing a gate electrode provided in one impurity region and a gate pad electrode connected to the gate electrode and provided on the second impurity region.

  Second, a method for manufacturing a compound semiconductor device, wherein the electrical characteristics of the HEMT are measured by measuring a monitor FET during a manufacturing process of forming the HEMT on a compound semiconductor substrate in which a plurality of semiconductor layers are stacked, Separating the substrate with an insulating layer, forming a first impurity region and a second impurity region constituting the monitor FET, a third impurity region constituting the HEMT, and the first impurity region by an ohmic metal layer Forming a first source electrode and a first drain electrode on the third impurity region and forming a second source electrode and a second drain electrode on the third impurity region; and a first gate on the first impurity region by a gate metal layer. A gate pad electrode is formed on the second impurity region to form a monitor FET, and a second gate electrode is formed on the third impurity region. Forming an insulating film on the entire surface, forming an opening in the insulating film at a predetermined position on the ohmic metal layer and the gate pad electrode, and the first source electrode and the first drain electrode. And a step of bringing a probe into contact with the gate pad electrode and measuring the electrical characteristics of the monitor FET.

  According to the monitor FET of the present invention, electrical characteristics can be normally measured even when the thickness of the gate pad electrode is several tens of millimeters. The monitor FET formed on the same wafer as the HEMT may be measured in a state where the gate pad electrode has a film thickness of several tens of millimeters and a part of Pt, which is the lowermost layer metal, is embedded in the substrate surface of about 100 inches. In this case, since the probe is measured with the tip pierced to a depth of 200 to 300 mm, the measurement is performed with the probe breaking through the gate pad electrode. In the monitor FET of this embodiment, since the second impurity region is provided immediately below the gate pad electrode, electrical connection with the monitor gate electrode is possible even if the probe breaks through the gate pad electrode, and normal measurement is possible. Yes.

  Further, according to the manufacturing method of the present invention, when the buried gate electrode structure in which a part of Pt is buried and the Pt vapor deposition film thickness is set to several tens of millimeters, the electrical measurement can be normally performed by the monitor FET. It is desirable to reduce the thickness of the gate electrode in order to reduce variations in HEMT characteristics. In this case, when the electrical measurement is performed immediately after the HEMT gate electrode is formed, the gate pad electrode of the monitor FET is also thin. In this embodiment, since the second impurity region is provided below the gate pad electrode, the thickness of the gate pad electrode is thin, so that even if the probe may break through the gate pad electrode, electrical connection with the monitor gate electrode is possible. It becomes.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a diagram for explaining the monitor FET of the present embodiment at the time when the characteristic inspection of the monitor FET is performed during the manufacturing process. FIG. 1A is a schematic plan view of a wafer, and FIG. 1B is a plan view of a monitor FET.

  The substrate (wafer) 30 is a compound semiconductor substrate in which a plurality of semiconductor layers are stacked, and the monitor FET 160 is provided on the same substrate as the HEMT that is an actual product. For example, several tens of monitor FETs 160 are arranged in one wafer 30 with respect to a certain number of HEMT formation regions s. For example, when the HEMT is formed by reduction projection exposure using a stepper, several monitor wafers 160 are provided for each shot of the stepper on one wafer 30 (FIG. 1A).

  As shown in FIG. 1B, the monitor FET 160 of this embodiment includes a first impurity region 161, a second impurity region 162, a source electrode 163, a drain electrode 164, a gate electrode 165, and a gate pad electrode 166. Composed.

  The first impurity region 161 and the second impurity region 162 are impurity regions similar to the source region and drain region of the HEMT to be a product. Although the impurity region will be described in detail later, an insulating layer 60 is provided around the first impurity region 161 and the second impurity region 162, and the first impurity region 161 and the second impurity region 162 are separated from each other by the insulating layer 60. Separated by

  In the first impurity region 161, a monitor source electrode 163 and a monitor drain electrode 164 of the monitor FET 160 are provided. The monitor source electrode 163 and the monitor drain electrode 164 are electrodes that are directly fixed to the first impurity region 161, and are electrodes having the same size (about 60 μm width) as the electrode pads for wire bonding because the probe contacts. is there.

  A monitor gate electrode 165 is provided in the first impurity region 161 between the monitor source electrode 163 and the monitor drain electrode 164. Monitor gate electrode 165 extends to the outside of first impurity region 161 and is connected to gate pad electrode 166 provided on second impurity region 162.

  FIG. 2 is a cross-sectional view of the monitor FET. 2A and 2B are cross-sectional views taken along line aa in FIG. 1B, and FIG. 2C is a cross-sectional view taken along line bb in FIG.

  The substrate 30 is formed by laminating a plurality of semiconductor layers on a semi-insulating GaAs substrate 31. The plurality of semiconductor layers are a non-doped buffer layer 32, an electron supply layer 33, a channel (electron travel) layer 35, a barrier layer 36, a stable layer 38, and a cap layer 37. An electron supply layer 33 is disposed above and below the channel layer 35, and a spacer layer 34 is disposed between the channel layer 35 and the electron supply layer 33.

  The buffer layer 32 is a high-resistance layer to which no impurity is added, and its film thickness is about several thousand Å. The non-doped AlGaAs layer serving as the barrier layer 36 is provided in contact with the electron supply layer 33. That is, it is disposed between the stable layer 38 and the electron supply layer 33, and ensures a predetermined breakdown voltage and pinch-off voltage. The stable layer 38 is an InGaP layer which is provided on and in contact with the barrier layer 36 and hardly oxidizes, and is resistant to chemical stress from the outside and stable in terms of reliability. In the figure, the stable layer 38 of the n + InGaP layer is shown, but it may be a non-doped InGaP layer. Further, an n + GaAs layer 37 serving as a cap layer is laminated on the uppermost layer.

  The first impurity region 161 and the second impurity region 162 of the monitor FET 160 are provided, for example, in the region of the one-dot chain line in FIG. 1B by providing and separating the insulating layer 60 reaching the buffer layer 32. Here, the insulating layer 60 is an electrically insulated region which is not electrically completely insulated, but is provided by providing carrier trap levels in the epitaxial layer by ion implantation of impurities (B +). In other words, the insulating layer 60 is not a complete insulating region, but in this specification, all the semiconductor layers other than the insulating layer 60 are impurity regions. That is, a total region including all the semiconductor layers constituting the substrate (wafer) 30 such as the electron supply layer 33, the channel (electron traveling) layer 35, the spacer layer 34, the barrier layer 36, the stable layer 38, and the cap layer 37. Is an impurity region.

  As shown in FIG. 2A, the gate pad electrode 166 is provided on the second impurity region 162 where the non-doped layer (barrier layer) 36 is exposed by etching the cap layer 37 and the stable layer 38, and the barrier layer 36 and the Schottky are formed. Form a bond.

  Further, if the stable layer 38 is a non-doped layer as shown in FIG. That is, the gate pad electrode 166 may be provided on the second impurity region 162 where the cap layer 37 is etched to expose the stable layer (non-doped layer) 38.

  As shown in FIG. 2C, the cap layer 37 of the first impurity region 161 is patterned into a desired shape. That is, the monitor source electrode 163 and the monitor drain electrode 164 are provided on the cap layer 37. On the other hand, the monitor gate electrode 165 is provided on the same semiconductor layer as the gate pad electrode 166. That is, a Schottky junction is formed with the barrier layer 36 on the surface of the first impurity region 161 exposed by patterning of the cap layer 37 and the stable layer 38 of the first impurity region 161.

  Here, the monitor gate electrode 165 is formed on the barrier layer 36, but when the gate pad electrode 166 has the structure shown in FIG. 2B, the monitor gate electrode 165 is exposed to the stable layer 38 (non-doped layer). Provided on top.

  The width w of each of the gate electrode pad 166, the monitor source electrode 163, and the monitor drain electrode 164 is 60 μm. Then, the probe is brought into contact with the contact hole CH obtained by etching the nitride film 167, and the electrical characteristics are measured.

  The monitor gate electrode 165 and the gate pad electrode 166 are, for example, Pt (platinum) / Mo (molybdenum). Moreover, as for these vapor deposition film thickness, Pt is 40 to 60 mm and Mo is 50 mm. Then, Pt is deposited on the lower layer and Mo is deposited on the upper layer. A part of Pt has a structure embedded in the surface of the first impurity region 161 and the second impurity region 162 (the surface of the stable layer 38 or the barrier layer 36) by heat treatment.

For example, when the deposited film thickness of Pt is 50 mm, the embedded Pt (embedded portions 166b and 165b) becomes PtAs ₂ and the depth is 120 mm. Pt deposited on the substrate surface becomes PtGa by a heat treatment for embedding. This thickness is 50 mm, the same as the deposited film thickness.

  As described above, the monitor FET 160 of this embodiment is provided with the second impurity region 162 below the gate pad electrode 166, unlike the conventional monitor FET in which the insulating layer 250 is provided below the gate pad electrode 506. Further, among the metal layers constituting the monitor gate electrode 165 and the gate pad electrode 166, the deposited film thickness of Pt is 40 to 60 mm, and the total film thickness of the metal layer is 200 mm or less.

  The monitor FET 160 is formed in the same process on the same wafer 30 as the HEMT as a product as described above. Then, by measuring the monitor FET 160, for example, after the basic structure of the HEMT is completed, the characteristics of the HEMT that cannot be measured are grasped.

  Although the characteristics of the monitor FET are measured in a plurality of steps, the monitor FET of the present embodiment shows a case where measurement is performed in a state where a gate electrode of HEMT is formed and a contact hole is provided in the nitride film.

  In other words, the metal layers constituting the monitor gate electrode 165 and the gate pad electrode 166 shown in the figure are the gate metal layers constituting the HEMT gate electrode. The nitride film 167 is a nitride film constituting a HEMT passivation film and the like, and the contact hole CH is formed simultaneously with the formation of the contact hole provided in the nitride film of the HEMT.

  By the way, in order to improve the characteristics of the switch MMIC, a buried gate structure of Pt may be adopted for the gate electrode structure of the HEMT. In this case, the Pt vapor deposition film thickness of the gate metal layer constituting the gate electrode is preferably 40 to 60 mm. Although the reason for this will be described in detail later, since the monitor gate electrode and the gate pad electrode of the monitor FET 160 are also formed of the same gate metal layer, the film thickness is reduced as described above.

  FIG. 3 is a diagram for explaining the measurement of the monitor FET 160 in a state where the contact hole is provided. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along the line cc of FIG. 3A.

  The probe 10 is brought into contact with the monitor source electrode 163, the monitor drain electrode 164, and the gate pad electrode 166 through the contact hole CH provided in the nitride film 167, and the characteristics of the monitor FET 160 are measured.

  At this time, since the gate pad electrode 166 is thin, the probe 10 often breaks through the gate pad electrode 166 as shown in FIG.

  However, in the present embodiment, the second impurity region 162 is disposed immediately below the gate pad electrode 166. That is, even when the probe 10 breaks through the gate pad electrode 166, the probe 10 contacts the non-doped layer (stable layer 38 or barrier layer 36) below the n + GaAs layer 37.

The probe 10 is disposed in the PtGa layer on the substrate surface, the Mo layer on the gate metal layer 120, and the first impurity region 161 from the contacted non-doped layer through the metal layer (PtAs ₂ layer) of the peripheral buried portion 166b. The monitor gate electrode 165 is electrically connected. Therefore, the gate conduction failure does not occur as in the prior art.

  Further, by providing the insulating layer 60 around the second impurity region 162, insulation between the gate pad electrode 166 and other elements can be ensured similarly to the conventional monitor FET 500 shown in FIG.

  Furthermore, since the second impurity region 162 can be formed only by changing the ion implantation pattern of the insulating layer 60, it is not necessary to add a special process.

  Next, a method for manufacturing a compound semiconductor device in which characteristics are measured during the process using the above-described monitor FET will be described with reference to FIGS. 4 to 11 by taking a switch MMIC configured by a depletion type HEMT as an example.

  4A and 4B are diagrams illustrating a structure of a compound semiconductor device, in which FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along a line dd in FIG. 4A.

  As shown in FIG. 4A, two HEMTs to be switched, FET1 and FET2 are arranged on the substrate 30 in the central portion. A plurality of electrode pads are arranged around FET1 and FET2. Specifically, the electrode pads are pads IC, O1, O2, C1, and C2 corresponding to the common input terminal IN, the first and second output terminals OUT1 and OUT2, and the first and second control terminals Ctl1 and Ctl2. Control resistors R1 and R2 are connected to the gate electrode of each FET. Note that the metal layer indicated by a dotted line is a gate metal layer (Pt / Mo) 120 formed simultaneously with the formation of the gate electrode 127 of each FET. A metal layer indicated by a solid line is a pad metal layer (Ti / Pt / Au) 130 that forms connection of each element, formation of a pad, and a second source electrode and drain electrode of each FET. The ohmic metal layer (AuGe / Ni / Au) bonded to the substrate 30 in an ohmic manner forms the first source electrode, drain electrode, and extraction electrodes at both ends of each of the FETs. It is not shown to overlap.

  A comb-like pad metal layer 130 extending toward the center of the chip is a second drain electrode 136 (or source electrode) connected to the output terminal pad O1, and a layer formed of an ohmic metal layer below this drain electrode 136. There is an eye drain electrode (or source electrode). Further, a comb-like pad metal layer 130 extending outward from the center of the chip is a second-layer source electrode 135 (or drain electrode) connected to the common input terminal pad IC, and an ohmic metal layer is formed thereunder. There is a first-layer source electrode (or drain electrode).

  The HEMT operation region 200a is provided in a region indicated by a one-dot chain line. In the operation region 200a, a source electrode 135 and a drain electrode 136 are arranged in a shape in which comb teeth are engaged. A gate electrode 127 formed of the gate metal layer 120 is disposed in a comb shape between the source electrode 135 and the drain electrode 136, and forms a Schottky junction with a part of the operation region 200a.

  The gate electrode 127 of FET1 and the control terminal pad C1 are connected by a control resistor R1, and the gate electrode 127 of FET2 and the control terminal pad C2 are connected by a control resistor R2. The control resistors R1 and R2 are constituted by the impurity region 200b. A peripheral impurity region 200c is provided around each pad to improve isolation.

  Here, the HEMT operation region 200 a is an impurity region separated by providing an insulating layer 60 reaching the buffer layer 32. In the switch MMIC, the impurity regions 200b and the peripheral impurity regions 200c constituting the control resistors R1 and R2 are also separated by the insulating layer 60. In the present embodiment, the impurity regions 200a, 200b, and 200c constituting the HEMT or the switch MMIC are all defined as the third impurity region 200.

  As shown in FIG. 4B, the HEMT substrate 30 is formed by laminating a plurality of semiconductor layers on a semi-insulating GaAs substrate 31. The plurality of semiconductor layers are a non-doped buffer layer 32, an electron supply layer 33, a channel (electron travel) layer 35, a barrier layer 36, a stable layer 38, and a cap layer 37. An electron supply layer 33 is disposed above and below the channel layer 35, and a spacer layer 34 is disposed between the channel layer 35 and the electron supply layer 33.

  The buffer layer 32 is a high-resistance layer to which no impurity is added, and its film thickness is about several thousand Å. The non-doped AlGaAs layer serving as the barrier layer 36 is provided in contact with the electron supply layer 33. That is, it is disposed between the stable layer 38 and the electron supply layer 33, and ensures a predetermined breakdown voltage and pinch-off voltage.

  The stable layer 38 is an InGaP layer which is provided on and in contact with the barrier layer 36 and hardly oxidizes and is resistant to chemical stress from the outside and is stable in reliability, and has a thickness of about 100 mm. In the figure, the stable layer 38 of the n + InGaP layer is shown, but the stable layer 38 may be a non-doped InGaP layer. The stable layer 38 also functions as an etch stop layer. The stable layer 38 is etched in the same pattern as that of the upper cap layer 37. However, the stable layer 38 may be a non-doped InGaP layer, and the gate electrode 127 may be provided on the stable layer 38 without etching the stable layer 38.

Further, an n + GaAs layer 37 serving as a cap layer is laminated on the uppermost layer. The cap layer 37 has a thickness of 600 mm or more and an impurity concentration of 2 × 10 ¹⁸ cm ⁻³ or more, preferably a film thickness of about 1000 mm and an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more. The electron supply layer 33 is made of a material having a larger band gap than the channel layer 35. The impurity concentration of the n-type impurity (for example, Si) in the n + AlGaAs layer of the electron supply layer 33 is related to Vp, on-resistance Ron, and breakdown voltage, but in this embodiment, about 2 to 4 × 10 ¹⁸ cm ⁻³ (preferably Is 2.6 × 10 ¹⁸ cm ⁻³ ).

  In addition, in order to prevent crystal defects such as slits caused by distortion in the crystal, the InGaP layer (stable layer) 38 is formed of GaAs, that is, the n + GaAs layer (cap layer) 37 and the non-doped AlGaAs layer (barrier layer) 36 here. Match the lattice. Further, since the non-doped AlGaAs layer (barrier layer) 36 and the electron supply layer 33 are both AlGaAs layers, they are lattice-matched.

  The cap layer 37 is patterned into a desired shape to become a source region 37s and a drain region 37d with which the first-layer source electrode 115 and drain electrode 116 are in contact, respectively. On the source electrode 115 and the drain electrode 116, a second-layer source electrode 135 and drain electrode 136 formed of the pad metal layer 130 are in contact with each other. The gate electrode 127 is disposed between the source region 37s and the drain region 37d.

  The HEMT operation region 200a includes the HEMT source electrodes 115 and 135, the drain electrodes 116 and 136, and the gate electrode among the third impurity regions 200 separated by providing an insulating layer (not shown here) reaching the buffer layer 32. A semiconductor layer in a region where 127 is disposed. That is, the impurity region including all the semiconductor layers constituting the HEMT such as the electron supply layer 33, the channel (electron transit) layer 35, the spacer layer 34, the barrier layer 36, the stable layer 38, and the cap layer 37 is defined as the operation region 200a. To do.

  The gate electrode 127 forms a Schottky junction with the barrier layer 36 on the surface of the operation region 200 a exposed by patterning of the cap layer 37 and the stable layer 38.

  The gate electrode 127 is, for example, Pt / Mo, and the deposited film thickness thereof is 45 mm for Pt and 50 mm for Mo. In addition, a part of Pt, which is the lowermost layer metal, is embedded in the barrier layer 36 by heat treatment. The buried Pt functions as the gate electrode 127. The depth of the buried Pt is, for example, 108 mm, and its bottom is located in the barrier layer 36. As a result, a pinch-off voltage of -0.8V is realized.

  When the deposited film thickness of Pt is 110 mm or less, the Pt embedding depth is 2.4 times the deposited film thickness of Pt and has a linear characteristic with a constant proportional coefficient. That is, the embedding depth can be controlled by the deposited film thickness of Pt. Since the buried Pt functions as a gate electrode, the bottom of the gate electrode of the HEMT is provided at a position deeper than the embedding depth. That is, if the deposited film thickness of Pt is 110 mm or less, the HEMT pinch-off voltage (hereinafter referred to as Vp) can be controlled by controlling the embedding depth. This is because the VMT of HEMT can be easily controlled by the deposited film thickness of Pt. It means that it can be controlled.

  Incidentally, the production variation when depositing Pt is ± 10%. That is, as the deposited film thickness increases, the production variation increases, and therefore the embedded depth variation also increases. Specifically, when the deposited film thickness of Pt becomes larger than 60 mm, the Vp variation exceeds the variation allowable range required for the HEMT.

  On the other hand, when the Pt vapor deposition film thickness is less than 40 mm, the Pt vapor deposition time is too short, and the dispersion of the Pt vapor deposition film thickness is also large. Therefore, when adopting the buried gate structure, the deposited film thickness of Pt is preferably 40 to 60 mm.

  Further, it is desirable that a metal that does not react with GaAs in Pt embedment heat treatment, such as Mo, is continuously deposited on Pt following Pt. When the gate electrode is formed of only Pt, foreign matter may adhere to the Pt surface between the time after Pt deposition and the time when Pt is embedded. In that case, even the adhering foreign matter is involved in the Pt embedding heat treatment reaction, and the FET characteristics are deteriorated. By covering the top of Pt with Mo, even if the same foreign matter adheres to Mo, Mo becomes a barrier and the foreign matter does not participate in the Pt embedding heat treatment reaction. If the thickness of Mo is too large, stress occurs between Pt and it is desirable that the thickness of Mo be at most the same as the thickness of Pt. Since Pt thickness is 40 to 60 mm, Mo is also set to about 50 mm.

  When the deposited film thickness of the gate electrode is thin, the resistance value of the gate electrode itself increases. However, in the case of the switch MMIC, since a resistance (control resistance) of about 10 KΩ or more is inserted between the gate electrode and the control terminal, there is no problem even if the resistance value of the gate electrode itself is high. Therefore, a gate metal layer structure in which Pt is 40 to 60% and Mo is 50% is preferable.

  The method for manufacturing the HEMT will be described below with reference to FIGS. 5 to 11 which are sectional views of the operating region of the HEMT and the monitor FET. In each cross-sectional view, (A) is a cross-sectional view taken along the line dd in FIG. 4 (A), (B) is a cross-sectional view taken along the line bb in FIG. 1 (B), and (C) is the cross-sectional view in FIG. Aa line sectional drawing is shown.

  The manufacturing method of the compound semiconductor device of this embodiment is a compound semiconductor device that grasps the electrical characteristics of the HEMT by measuring the monitor FET during the manufacturing process of forming the HEMT on the compound semiconductor substrate in which a plurality of semiconductor layers are stacked. The substrate is separated by an insulating layer, the first impurity region and the second impurity region constituting the monitor FET, the third impurity region constituting the HEMT, and the ohmic metal layer Forming a first source electrode and a first drain electrode on one impurity region, forming a second source electrode and a second drain electrode on the third impurity region, and forming a first metal region on the first impurity region by a gate metal layer; A monitor FET is formed by forming one gate electrode, a gate pad electrode on the second impurity region, and a second gate electrode on the third impurity region. A step of forming each, a step of forming an insulating film on the entire surface, forming an opening in the insulating film at a predetermined position on the ohmic metal layer and the gate pad electrode, a first source electrode, a first drain electrode, and a gate pad A probe is brought into contact with the electrode, and the electrical characteristics of the monitor FET are measured.

  First step (FIG. 5): a step of separating the substrate with an insulating layer, and forming a first impurity region and a second impurity region constituting the monitor FET, and a third impurity region constituting the HEMT.

  As shown in FIG. 5, a plurality of semiconductor layers are stacked on a semi-insulating GaAs substrate 31. The semiconductor layers are a buffer layer 32, an electron supply layer 33, a channel (electron travel) layer 35, an electron supply layer 33, a barrier layer 36, a stable layer 38, and a cap layer 37, and between the electron supply layer 33 and the channel layer 35. The spacer layer 34 is disposed.

  The non-doped buffer layer 32 is a high-resistance layer to which no impurity is added, and has a film thickness of about several thousand cm and is often formed of a plurality of layers.

On the buffer layer 32, an n + AlGaAs layer 33 serving as an electron supply layer, a spacer layer 34, a non-doped InGaAs layer 35 serving as a channel layer, a spacer layer 34, and an n + AlGaAs layer 33 serving as an electron supply layer are sequentially formed. The electron supply layer 33, channel layer 35 material having a large band gap is used than, n-type impurities (e.g., Si) of about 2 to 4 la ¹⁰ 18 ^{cm -3} (e.g. 2.6 × ¹⁰ 18 ^{cm -3)} It has been added.

  The barrier layer 36 is a non-doped AlGaAs layer stacked on the electron supply layer 33 in order to ensure a predetermined breakdown voltage and pinch-off voltage. A stable layer 38 that is resistant to chemical stress from the outside and is stable in terms of reliability is provided on the upper layer because it is difficult to oxidize. The stable layer 38 is a non-doped InGaP layer or an n + InGaP layer, and also functions as an etch stop layer. Further, an n + GaAs layer 37 serving as a cap layer is laminated on the uppermost layer.

The stable layer 38 has a thickness of 100 mm, and the underlying barrier layer 36 has a thickness of 250 mm. The cap layer 37 has a thickness of 1000 、, and the impurity concentration is 3 × 10 ¹⁸ cm ⁻³ or more.

  As described above, the HEMT of this embodiment employs a double heterojunction structure in which the electron supply layers 33 are disposed above and below the channel layer 35.

  Then, an initial nitride film 50 is deposited on the entire surface of the substrate. The initial nitride film 50 serves as a protective film on the substrate surface after the wafer is loaded. Alternatively, it becomes a protective film for activation annealing of impurities implanted when an insulating layer is formed in a later step. Or they are shared by both.

  A resist (not shown) is provided, and a mask in which an alignment mark pattern is opened is formed by a photolithography process. The initial nitride film 50 and a part of the cap layer 37 are etched using this mask to form alignment marks (not shown).

  After removing the resist, a new resist (not shown) is provided, and a mask for forming an insulating layer is formed by a photolithography process. Boron (B +) is ion-implanted from above the initial nitride film 50 and the resist is removed, followed by annealing at 500 ° C. for about 30 seconds. Thereby, the insulating layer 60 reaching the buffer layer 32 is formed.

  The insulating layer 60 is not electrically completely insulated but is an insulating region in which carrier traps are provided in the epitaxial layer by ion implantation of impurities (B +). That is, impurities are present as an epitaxial layer in the insulating layer 60, but are inactivated by B + implantation for insulation.

  That is, by forming the insulating layer 60 in a predetermined pattern, the third impurity region which becomes the HEMT operation region 200a, the impurity region 200b (not shown) constituting the control resistance, and the peripheral impurity region 200c (not shown). 200 is separated (FIG. 5A).

  At the same time, the first impurity region 161 and the second impurity region 162 constituting the monitor FET 160 are also separated by the insulating layer 60 (FIGS. 5B and 5C).

  Second step (FIG. 6): forming a first source electrode and a first drain electrode on the first impurity region by using an ohmic metal layer, and forming a second source electrode and a second drain electrode on the third impurity region. .

  The initial nitride film 50 on the entire surface is removed, and the cap layer 37 is exposed. In this embodiment, the initial nitride film 50 is removed, and a nitride film serving as a mask for the recess etching of the gate is newly deposited in a later process. Thereby, the subsequent nitride film can be formed in a uniform film thickness.

  A new resist PR is applied to the entire surface, and a mask for forming an ohmic electrode is formed by a photolithography process. Then, an ohmic metal layer (AuGe / Ni / Au) 110 is deposited on the entire surface.

  Then lift off and alloy. As a result, the monitor source electrode 163 and the monitor drain electrode 164 that become the first source electrode and the first drain electrode, respectively, are formed on the first impurity region 161.

  In addition, the source electrode 115 and the drain electrode 116 of the first layer that are in contact with a part of the operation region 200a of the HEMT and respectively become the second source electrode and the second drain electrode are formed.

  Thereafter, a first nitride film 511 is formed on the entire surface. The first nitride film 511 serves as a mask for recess etching of the gate. The first nitride film 511 has a substantially uniform film thickness and film quality, and is in close contact with the surface and side surfaces of the source electrode 115 and the drain electrode 116 and the cap layer 37 in the vicinity thereof. That is, the step between the source electrode 115 (same as the drain electrode 116) and the cap layer 37 is completely covered, and no gap is formed around the source electrode 115 (drain electrode 116). Thereby, the surface of the cap layer 37 in the vicinity of the source electrode 115 and the drain electrode 116 can be completely protected from the chemical solution and moisture during the subsequent manufacturing process or after completion of the wafer. Therefore, the occurrence of the galvanic effect can be prevented.

  Third step (FIGS. 7 and 8): a first FET is formed on the first impurity region and a gate pad electrode is formed on the second impurity region by the gate metal layer to form a monitor FET; Forming a second gate electrode thereon;

  A new resist PR is provided for forming the gate electrode. A mask in which the formation region of the gate electrode is patterned is formed by a photolithography process. Then, the first nitride film 511 exposed in the opening of the mask is removed, and the gate is etched by recess. That is, the cap layer 37 exposed in the opening OP of the first nitride film 511 is further removed by wet etching, and the InGaP layer 38 that is a stable layer is exposed in the opening OP.

  The cap layer 37 is side-etched to a predetermined dimension larger than the width of the gate electrode formation region in order to ensure a breakdown voltage. The predetermined dimension is, for example, a distance of 0.3 μm from a gate electrode to be formed later. At this time, the GaAs layer as the cap layer and the InGaP layer as the stable layer therebelow are selectively etched, so that the InGaP layer is not etched during the side etching. By etching the cap layer 37, the cap layer 37 in the operation region 200 a is separated into a source region 37 s that contacts the source electrode 115 and a drain region 37 d that contacts the drain electrode 116.

  By side etching of the cap layer 37, the first nitride film 511 protrudes from the cap layer 37 in an eave shape. The overhanging eaves part is removed by plasma etching from the back side because the resist is in close contact with the surface. If the eaves are left, the resist cannot be applied uniformly when forming the gate electrode 127, and the gate electrode 127 cannot be formed normally. Even if the gate electrode 127 can be formed, a nitride film to be a passivation film to be formed later is not formed under the eaves portion, and a cavity is formed around the gate electrode 127, which causes a problem in reliability.

  Here, when the eaves portion is removed by wet etching, the operation region 200a is not damaged, and the removal of the eaves portion causes the surface depletion layer to reach the n + AlGaAs layer 233 of the electron supply layer or the non-doped InGaAs layer 235 of the channel layer. The problem of increasing the on-resistance by reaching it can be prevented. However, wet etching tends to be overetched, and the source electrode 115 (drain electrode 116) may be exposed. As a result, the cap layer 37 may be etched during the process due to the galvanic effect, so wet etching is inappropriate.

  Therefore, the eaves portion is removed by dry etching. At this time, the surface of the operation region 200a exposed to dry etching plasma when the eaves are removed is covered with a stable InGaP layer 38. Therefore, etching can be performed without damaging the operation region 200a. Further, since dry etching is used, only the eaves portion can be removed, and the first nitride film 511 is not over-etched.

  Thereafter, while exposing the resist PR, the exposed InGaP layer 38 is further etched and removed to expose the barrier layer 36 as shown. As described above, when plasma etching is performed, the surface of the operation region 200a is protected by the InGaP layer 38, and then the InGaP layer 38 that has undergone plasma damage is removed, whereby the gate electrode 127 can be formed on the clean barrier layer 36. .

  In this step, a part of the first impurity region 161 of the monitor FET 160 and the second impurity region 162 are similarly etched. That is, after the cap layer 37 is removed by etching, the eaves portion is removed. Thereafter, the stable layer 38 is removed to expose the barrier layer 36.

  Next, a gate metal layer 120 is deposited on the entire surface. The gate metal layer 120 is, for example, Pt / Mo, and the deposited film thickness is 45 mm for Pt and 50 mm for Mo (FIG. 7).

  Thereafter, lift-off is performed, and a heat treatment for embedding Pt of the lowermost layer metal of the gate metal layer 120 is performed. As a result, a part of Pt is embedded in the barrier layer 36 while maintaining a Schottky junction with the barrier layer 36. A monitor gate electrode 165 is formed on the barrier layer 36 exposed between the monitor source electrode 163 and the monitor drain electrode 164 in the first impurity region 161. Further, the gate pad electrode 166 is formed on the barrier layer 36 exposed in the second impurity region 162, and the monitor FET 160 is formed. At the same time, the gate electrode 127 is formed on the barrier layer 36 exposed in the operation region 200a which is the third impurity region.

The depth of the embedded Pt is, for example, 108 mm. The embedded Pt becomes PtAs ₂ , and Pt deposited on the substrate surface becomes PtGa by the heat treatment for embedding. (FIG. 8)).

  Although not shown, in the case of a switch circuit device, a gate wiring for bundling the gate electrode 127 is also formed by this step.

  On the Pt as the gate metal layer 120, it is desirable to continuously deposit a metal such as Mo that does not react with GaAs in the Pt embedding heat treatment, following the Pt. The gate metal layer is preferably Pt / Mo.

  As a metal that does not react with GaAs due to heat, W (tungsten) may be considered instead of Mo. However, since W has a high melting point, it is generally formed by sputtering and cannot be formed by vapor deposition. Therefore, W cannot be formed continuously with the vapor deposition of Pt, and since high heat is generated in the case of sputtering, the resist cannot withstand and formation by lift-off is impossible.

  In the present embodiment, the HEMT characteristics can be improved by using an embedded gate structure in which a part of the lowermost layer metal of the gate electrode is embedded in the substrate surface. This is because Pt embedded as shown in the figure has a round bottom end. Accordingly, the electric field strength is dispersed when a reverse bias is applied to the gate electrode, as compared with a gate electrode (for example, Ti / Pt / Au) that does not have a buried gate structure with a sharp bottom end. That is, the buried gate structure is because the maximum electric field strength is weakened and the breakdown voltage is significantly increased.

  Conversely, when designing to a predetermined breakdown voltage, the buried gate structure can greatly increase the impurity concentration of the electron supply layer 33 as the electric field strength near the gate electrode is weakened, and can greatly reduce the on-resistance Ron. . That is, the electron supply layer 33 of the present embodiment is designed so that the HEMT constituting the switch circuit can obtain the maximum characteristics.

  In order to ensure a predetermined breakdown voltage, the gate electrode 127 is deposited on the surface of the barrier layer 36 which is a non-doped layer, and a part of the gate electrode 127 is embedded in the barrier layer 36. That is, there is no layer doped with impurities between the gate electrode 127 and the electron supply layer 33, and the gate electrode 127 is provided in the non-doped layer 36 that is substantially continuous with the electron supply layer 33. .

As described above, the HEMT can realize a very low on-resistance while ensuring a predetermined breakdown voltage by the double heterojunction structure and the structure in which the gate electrode is provided in the non-doped layer continuous to the electron supply layer 33. . In other words, by adopting a Pt buried gate structure, a double heterojunction structure, and a structure in which the electron supply layer to the gate electrode are all non-doped layers while having a gate breakdown voltage of 20 V, the concentration of the electron supply layer is 2.6. × 10 ¹⁸ cm ^-3 can be increased. As a result, an on-resistance Ron = 1.4Ω / mm was realized when the gate voltage Vg = 0V as the on-resistance per 1 mm of the gate width at Vp = −0.8V. It can be said that the on-resistance value is extremely low for a switching HEMT.

  The stable layer 38 may be a non-doped InGaP layer. Thus, the stable layer 38 is not etched, that is, after etching the first nitride film 511 in the opening of the resist PR in the step shown in FIG. 7, only the cap layer 37 is etched to expose the stable layer 38, and the first nitride film The elongate portion 511 may be removed by dry etching, and the gate metal layer 120 may be deposited on the stable layer 38. Then, by performing a heat treatment in the process shown in FIG. 8, a part of Pt of the gate metal layer 120 is embedded in the stable layer 38 which is a non-doped layer. Although the surface of the stable layer 38 is exposed to dry etching for removing the eaves portion, the stable layer 38 is hardly changed chemically compared to AlGaAs that is easily oxidized because it contains Al. Even if the surface of the stable layer 38 is somewhat damaged, a part of Pt of the gate metal layer 120 is embedded in the stable layer 38, so that the bottom of the gate electrode is located at a place where there is no damage, and dry etching is performed. The HEMT characteristics do not deteriorate. Even in this case, there is no layer doped with impurities between the gate electrode 127 and the electron supply layer 33, and the gate electrode 127 is provided in the non-doped layers 36 and 38 that are substantially continuous to the electron supply layer 33. It will be.

  Fourth step (FIG. 9): A step of providing an insulating film on the entire surface and forming an opening in the insulating film at a predetermined position on the ohmic metal layer and the gate pad electrode.

  When the third step is completed, the basic structure of the FET is completed. The monitor FET 160 is measured in a plurality of steps during the manufacturing process. First, in this state, the monitor FET 160 performs measurement.

  A second nitride film 512 serving as a passivation film is deposited on the entire surface. The gate electrode 127 and the barrier layer 36 exposed around the gate electrode 127 are covered with a second nitride film 512. At this time, the first nitride film 511 has a substantially uniform thickness and covers the source electrode 115 (drain electrode 116) and the cap layer 37 around the end thereof. Accordingly, the second nitride film 512 formed on the upper layer of the first nitride film 511 also has a uniform film formation density, and can be covered evenly. Therefore, even after the wafer is completed, the infiltration of moisture or chemicals can be prevented and the galvanic effect can be prevented.

  The second nitride film 512 also covers the monitor gate electrode 165 and the gate pad electrode 166 of the monitor FET 160.

  Then, a new resist (not shown) is provided to form a mask for forming a contact hole, and the source electrode 115, the drain electrode 116, the monitor source electrode 163 of the monitor FET 160, the monitor drain electrode 164, and further a gate pad electrode The first nitride film 511 and the second nitride film 512 on 166 are etched. As a result, a contact hole CH is formed on the source electrode 115, the drain electrode 116, the monitor source electrode 163, the monitor drain electrode 164, and the gate pad electrode 166. The depth of the contact hole is the total thickness T3 of the first nitride film 511 and the second nitride film 512.

  Further, the contact hole CH is not formed on the gate electrode 127 of the HEMT and the monitor gate electrode 165 of the monitor FET 160.

  As a result, the contact hole CH is also formed in the nitride film 51 (167) of the monitor FET 160.

  Fifth step (FIG. 10): A step of contacting the probe with the first source electrode, the first drain electrode, and the gate pad electrode, and measuring the electrical characteristics of the monitor FET.

  The probe 10 is brought into contact with the monitor source electrode 163, the monitor drain electrode 164, and the gate pad electrode 166 through the contact hole CH of the monitor FET 160.

  In the present embodiment, the second impurity region 162 is disposed immediately below the gate pad electrode 166. That is, since the gate metal layer 120 is thin, even if the probe may break through the gate pad electrode 166, the probe contacts the non-doped layer (stable layer 38 or barrier layer 36) below the n + GaAs layer 37.

The probe 10 includes a gate metal layer 120 (a PtGa layer and a Mo layer after heat treatment) on the substrate surface through a metal layer (PtAs ₂ layer) of a peripheral buried portion 166b from a non-doped layer (here, the barrier layer 36) in contact, Then, it is electrically connected to the monitor gate electrode 165 disposed in the first impurity region 161. Therefore, the gate conduction failure does not occur as in the prior art, and the electrical characteristics of the monitor FET 160 can be accurately measured.

  Since the insulating layer 60 is disposed around the second impurity region 162, the gate pad electrode 166 and the monitor source electrode 163, the monitor drain electrode 164, or the components of the HEMT can ensure sufficient insulation.

  As described above, by providing the second impurity region 162 in this embodiment, the monitor FET 160 can be accurately measured even when the gate metal layer 120 of the HEMT is thin. Since the second impurity region 162 can be formed only by changing the ion implantation pattern of the insulating layer 60, it is not necessary to add a special process.

  Sixth step (FIG. 11): a step of forming a pad metal layer, forming an upper layer electrode in contact with each electrode except the first gate electrode through the opening, and measuring other electrical characteristics.

  A HEMT is formed by forming a wiring pattern or the like with a pad metal layer. That is, a new resist (not shown) is provided to form a mask, and a pad metal layer (Ti / Pt / Au) 130 is deposited and lifted off.

  As a result, a second-layer source electrode 135 and a drain electrode 136 are formed in contact with the first-layer source electrode 115 and the drain electrode 116, respectively. Further, in the case of the switch circuit device shown in FIG. 4, each electrode pad P and wiring are also formed in a desired pattern by this process, and the HEMT 150 is formed.

  In addition, a second monitor source electrode 170 and a monitor drain electrode 168 are also formed on the monitor source electrode 163 and the monitor drain electrode 164 of the monitor FET 160 by a pad metal layer. Further, a second-layer gate pad electrode 169 is also formed on the gate pad electrode 166 by a pad metal layer. Note that the second layer electrode is not provided on the monitor gate electrode 165.

  Although not shown, the measurement by the monitor FET 160 is performed again in this state. That is, the characteristics of the HEMT 150 after forming the wiring pattern and the like are grasped by bringing the probe into contact with the monitor source electrode 170, the monitor drain electrode 168, and the gate pad electrode 169 in the second layer again and measuring the characteristics of the monitor FET 160. .

  Further, a third nitride film 513 serving as a jacket film is formed on the entire surface. The third nitride film 513 covers the second nitride film 512 and the source electrode 135 and drain electrode 136. Here, the thickness T1 of the nitride film 51 on the gate electrode 127, the thickness T3 of the nitride film 51 around the contact hole CH on the source electrode 115 (drain electrode 116), and the second source electrode 135 (second drain). The following relationship holds for the film thickness T2 of the nitride film 51 on the electrode 136).

T3- (T1-T2)> 0
That is, T3- (T1-T2) is the thickness of the first nitride film 511, and since this inequality reaches the contact hole CH portion of the first nitride film 511, the source electrode 115 (drain electrode 116) is surrounded. It indicates that there is no gap and the galvanic effect is prevented as described above. The third nitride film 513 may or may not exist, and the inequality is established by substituting T3 = 0 for the case where the third nitride film 513 does not exist.

  Further, although not shown in the figure, an opening for wire bonding is provided in the jacket nitride film of the bonding pad portion.

  In the present embodiment, the switch MMIC is shown as an example of a plan view of the HEMT. However, the present invention is not limited to this, and the present invention can be applied to a method for manufacturing a HEMT that is a basic element.

  Further, although the above example has been described for the depletion type HEMT, the enhancement type HEMT can be similarly implemented.

Furthermore, a semiconductor device in which a depression type HEMT and an enhancement type HEMT are integrated on the same substrate may be used.

It is a top view for demonstrating the monitor FET of this invention. It is sectional drawing for demonstrating the monitor FET of this invention. It is (A) top view and (B) sectional view for explaining the present invention. It is (A) top view and (B) sectional view for explaining the present invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is sectional drawing for demonstrating the manufacturing method of this invention. It is (A) top view and (B) sectional drawing explaining the conventional monitor FET. It is sectional drawing for demonstrating the conventional manufacturing method. It is sectional drawing for demonstrating a prior art.

Explanation of symbols

10 Probe 30 Substrate (wafer)
31 GaAs substrate 32 Buffer layer 33 Electron supply layer 34 Spacer layer 35 Channel layer 36 Barrier layer 37 Cap layer 38 Stable layer 37 s Source region 37 d Drain region 60 Insulating layer 50 Initial nitride film 51 Nitride film 511 First nitride film 512 Second Nitride film 513 Third nitride film 110 Ohmic metal layer 115, 135 Source electrode 116, 136 Drain electrode 120 Gate metal layer 127 Gate electrode 130 Pad metal layer 150 HEMT
160 Monitor FET
161 First impurity region 162 Second impurity region 163, 170 Monitor source electrode 164, 168 Monitor drain electrode 165 Monitor gate electrode 166 Gate pad electrode 169 Gate pad electrode 165b, 166b Embedded portion 167 Nitride film 200 Third impurity region 200a Operation region 200b Control resistance 200c Peripheral impurity region 231 GaAs substrate 232 Buffer layer 233 Electron supply layer 234 Spacer layer 235 Channel layer 236 Barrier layer 237 Cap layer 237s Source region 237d Drain region 250 Insulating layer 251 Nitride film 2511 Nitride film 2511 Through ion implantation nitride film 2512 Passivation film 300 Operating region 310 Ohmic metal layer 315, 335 Source electrode 316, 336 Drain electrode 320 Gate Metal layer 327 Gate electrode 330 Pad metal layer 500 Monitor FET
501 impurity region 503 monitor source electrode 504 monitor drain electrode 505 monitor gate electrode 506 gate pad electrode 507 nitride film OP opening CH contact hole PR resist IN common input terminal Ctl1 control terminal Ctl2 control terminal OUT1 output terminal OUT2 output terminal IC common input terminal Pad C1 First control terminal pad C2 Second control terminal pad O1 First output terminal pad O2 Second output terminal pad s HEMT formation region

Claims (12)

A monitor FET for measuring the electrical characteristics of a HEMT provided on a compound semiconductor substrate in which a plurality of semiconductor layers are stacked, during the manufacturing process of the HEMT,
A first impurity region and a second impurity region provided in the substrate;
A source electrode and a drain electrode provided on the first impurity region;
A gate electrode provided in the first impurity region between the source electrode and the drain electrode;
A monitor FET comprising: a gate pad electrode connected to the gate electrode and provided on the second impurity region.   2. The monitor FET according to claim 1, wherein the metal layer constituting the gate pad electrode has a thickness of 200 mm or less.   2. The monitor FET according to claim 1, wherein the metal layer constituting the gate pad electrode is made of at least one metal, and a deposition thickness of the one metal is 60 mm or less.   The monitor FET according to claim 3, wherein a part of the one metal is embedded in the second impurity region.   The monitor FET according to claim 3, wherein the one metal is Pt.   The monitor FET according to claim 1, wherein an upper layer electrode is provided on each of the electrodes excluding the gate electrode. A method of manufacturing a compound semiconductor device in which the electrical characteristics of the HEMT are measured by measuring a monitor FET during a manufacturing process of forming the HEMT on a compound semiconductor substrate in which a plurality of semiconductor layers are stacked,
Separating the substrate with an insulating layer, and forming a first impurity region and a second impurity region constituting the monitor FET, and a third impurity region constituting the HEMT;
Forming a first source electrode and a first drain electrode on the first impurity region by an ohmic metal layer, and forming a second source electrode and a second drain electrode on the third impurity region;
A monitor FET is formed by forming a first gate electrode on the first impurity region and a gate pad electrode on the second impurity region by a gate metal layer, and a second gate electrode on the third impurity region. Forming, and
Providing an insulating film on the entire surface, and forming an opening in the insulating film at a predetermined position on the ohmic metal layer and the gate pad electrode;
Contacting a probe with the first source electrode, the first drain electrode, and the gate pad electrode, and measuring electrical characteristics of the monitor FET;
A method of manufacturing a compound semiconductor device comprising:   8. The pad metal layer is formed, an upper electrode in contact with each electrode except the first gate electrode is formed through the opening, and the electrical characteristics are measured again. A method for manufacturing a compound semiconductor device.   8. The method of manufacturing a compound semiconductor device according to claim 7, wherein the gate metal layer is formed to a thickness of 200 mm or less.   8. The method of manufacturing a compound semiconductor device according to claim 7, wherein the gate metal layer is made of at least one metal, and a deposition thickness of the one metal is 60 mm or less.   11. The method of manufacturing a compound semiconductor device according to claim 10, wherein a part of the one metal is embedded in the first, second, and third impurity regions by heat treatment.   The method of manufacturing a compound semiconductor device according to claim 10, wherein the one metal is Pt.