JP2006209415A - Microcomputer - Google Patents

Abstract

Power consumption is reduced for a microcomputer equipped with a ROM having a larger operating power than a RAM or a logic circuit.
A CPU, a ROM that stores data necessary for the processing of the CPU, a memory that saves and stores read data D1 from the ROM, and an address corresponding to the data that is saved from the ROM to the memory are stored. Each time the CPU designates an address, the designated address is compared with the stored address to determine whether or not they match. If they match, the data reading from the ROM 13 is enabled and the read data is When the data does not match, the judgment control circuit 12 that enables data reading from the memory 14 is selected. When the judgment result of the judgment control circuit does not match, the data read from the ROM 13 is selected. Is a selection circuit 15 that selects and outputs read data from the memory 14; Provided.
[Selection] Figure 1

Description

  The present invention relates to a technique for reducing the power consumption of a microcomputer on which a memory having a large power consumption such as a flash memory is mounted as a storage means used by a CPU (central processing unit).

  FIG. 11 shows a schematic diagram of a microcomputer as a first conventional example (see, for example, Non-Patent Document 1). The CPU 31 outputs an access signal b1 and an address signal a1 to a ROM (Read Only Memory) 32. Receiving the access signal b1, the ROM 32 outputs the data at the address specified by the address signal a1 to the CPU 31 as read data d1. The CPU 31 stores the read data d1 in a built-in register and performs a predetermined process.

  FIG. 12 shows a schematic diagram of a microcomputer as a second conventional example (see, for example, Patent Document 1). The microcomputer includes a CPU 41, a cache controller 42, a cache memory 43, and a ROM 44.

  The CPU 41 outputs an access signal B11 and an address A11 to the cache controller 42. The cache controller 42 that has received the access signal B11 compares the address A11 with the address of the data cached in the cache memory 43 (hereinafter referred to as a cache address).

  When the comparison results match, the cache controller 42 outputs the access signal B13 and the address A13 to the cache memory 43. The cache memory 43 outputs read data D12. The CPU 41 stores the read data D12 and performs a predetermined process. The CPU 41 can read the cache data in a basic CPU cycle and execute a predetermined process.

  On the other hand, when they do not match, in the first CPU cycle, the cache controller 42 outputs the access signal B12 and the address A12 to the ROM 44 and outputs the rewrite control signal Wc to the cache memory 43. Receiving the access signal B12, the ROM 44 outputs read data D11. In the CPU cycle after the first CPU cycle, the cache memory 43 that has received the rewrite control signal Wc caches the read data D11. When the cache process is completed, the address A11 and the cache address match, so the cache controller 42 outputs the access signal B13 and the address A13, and the cache memory 43 outputs the read data D12 as described above.

The cache controller 42 normally accesses the cache memory 43, and the ROM 44 is accessed only when the cache addresses do not match. Therefore, if the current consumption of the cache memory 43 is less than that of the ROM 44, the system can be reduced in consumption.
JP-A-7-134701 (page 13, FIG. 17) MN101C Series LSI Manual

  In the case of the first conventional example, since the ROM 31 outputs the data d11 every time the access signal b1 is input, there is a problem that the current consumption of the ROM 31 increases.

  In the case of the second conventional example, if the cache addresses do not match, as a result, a waiting time for re-cache from the ROM 44 to the cache memory 43 occurs before the CPU 41 executes a predetermined process. Become. There is a problem that it takes extra time for the CPU 41 to rewrite the cache memory 43 until the CPU 41 stores the data in the ROM 44, and the processing capacity of the CPU decreases.

  The present invention has been created in view of such circumstances, and has an object to reduce the operating frequency of the ROM and the power consumption of the microcomputer without reducing the processing capability of the CPU.

The microcomputer according to the present invention includes:
CPU,
First storage means for storing data necessary for the processing of the CPU;
Second storage means for evacuating and storing read data from the first storage means;
An address corresponding to the data saved from the first storage means to the second storage means is stored as a storage address, and each time the CPU specifies an address, the specified address is compared with the storage address. It is determined whether or not they coincide with each other. If they match, the data reading from the first storage means is validated and the read data is saved in the second storage means. Determination control means for validating data reading from the storage means,
Selecting means for selecting read data from the first storage means when the determination result of the determination control means does not match, and selecting and outputting the read data from the second storage means when they match. It is provided.

  According to this configuration, data is read from the first storage means and transferred to the CPU, and at the same time, the read data is transferred and stored in the second storage means and saved. At this time, the addresses designated by the CPU are often localized, and when data of the same address is read, the number of times of reading to the first storage means is reduced by using the data saved in the second storage means. In addition, since the data can be read without causing any penalty in the read cycle of the stored data, there is an effect of reducing the power without degrading the processing performance of the CPU.

  In the above-described configuration, there are several preferable modes for some of the components as follows.

  First, the data width of the read data of the first storage means and the data width of the read data of the second storage means are set to an enlarged data width that is an integral multiple of the data width of the CPU, The selection means is configured to select read data having the same width as the CPU data width, in accordance with a designated address from the CPU, among the read data having an enlarged data width selected by the determination result by the determination control means. It is what.

  If comprised in this way, the frequency | count of reading to a 1st memory | storage means will be reduced, and also there exists an electric power reduction effect.

  Second, the first storage means includes a plurality of first storage means having the same width as the data width of the CPU, and the second storage means is provided by the plurality of first storage means. The selection unit is configured to save the read data in a lump, and the selection unit further includes a group of read data from the plurality of first storage units selected based on a determination result by the determination control unit, and further from the CPU. According to the designated address, read data having the same width as the CPU data width is selected.

  If comprised in this way, the effect equivalent to the above is realizable using the 1st memory | storage means of the same data width as CPU.

  Third, the CPU is configured to output a low consumption mode signal to the first storage unit and the determination control unit, and the first storage unit receives the low consumption mode signal. Is configured to operate at a low speed in data reading, and when the low consumption mode signal is input, the determination control means activates and outputs a standby signal to the CPU when the determination result does not match. When the determination result is coincident, the standby signal is configured to remain inactive.

  With this configuration, the power consumption of the microcomputer can be reduced when the processing performance of the CPU is not necessary, and high-speed reading is possible when reading the data saved in the second storage means.

  According to the present invention, when the first storage means having a large power consumption is used, the power consumption of the entire microcomputer can be reduced and the processing performance of the CPU can be prevented from being lowered.

  Embodiments of a microcomputer according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a schematic configuration of a microcomputer according to Embodiment 1 of the present invention.

  The microcomputer includes a CPU 11, a determination control circuit 12, a ROM 13 as a first storage unit, a memory 14 as a second storage unit, and a selection circuit 15. The CPU 11 outputs a read control signal R0 and an address A1, stores read data D3, and performs a predetermined process.

  The determination control circuit 12 receives the read control signal R0 and the address A1, determines whether the data at the address specified by the address A1 is read from the ROM 13 or the memory 14, and reads the data from the ROM 13 Read control signal R1, memory write control signal W1, and memory address A2 are output. The ROM read control signal R1 is output to the ROM 13 and the selection circuit 15, and the memory write control signal W1 and the memory address A2 are output to the memory 14. On the other hand, when it is determined to read data from the memory 14, the memory read control signal R2 and the memory address A2 are output to the memory 14, the memory read control signal R2 is output to the selection circuit 15, and the ROM read control signal R1 and the memory The write control signal W1 remains inactive.

  When the ROM read control signal R1 and the address A1 are input, the ROM 13 outputs the designated data to the selection circuit 15 and the memory 14 as ROM read data D1.

  When the memory 14 receives the memory write control signal W1, the memory 14 stores the ROM read data D1 read from the ROM 13 at the address specified by the memory address A2, while holding the memory read control signal R2 This data is output to the selection circuit 15 as memory read data D2.

  When receiving the ROM read control signal R1, the selection circuit 15 outputs the ROM read data D1 from the ROM 13 to the CPU 11 as read data D3. When receiving the memory read control signal R2, the selection circuit 15 reads the memory read data D2 from the memory 14. Output as data D3.

  The ROM read data D1, the memory read data D2, and the read data D3 have the same data width as that of the CPU 11.

  FIG. 2 is a block diagram showing details of the determination control circuit 12.

  The determination control circuit 12 includes an address temporary storage circuit 21 including a plurality of address storage memories M1, M2,... Mn, a storage memory selection circuit 22, a comparator 23, a ROM control circuit 24, and a memory control circuit 25.

  The address storage memories M1, M2,... Mn are configured to output the storage addresses Am1, Am2,.

  The comparator 23 compares the address A1 output from the CPU 11 with the storage addresses Am1, Am2,... Amn from the address storage memories M1, M2,... Mn, and the address A1 matches any of the storage addresses Am1, Am2,. If there is, the address match signal Sh and the match memory address Ah are output. The address match signal Sh is supplied to the storage memory selection circuit 22, the ROM control circuit 24, and the memory control circuit 25, and the match memory address Ah is supplied to the memory control circuit 25. When the address A1 does not match any of the storage addresses Am1, Am2,... Amn, both the address match signal Sh and the match memory address Ah remain inactive.

  When the address match signal Sh from the comparator 23 is inactive, the storage memory selection circuit 22 activates any one of the address storage signals Ss1, Ss2,... Ss3, and the address storage memories M1, M2,. The corresponding one of them is set to the update state, and the address A1 from the CPU 11 is held as a storage address.

  Each of the address storage memories M1, M2,... Mn is updated when the read control signal R0 from the CPU 11 is active, and when the address storage signals Ss1, Ss2,. It is set to hold the address A1 from the CPU 11 as a storage address.

  The ROM control circuit 24 is configured to output the read control signal R0 from the CPU 11 to the ROM 13 and the selection circuit 15 as the ROM read control signal R1 when the address match signal Sh from the comparator 23 is inactive. . When the address match signal Sh from the comparator 23 is activated, the ROM read control signal R1 is not activated even if the read control signal R0 is input.

  When the address match signal Sh from the comparator 23 is inactive, the memory control circuit 25 activates the memory write control signal W1 and outputs it to the memory 14, while the memory read control signal R2 remains inactive. Is configured to do. On the other hand, when the address coincidence signal Sh is activated, the memory read control signal R2 is activated and outputted to the memory 14 and the selection circuit 15, and from the coincidence memory address Ah inputted from the comparator 23, the corresponding memory Address A2 is output to memory 14, while memory write control signal W1 remains inactive.

  FIG. 3 is a block diagram showing details of the selection circuit 15. In this embodiment, the selection circuit 15 is simply the selection circuit 15a itself.

  When the ROM read control signal R1 from the determination control circuit 12 becomes active, the selection circuit 15a selects the ROM read data D1 output from the ROM 13 and sends it to the CPU 11 as read data D3. Conversely, when the memory read control signal R2 from the determination control circuit 12 becomes active, the memory read data D2 output from the memory 14 is selected and sent to the CPU 11 as read data D3.

  Next, the operation of the microcomputer of the present embodiment configured as described above will be described. FIG. 4 is a timing chart showing a series of operations in the microcomputer of the present embodiment.

  When the CPU 11 outputs the read control signal R0 and the address A1, the read control signal R0 and the address A1 are input to the determination control circuit 12, and the address A1 is given to the ROM 13.

  The determination control circuit 12 receives the read control signal R0 and the address A1, and determines whether the data at the address specified by the address A1 is read from the ROM 13 or the memory 14. As a result of the determination, when it is determined to read from the ROM 13, the ROM read control signal R 1 and the memory write control signal W 1 are activated and the memory address A 2 is output to the memory 14. The activated ROM read control signal R1 is output to the ROM 13 and the selection circuit 15, and the memory write control signal W1 and the memory address A2 are output to the memory 14. On the other hand, when it is determined to read from the memory 14, the memory read control signal R2 is activated and output to the memory 14 and the selection circuit 15, and the memory address A2 is given to the memory 14. At this time, the ROM read control signal R1 and the memory write control signal W1 remain inactive.

  The operation of the determination control circuit 12 will be described in more detail.

  The address storage memories M1, M2,... Mn output the stored storage addresses Am1, Am2, ... Amn to the comparator 23 when the read control signal R0 from the CPU 11 is input. The comparator 23 receives the read control signal R0 from the CPU 11 and the address A1. The comparator 23 having received the read control signal R0 compares the address A1 from the CPU 11 with the storage addresses Am1, Am2,... Amn.

(1) When the comparison results do not match When the address A1 does not match any of the storage addresses Am1, Am2,... Amn, the comparator 23 inactivates the address match signal Sh, and the ROM control circuit 24 and the storage memory The data is sent to the selection circuit 22. The storage memory selection circuit 22 to which the inactive address coincidence signal Sh has been input sends an address storage signal (Ss1, Ss2... Ss3) to an appropriate one of the address storage memories M1, M2. In the selected address storage memory Mi (i = 1, 2,... N), the address A1 from the CPU 11 is updated and written. At the same time, the ROM control circuit 24 to which the inactive address match signal Sh is input outputs the read control signal R0 from the CPU 11 to the ROM 13 and the selection circuit 15 as the active ROM read control signal R1. As described above, the ROM 13 is set to the read state, and the selection circuit 15 is switched to the state for selecting the ROM read data D1 from the ROM 13. Upon receiving the inactive address match signal Sh, the memory control circuit 25 activates the memory write control signal W1 and deactivates the memory read control signal R2.

  The ROM 13 that has received the active ROM read control signal R1 from the ROM control circuit 24 and the address A1 from the CPU 11 outputs the corresponding data to the selection circuit 15 and the memory 14 as ROM read data D1. On the other hand, the selection circuit 15 receiving the active ROM read control signal R1 and the inactive memory read control signal R2 from the ROM control circuit 24 selects the ROM read data D1 from the ROM 13 and transfers it to the CPU 11 as read data D3. To do.

  The memory 14 to which the active memory write control signal W1 is input from the memory control circuit 25 stores the ROM read data D1 from the ROM 13 at the memory address A2 from the memory control circuit 25.

  In the above operation, the fact that the ROM read data D1 is saved in the memory 14 is stored by updating the storage address Ami (i = 1, 2,... N) in the temporary address storage circuit 21.

(2) When the comparison result is coincidence When the address A1 from the CPU 11 coincides with one of the storage addresses Am1, Am2,... Amn, the comparator 23 activates the address coincidence signal Sh and sets the memory control circuit 25 and The data is sent to the ROM control circuit 24, and the address A1 is transferred to the memory control circuit 25 as the coincidence memory address Ah. The storage memory selection circuit 22 to which the active address match signal Sh is input does not operate. Further, the ROM control circuit 24 to which the active address match signal Sh is input is also inoperative, and the ROM read control signal R1 is not output to the ROM 13. On the other hand, the memory control circuit 25 that has received the active address match signal Sh outputs the read control signal R0 from the CPU 11 to the memory 14 and the selection circuit 15 as the active memory read control signal R2, and also receives a match from the comparator 23. The memory address Ah is given to the memory 14 as the memory address A2. The memory write control signal W1 remains inactive. As described above, the memory 14 is set to the read state, and the selection circuit 15 is switched to the state for selecting the memory read data D2 from the memory 14.

  The memory 14 having received the active memory read control signal R2 and the memory address A2 from the memory control circuit 25 outputs the cached data to the selection circuit 15 as the memory read data D2. On the other hand, the selection circuit 15 receiving the active memory read control signal R2 and the inactive ROM read control signal R1 from the memory control circuit 25 selects the memory read data D2 from the memory 14 and sends it to the CPU 11 as read data D3. Forward.

  When the address A1 from the CPU 11 matches the address previously read from the ROM 13 and the save storage has already been performed in the memory 14, the saved data is read from the memory 14. Is not performed, and the ROM 13 is set in a standby state.

  If they do not match, the data is read from the ROM 13, the data is temporarily stored in the memory 14, and the address is stored.

  In the above description, the determination control circuit 12 determines whether to read data from the ROM 13 or the memory 14 at the time when the address A1 is output from the CPU 11, and also reads data to the CPU 11 and stores data in the memory 14. Are performed in the same cycle as the ROM read cycle of the CPU 11, the processing performance of the CPU 11 does not deteriorate.

  According to the microcomputer of this embodiment, it is possible to reduce the number of times of reading to the ROM by reusing the read data from the ROM, and the mounted ROM has a larger operating current than the memory and logic circuit. Even if it is a thing, reduction of power consumption is attained.

(Embodiment 2)
FIG. 5 is a block diagram showing a schematic configuration of the microcomputer according to the second embodiment of the present invention.

This embodiment corresponds to the data bus width increased in the first embodiment. That is, the ROM read data D1 bus connecting the ROM 13, the memory 14 and the selection circuit 15 has an expanded data width of a power of 2 (2 ² , 2 ⁴ , 2 ⁸ ...) With respect to the data width of the CPU 11. . Also, the memory read data D2 bus connecting the memory 14 and the selection circuit 15 has the same expanded data width.

  FIG. 6 is a block diagram showing details of the selection circuit 15. The selection circuit 15 includes a first selection circuit 15a and a second selection circuit 15b. The first selection circuit 15a is configured to select the ROM read data D1 having the expanded data width and the memory read data D2 having the expanded data width and output the selected read data D4.

  The second selection circuit 15b is connected to the next stage of the first selection circuit 15a, and is a bit specified by the address A1 from the CPU 11 in the selection read data D4 of the expanded data width input from the first selection circuit 15a. The position data is selected and output as read data D3.

  Since other configurations are the same as those in the first embodiment, the same reference numerals are given to the same portions, and descriptions thereof are omitted.

  In the present embodiment, since the data widths of the ROM read data D1 and the memory read data D2 are expanded as compared with the first embodiment, the probability of reuse of read data from the ROM is improved, and reading from the ROM is performed. It is possible to reduce the number of times. As a result, the power consumption of the microcomputer can be reduced.

(Embodiment 3)
FIG. 7 is a block diagram showing a schematic configuration of the microcomputer according to the third embodiment of the present invention.

  The present embodiment corresponds to a configuration in which a plurality of components corresponding to the ROM 13 are arranged in parallel in the first embodiment. That is, a plurality of ROMs 13a, 13b,... 13n are arranged as ROMs accessible by the CPU 11. These ROMs 13a, 13b,... 13n receive the address A1 from the CPU 11, and when the active ROM read control signal R1 from the determination control circuit 12 is input, the data at the corresponding address is designated as ROM read data D1a, D1b,. It is configured to output to the selection circuit 15 and the memory 14. These ROMs 13a, 13b... 13n have the same capacity. Data write in the memory 14 is stored at an address designated by the memory address A2 when the memory write control signal W1 is active. The data width of the individual ROM read data D1a, D1b... D1n is the same as the data width of the CPU 11, and the data width of the memory read data D2 corresponds to the sum of the data widths of the ROM read data D1a, D1b.

  FIG. 8 is a block diagram showing details of the selection circuit 15. The selection circuit 15 includes a first selection circuit 15a and a second selection circuit 15b. The first selection circuit 15a is configured to select a group of ROM read data D1a, D1b,... D1n and memory read data D2 having an expanded data width and output selected read data D4.

  The second selection circuit 15b is connected to the next stage of the first selection circuit 15a, and is a bit specified by the address A1 from the CPU 11 in the selection read data D4 of the expanded data width input from the first selection circuit 15a. The position data is selected and output as read data D3.

  Since other configurations are the same as those in the first embodiment, the same reference numerals are given to the same portions, and descriptions thereof are omitted.

  In this embodiment, since the capacity of ROM data temporarily stored in the memory 14 is increased compared to the first embodiment, the probability of reuse of read data from the ROM is improved, and the number of times of reading from the ROM is reduced. It is possible to reduce. Also, unlike the second embodiment, the same effect as in the second embodiment can be realized even if a ROM having a small data bus width is used.

(Embodiment 4)
The present embodiment relates to a microcomputer having a mode for operating the system with low power consumption.

  FIG. 9 is a block diagram showing a schematic configuration of the microcomputer according to the fourth embodiment of the present invention. FIG. 10 is a block diagram showing details of the determination control circuit 12 of FIG.

  The CPU 11 is configured to activate and output the low consumption mode signal Sm to the ROM 13 and the determination control circuit 12 when operating the system with low power consumption. The ROM 13 is configured such that when the active low consumption mode signal Sm is input from the CPU 11, the operation speed is reduced so that the operation with low power consumption is possible.

  The comparator 23 in the determination control circuit 12 receives the read control signal R0 from the CPU 11 when the active low consumption mode signal Sm is input, and the address A1 from the CPU 11 is one of the storage addresses Am1, Am2,. If they do not coincide with each other, it is determined that data reading from the ROM 13 is performed. At the same time, the read standby signal Sst is activated until the ROM 13 receives the ROM read data D1. It is configured to output to. When the addresses match, it is determined that data is read from the memory 14, but at this time, the read standby signal Sst remains inactive.

  The CPU 11 receiving the active read standby signal Sst from the determination control circuit 12 stops its operation and realizes low power consumption.

  Since other configurations are the same as those in the first embodiment, the same reference numerals are given to the same portions, and descriptions thereof are omitted.

  In the present embodiment, when the read control signal R0 and the address A1 are output from the CPU 11 in a state where the low consumption mode signal Sm is activated and the ROM 13 is shifted to the low speed low consumption mode, the determination control circuit 12 When the address determination is not coincident, the read standby signal Sst is activated and the operation of the CPU 11 is stopped. On the other hand, when the address determination is coincident and the memory read data D2 is read from the memory 14, the read standby signal Sst is Leave active. As a result, data can be read at high speed even in the low consumption mode.

  The technology of the present invention is particularly useful for a single chip microcomputer suitable for a device that requires low power consumption.

1 is a block diagram showing a configuration of a microcomputer according to Embodiment 1 of the present invention. 1 is a block diagram showing a configuration of a determination control circuit of a microcomputer according to Embodiment 1 of the present invention. 1 is a block diagram showing a configuration of a selection circuit of a microcomputer according to Embodiment 1 of the present invention. Timing chart showing the operation of the microcomputer according to the first embodiment of the present invention. The block diagram which shows the structure of the microcomputer in Embodiment 2 of this invention. The block diagram which shows the structure of the selection circuit of the microcomputer in Embodiment 2 of this invention. The block diagram which shows the structure of the microcomputer in Embodiment 3 of this invention. The block diagram which shows the structure of the selection circuit of the microcomputer in Embodiment 3 of this invention. The block diagram which shows the structure of the microcomputer in Embodiment 4 of this invention. The block diagram which shows the structure of the determination control circuit of the microcomputer in Embodiment 4 of this invention 1 is a schematic configuration diagram of a microcomputer according to a first conventional example. Schematic configuration diagram of microcomputer of second conventional example

Explanation of symbols

11 CPU (Central Processing Unit)
12 determination control circuit 13 ROM (read-only memory; first storage means)
13a, 13b ... 13n ROM
14 Memory (second storage means)
DESCRIPTION OF SYMBOLS 15 Selection circuit 15a 1st selection circuit 15b 2nd selection circuit 21 Address temporary storage circuit 22 Storage memory selection circuit 23 Comparator 24 ROM control circuit 25 Memory control circuit A1 Address A2 Memory address Ah Match memory address Am1, Am2 ... Amn Storage address D1 ROM read data D1a, D1b ... D1n ROM read data D2 Memory read data D3 Read data D4 Select read data M1, M2 ... Mn Address storage memory R0 Read control signal R1 ROM read control signal R2 Memory read control signal Sh Signal Ss1, Ss2... Ss3 Address storage signal Sm Low consumption mode signal Sst Read standby signal W1 Memory write control signal

Claims (4)

CPU,
First storage means for storing data necessary for the processing of the CPU;
Second storage means for evacuating and storing read data from the first storage means;
An address corresponding to the data saved from the first storage means to the second storage means is stored as a storage address, and each time the CPU specifies an address, the specified address is compared with the storage address. It is determined whether or not they coincide with each other. If they match, the data reading from the first storage means is validated and the read data is saved in the second storage means. Determination control means for validating data reading from the storage means,
Selecting means for selecting read data from the first storage means when the determination result of the determination control means does not match, and selecting and outputting the read data from the second storage means when they match. A microcomputer equipped. The data width of the read data of the first storage means and the data width of the read data of the second storage means are set to an enlarged data width that is an integral multiple of the data width of the CPU,
The selection means is configured to select read data having the same width as the CPU data width, in accordance with a designated address from the CPU, among the read data having an enlarged data width selected by the determination result by the determination control means. The microcomputer according to claim 1. The first storage means includes a plurality of first storage means having the same width as the data width of the CPU,
The second storage unit is configured to collectively save read data from the plurality of first storage units,
The selection means further selects read data having the same width as the CPU data width from the group of read data from the plurality of first storage means selected by the determination result by the determination control means according to the designated address from the CPU. The microcomputer of claim 1 configured to select. The CPU is configured to output a low consumption mode signal to the first storage unit and the determination control unit,
The first storage means is configured to operate at a low speed in data reading when the low consumption mode signal is input,
The determination control means activates and outputs a standby signal to the CPU when the determination result does not match when the low consumption mode signal is input, and the standby signal when the determination result matches. The microcomputer according to any one of claims 1 to 3, wherein the microcomputer is configured to remain inactive.

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