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JP2006216977A - Semiconductor device - Google Patents

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Publication number
JP2006216977A
JP2006216977A JP2006072497A JP2006072497A JP2006216977A JP 2006216977 A JP2006216977 A JP 2006216977A JP 2006072497 A JP2006072497 A JP 2006072497A JP 2006072497 A JP2006072497 A JP 2006072497A JP 2006216977 A JP2006216977 A JP 2006216977A
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layer
resin
metal layer
semiconductor device
electrode layer
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JP3993218B2 (en
Inventor
Hiroshi Nakagawa
宏史 中川
Yasuharu Tominaga
安治 富永
Noriyuki Numata
典之 沼田
Hiroshi Kimura
浩 木村
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Torex Semiconductor Ltd
Maxell Ltd
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Kyushu Hitachi Maxell Ltd
Torex Semiconductor Ltd
Hitachi Maxell Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

【課題】リードレス表面実装方式の半導体装置において、高精度,小型,薄型タイプでありながら、密着強度の向上が図れ信頼性にも優れた半導体装置を提供する。
【解決手段】半導体素子Sが搭載される金属層2aと、該金属層2aの周りに所定の間隔をおいて配置される1以上の電極層2bと、上記金属層2a上に搭載した半導体素子Sと電極層2bとを、ワイヤーボンディング等の方法で電気的に接続した状態で樹脂封止して、金属層2aと電極層2bの各裏面を樹脂層4の底面から露出して形成した半導体装置であり、樹脂封止される上記金属層2a及び電極層2b各々の上端部周縁を、庇状に張り出し、樹脂層4に喰い込む構造とする。
【選択図】図1
A semiconductor device of a leadless surface mounting system is provided with high reliability, a small size, and a thin type, and improved reliability and excellent reliability.
A metal layer 2a on which a semiconductor element S is mounted, one or more electrode layers 2b arranged around the metal layer 2a at a predetermined interval, and a semiconductor element mounted on the metal layer 2a A semiconductor in which S and the electrode layer 2b are resin-sealed in a state where they are electrically connected by a method such as wire bonding, and the back surfaces of the metal layer 2a and the electrode layer 2b are exposed from the bottom surface of the resin layer 4 The device has a structure in which the periphery of the upper end of each of the metal layer 2a and the electrode layer 2b to be resin-sealed extends in a bowl shape and bites into the resin layer 4.
[Selection] Figure 1

Description

本発明は半導体装置に関し、小型・薄型化を図れ、かつ信頼性の高い樹脂封止型の半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a resin-encapsulated semiconductor device that can be reduced in size and thickness and has high reliability.

この種半導体装置としては、例えばリードフレームのようなパターン金属を用いて、リードフレーム上に搭載した半導体素子とリードフレームに形成した外部端子とを電気的に接続した上で、樹脂封止して外部端子を露出させる形態の小型の半導体装置がある。   As this type of semiconductor device, for example, using a pattern metal such as a lead frame, a semiconductor element mounted on the lead frame and an external terminal formed on the lead frame are electrically connected and then resin-sealed. There is a small semiconductor device in which an external terminal is exposed.

このような半導体装置は、小型あるいは薄型化を図るために、樹脂封止を半導体素子が搭載されたリードフレームの片面側のみに施し、樹脂封止底面側からリードフレームの外部端子を露出させるようにしている構造が採用されている。   In order to reduce the size or thickness of such a semiconductor device, resin sealing is performed only on one side of the lead frame on which the semiconductor element is mounted, and external terminals of the lead frame are exposed from the resin sealing bottom side. The structure is used.

しかしながら、かかる半導体装置では、外部端子となるリードフレームと封止樹脂との間の密着強度が低いため、樹脂剥がれが生じたり、リードフレームの外部端子が抜け出る不良が散見され、装置に対する信頼性が著しく損なわれるものである。   However, in such a semiconductor device, since the adhesion strength between the lead frame serving as the external terminal and the sealing resin is low, there are some cases in which the resin peels off or the lead frame external terminal comes out, and the reliability of the device is high. It is seriously damaged.

本発明の目的は、かかる従来の問題点を解決するために提案されたものであって、小型かつ薄型の半導体装置を製造するにあたり、装置を構成する部品を封止樹脂内で強固に結着し、極めて信頼性に優れた半導体装置の構造を提供することにある。   The object of the present invention is proposed to solve such conventional problems, and in manufacturing a small and thin semiconductor device, the components constituting the device are firmly bound in a sealing resin. Another object of the present invention is to provide a highly reliable semiconductor device structure.

本発明は、上記課題を解決するためのものであって、半導体素子Sが搭載される金属層2aと、該金属層2aの周りに所定の間隔をおいて配置される1以上の電極層2bと、上記金属層2a上に搭載した半導体素子Sと電極層2bとを、ワイヤーボンディング等の方法で電気的に接続した状態で樹脂封止して、金属層2aと電極層2bの各裏面を樹脂層4の底面から露出して形成した半導体装置において、樹脂封止される上記金属層2a及び電極層2b各々の上端部周縁を、庇状に張り出し形成して構成したことを特徴とする。   The present invention is for solving the above-described problem, and includes a metal layer 2a on which a semiconductor element S is mounted, and one or more electrode layers 2b disposed around the metal layer 2a at a predetermined interval. Then, the semiconductor element S mounted on the metal layer 2a and the electrode layer 2b are resin-sealed in a state where they are electrically connected by a method such as wire bonding, and the back surfaces of the metal layer 2a and the electrode layer 2b are bonded to each other. In the semiconductor device formed to be exposed from the bottom surface of the resin layer 4, the periphery of the upper end of each of the metal layer 2a and the electrode layer 2b to be resin-sealed is formed so as to project in a bowl shape.

以上説明したように、本発明によれば、半導体素子Sが搭載される金属層2aと、上記半導体素子Sと電気的に接続される電極層2bの各々の裏面を封止樹脂である樹脂層4の底面から露出させた形態として、半導体装置の小型・薄型化を図り、また放熱特性にも優れたものでありながら、さらには、金属層2aや電極層2bの上端部周縁に意図的に庇状の張り出し部11を形成することによって樹脂封止工程において、樹脂層4に対し各張り出し部11がくい込み状に位置するため、この喰い付き効果により、金属層2a,電極層2bと樹脂層4との結着力が向上し、樹脂剥れやズレ等の不良が確実に防止でき、製品化後の品質並びに信頼性の向上が図れる。また、庇状の張り出し部11の特有の形状により、金属層2a及び電極層2bの表面側への水分等の浸入を阻止するとともに、沿面距離も稼ぐ効果もあり、結線部分や半導体素子側への耐水性耐湿性の向上も図ることができるものである。   As described above, according to the present invention, the resin layer in which the back surface of each of the metal layer 2a on which the semiconductor element S is mounted and the electrode layer 2b electrically connected to the semiconductor element S is a sealing resin. As a form exposed from the bottom surface of the semiconductor device 4, the semiconductor device is made small and thin and has excellent heat dissipation characteristics. Further, the semiconductor device is intentionally formed on the periphery of the upper end of the metal layer 2a or the electrode layer 2b. In the resin sealing step, the overhanging portions 11 are positioned in a bite shape with respect to the resin layer 4 by forming the flange-like overhanging portions 11, so that the metal layer 2 a, the electrode layer 2 b, and the resin layer 4 can be improved and defects such as resin peeling and misalignment can be surely prevented, and quality and reliability after commercialization can be improved. In addition, the unique shape of the ridge-like overhanging portion 11 has an effect of preventing moisture and the like from entering the surface side of the metal layer 2a and the electrode layer 2b and also increasing the creepage distance. It is also possible to improve the water resistance and moisture resistance.

本発明の1実施例について、図面を参照し説明する。
図1は、本発明に係るリードレス表面実装型の半導体装置を示しており、同図(a)は断面図、同図(b)は底面図である。同図において、Sは半導体素子であって、金属層2a上に接着されて搭載されている。Lは半導体素子S上に形成された電極であり、上記金属層2aと独立して並設された対応する電極層2bと金等の導電性のワイヤ3により結線され、電気的に接続されている。上記半導体素子Sの搭載部分は熱硬化性エポキシ樹脂等の樹脂層4にて封止されており、上記金属層2aと電極層2bの各裏面が露出した樹脂封止体が構成されている。
また、金属層2a及び電極層2bの各々の上端部周縁には、断面庇形状に張り出した張り出し部11,11を一体に形成している。この張り出し部11,11の存在により、樹脂層4との間の結着強度が向上することとなる。
An embodiment of the present invention will be described with reference to the drawings.
1A and 1B show a leadless surface mounting type semiconductor device according to the present invention, in which FIG. 1A is a sectional view and FIG. 1B is a bottom view. In the figure, S is a semiconductor element, which is mounted on the metal layer 2a by bonding. L is an electrode formed on the semiconductor element S, and is connected and electrically connected by a corresponding electrode layer 2b arranged in parallel with the metal layer 2a by a conductive wire 3 such as gold. Yes. The mounting portion of the semiconductor element S is sealed with a resin layer 4 such as a thermosetting epoxy resin, and a resin sealing body is formed in which the back surfaces of the metal layer 2a and the electrode layer 2b are exposed.
In addition, projecting portions 11 and 11 projecting in a cross-sectional shape are integrally formed on the periphery of the upper end portions of the metal layer 2a and the electrode layer 2b. Due to the presence of the overhang portions 11, 11, the binding strength with the resin layer 4 is improved.

次に、上記実施例に係る半導体装置の製造方法について詳述すると、図2及び図3は上記半導体装置の製造方法を工程ごとに示しており、図2(a)はステンレスやアルミ、銅等の導電性の金属板、例えば本実施例の場合SUS430により形成された0.1mm厚の基板1の両面に約50μm厚のアルカリタイプの感光性フィルムレジストをラミネートする等して、感光性レジスト層5,5を密着させる工程であり、次いで図2(b)のごとく基板1の一面側の感光性レジスト層5上に所定パターンのフィルムFを配した状態で紫外線照射による両面露光を行った後現像処理を行い図2(c)に示すような、基板1の一面側に所定のパターンニングを施したレジストパターン層6とその裏面に硬化したレジスト層5を得る。   Next, the semiconductor device manufacturing method according to the above embodiment will be described in detail. FIGS. 2 and 3 show the semiconductor device manufacturing method for each process, and FIG. 2A shows stainless steel, aluminum, copper, and the like. A conductive resist plate, such as laminating an alkali type photosensitive film resist having a thickness of about 50 μm on both surfaces of a substrate 1 having a thickness of 0.1 mm formed by SUS430 in this embodiment, and the like. 5 and 5, and after performing double-sided exposure by ultraviolet irradiation in a state where a film F having a predetermined pattern is arranged on the photosensitive resist layer 5 on one side of the substrate 1 as shown in FIG. Development processing is performed to obtain a resist pattern layer 6 having a predetermined patterning on one surface side of the substrate 1 and a cured resist layer 5 on the back surface thereof as shown in FIG.

次いで、基板1の一面側のレジストパターン層6で覆れていない露出面に対し、必要に応じて化学エッチングによる表面酸化被膜除去や薬品による周知の化学処理等の表面活性化処理を行った後、基板1に電鋳を行い、図2(d)に示すごとく基板1のレジストパターン層6により規定された露出面より導電性金属の電着物を成長させ、半導体搭載用の金属層2aと1の金属層2aに対して1以上の独立した電極層2bを各々対として、複数組を並列形成する。なお、電着物としてはニッケルやニッケル−コバルト合金、銅その他種々の金属が考えられるが、本実施例においては、スルファミン酸ニッケルの無光沢浴を使用し、本図のA−A部分の拡大図である図4に示すごとく、レジストパターン層6の厚みを超えて電着させるいわゆるオーバーハングさせることで、後述するようにレジストパターン層6除去後に、図2(e)及び同図のB−B部分の拡大図である図5に示すように、金属層2a及び電極層2bの上端部周縁に断面庇形状の張り出し部11,11が一体に形成されるようにしている。ここで、上記表面活性化処理の工程については、必須の工程ではない。   Next, after the surface activation treatment such as removal of the surface oxide film by chemical etching or well-known chemical treatment with chemicals is performed on the exposed surface not covered with the resist pattern layer 6 on the one surface side of the substrate 1 as necessary. Then, electroforming is performed on the substrate 1, and an electrodeposit of conductive metal is grown from the exposed surface defined by the resist pattern layer 6 of the substrate 1 as shown in FIG. One or more independent electrode layers 2b are paired with the metal layer 2a, and a plurality of sets are formed in parallel. In addition, although nickel, nickel-cobalt alloy, copper, and various other metals can be considered as electrodeposits, in this embodiment, a matte bath of nickel sulfamate is used, and an enlarged view of the AA portion of this figure. As shown in FIG. 4, by so-called overhang that is electrodeposited beyond the thickness of the resist pattern layer 6, after removing the resist pattern layer 6 as will be described later, FIG. 2 (e) and BB in FIG. As shown in FIG. 5, which is an enlarged view of the portion, overhanging portions 11 and 11 having a bowl-shaped cross section are integrally formed on the periphery of the upper end portions of the metal layer 2a and the electrode layer 2b. Here, the surface activation process is not an essential process.

図2(d)による電鋳工程の後、必要に応じて各金属層2aおよび電極層2bの表面に結着力向上用の金メッキ等を0.3〜0.4μm厚で行い、基板1の両面よりレジストパターン層6及びレジスト層5を除去することで、図2(e)の状態となる。なお、レジストの除去法としてはアルカリ溶液による膨潤除去の方法等が考えられる。   After the electroforming step according to FIG. 2D, the surface of each metal layer 2a and electrode layer 2b is subjected to gold plating for improving the binding force to a thickness of 0.3 to 0.4 μm as necessary, and both surfaces of the substrate 1 are formed. By removing the resist pattern layer 6 and the resist layer 5 further, the state of FIG. In addition, as a method for removing the resist, a method for removing swelling with an alkaline solution, or the like can be considered.

次いで図3(a)に示すごとく、半導体素子Sを公知の手法により金属層2a上に接着して搭載するとともに、上記半導体素子S上の電極Lにこれと対応する電極層2bとを、図3(b)のごとく、金線等の導電性のワイヤ3を用いて超音波ボンディング装置等により結線する。ここで、ワイヤ3を結線するにあたり、各電極層2bにはボンディング装置からの引き離し力が作用し、基板1から浮き上がろうとするが、上記のごとく、電鋳工程に先立って、基板1の露出面に対し表面活性化処理を行うことにより、基板1と電着層との密着力を予め向上させているため、結線時における電極層2bの脱落や浮き上がりを効果的に予防でき、製造工程時の不良品形成率を低減できる。   Next, as shown in FIG. 3A, the semiconductor element S is mounted on the metal layer 2a by a known method, and the electrode L 2b corresponding to the electrode L on the semiconductor element S is shown in FIG. As in 3 (b), the wire is connected by an ultrasonic bonding apparatus or the like using a conductive wire 3 such as a gold wire. Here, when the wires 3 are connected, each electrode layer 2b is subjected to a pulling force from the bonding apparatus and tends to float from the substrate 1. As described above, prior to the electroforming process, By performing surface activation treatment on the exposed surface, the adhesion between the substrate 1 and the electrodeposition layer has been improved in advance, so that it is possible to effectively prevent the electrode layer 2b from falling off and rising during connection, and the manufacturing process. The defective product formation rate can be reduced.

次いで基板1上の半導体素子S搭載部分を、図3(c)のごとく熱硬化性エポキシ樹脂等の樹脂層4でモールドし、基板1上に樹脂封止体を形成する。具体的には基板1一面側をモールド金型(上型)に装着するともに、モールド金型内にエポキシ樹脂をキャビティにより圧入するもので、基板1上に並列して形成した、複数組の半導体素子搭載部が樹脂層4により連続して封止された形態となる。この場合基板1自体が樹脂モールド時における下型の機能を果たす。なお、モールド時に複数の基板1を並列に配置して、エポキシ樹脂をライナを通して各基板1と上金型との間に圧入するようにすれば、効率良く多数の樹脂封止を行うことが可能である。   Next, the semiconductor element S mounting portion on the substrate 1 is molded with a resin layer 4 such as a thermosetting epoxy resin as shown in FIG. 3C to form a resin sealing body on the substrate 1. Specifically, a plurality of sets of semiconductors are formed in parallel on the substrate 1 by mounting one side of the substrate 1 to a mold die (upper die) and pressing an epoxy resin into the mold die through a cavity. The element mounting portion is continuously sealed by the resin layer 4. In this case, the substrate 1 itself functions as a lower mold during resin molding. If a plurality of substrates 1 are arranged in parallel at the time of molding and an epoxy resin is press-fitted between each substrate 1 and the upper mold through a liner, a large number of resins can be sealed efficiently. It is.

次いで、図3(d)のごとく、樹脂封止体から基板1を除去することにより、樹脂封止体の底面には複数組の金属層2aと電極層2bの各裏面が露出するとともに、金属層2a,電極層2bの各裏面と樹脂層4の底面は略同一平面となっている。ここで、上記のごとく金属層2aおよび電極層2bの周縁に張り出し部11,11を形成しておけば、後工程の樹脂層4による樹脂封止状態において、図1のごとく樹脂層4は各張り出し部11,11がくい込み状に位置した状態で硬化しているため、この喰い付き効果により、樹脂封止体からの基板1の剥離作業時に基板1を引き剥がし除去する際、金属層2aおよび電極層2bは樹脂層4側に確実に残留し、基板1とともにくっついて引き離されることはなく、ズレや欠落等が効果的に防止でき、製造工程時の歩留まりが向上する。
上記基板1を除去する方法としては、樹脂封止体から基板1を引き剥がす等強制的に剥離除去する方法の他、例えば基板1等を構成する材質に応じては、樹脂封止体側への影響のない溶剤等により基板1を溶解して除去する方法も含まれるものである。なお、本工程後必要に応じて、各電極層2bあるいは電極層2bと金属層2aの裏面のみに実装用に金,銀等の導電性金層の薄膜をフラッシュメッキ等の周知の方法により、0.3〜0.5μm厚で形成するようにしても良い。
Next, as shown in FIG. 3D, by removing the substrate 1 from the resin sealing body, the back surfaces of the plurality of sets of metal layers 2a and electrode layers 2b are exposed on the bottom surface of the resin sealing body, and the metal The back surfaces of the layer 2a and the electrode layer 2b and the bottom surface of the resin layer 4 are substantially in the same plane. Here, if the overhanging portions 11 and 11 are formed on the peripheral edges of the metal layer 2a and the electrode layer 2b as described above, the resin layer 4 can be separated into the resin layer 4 as shown in FIG. Since the overhanging portions 11 and 11 are hardened in a state of being bitten, the metal layer 2a and the metal layer 2a are removed when the substrate 1 is peeled off during the peeling operation of the substrate 1 from the resin sealing body. The electrode layer 2b reliably remains on the resin layer 4 side and does not stick to and separate from the substrate 1, and can be effectively prevented from being displaced or missing, thereby improving the yield during the manufacturing process.
As a method for removing the substrate 1, in addition to a method for forcibly peeling and removing the substrate 1 from the resin sealing body, for example, depending on the material constituting the substrate 1, A method of dissolving and removing the substrate 1 with an unaffected solvent or the like is also included. In addition, if necessary after this step, a thin film of a conductive gold layer such as gold or silver is mounted on only the back surface of each electrode layer 2b or the electrode layer 2b and the metal layer 2a by a known method such as flash plating. You may make it form by 0.3-0.5 micrometer thickness.

次いで、図3(e)のごとく樹脂封止体を切断線X−Xに沿って1つの半導体素子の対毎に切断して切り離すダイシングの工程を経て、個々の樹脂封止体すなわち図1に示す半導体装置が完成するものである。   Next, as shown in FIG. 3 (e), the resin sealing body is cut along a cutting line XX for each pair of semiconductor elements and separated into individual resin sealing bodies, that is, in FIG. The semiconductor device shown is completed.

以上のような構成を持つ半導体装置によれば、特に、特有の庇形状を持つ張り出し部11の存在により、金属層2aおよび電極層2bの裏面側の樹脂層4との微細な隙間から侵入する水分等が庇状の張り出し部11により阻止され、上方部すなわち結線部分や半導体素子搭載部分への侵入を阻止する効果もあり、半導体素子Sやワイヤとの結線個所への耐水性も向上する。さらに、完成した半導体装置自体の信頼性についても、金属層2a並びに電極層2bの各々の上端部周縁の張り出し部11,11が樹脂層4に対してくい込み状に配された状態にあり、金属層2a及び電極層2bと樹脂層4との密着強度が格段に向上し、樹脂剥れやズレ等の不良が生じることなく、品質を向上させることができるものである。   According to the semiconductor device having the above-described configuration, in particular, due to the presence of the overhanging portion 11 having a specific ridge shape, the semiconductor device enters from a minute gap between the metal layer 2a and the resin layer 4 on the back surface side of the electrode layer 2b. Moisture or the like is blocked by the bowl-shaped overhanging portion 11 and has an effect of preventing entry into the upper portion, that is, the connection portion or the semiconductor element mounting portion, and the water resistance to the connection portion with the semiconductor element S or the wire is improved. Further, regarding the reliability of the completed semiconductor device itself, the protruding portions 11 and 11 at the periphery of the upper end of each of the metal layer 2a and the electrode layer 2b are arranged in a state of biting into the resin layer 4, The adhesion strength between the layer 2a and the electrode layer 2b and the resin layer 4 is remarkably improved, and the quality can be improved without causing defects such as resin peeling and displacement.

なお、各張り出し部11については、出願人において実験により検証した結果、長さTはレジストパターン層6の厚みを越えてオーバーハングさせる高さに略比例して成長するものであり、その長さTが5μm以下だとモールド時の樹脂層4に対する喰い付き効果が弱く、基板1の引き剥がしの際、基板1側に若干ではあるが金属層2aおよび電極層2bがくっついて引き離され、ズレや欠落を生じる現象が見受けられるため、これ以上の長さに設定することが好ましく、また20μmを越えると電着工程後のレジストパターン層6の除去の際、アルカリ溶剤
によるレジストパターン層6の膨潤除去時に膨潤したレジストパターン層6が張り出し部11,11を介して電着金属(金属層2a,電極層2b)を基板1から浮き上がらせてしまう虞れがあるため、これらの点を考慮して5〜20μmの範囲内に設定することが好ましい。
In addition, as for each overhang | projection part 11, as a result of having verified by experiment by the applicant, length T grows substantially in proportion to the height which overhangs exceeding the thickness of the resist pattern layer 6, The length When T is 5 μm or less, the biting effect on the resin layer 4 at the time of molding is weak, and when the substrate 1 is peeled off, the metal layer 2a and the electrode layer 2b are slightly adhered to and separated from the substrate 1 side. It is preferable to set the length longer than this because there is a phenomenon of missing. When the thickness exceeds 20 μm, the resist pattern layer 6 is swelled and removed by an alkaline solvent when the resist pattern layer 6 is removed after the electrodeposition step. There is a possibility that the resist pattern layer 6 swollen sometimes floats the electrodeposited metal (metal layer 2a, electrode layer 2b) from the substrate 1 through the overhanging portions 11 and 11. Therefore, in view of these points, it is preferable to set within a range of 5 to 20 μm.

(他の実施例)
なお、樹脂封止した際、金属層2a及び電極層2b裏面のいずれか一方もしくは両方を、樹脂層4の裏面よりも若干突出させるように構成することも可能である。また、金属層2aや電極層2b等の裏面には、フラッシュメッキ等の方法により、金や銀等を薄膜形成しても良い。さらには、金属層2a及び電極層2b裏面について、樹脂層4の裏面よりも若干凹入させるごとく構成することも可能である。
(Other examples)
It should be noted that when the resin is sealed, either one or both of the metal layer 2a and the back surface of the electrode layer 2b may be configured to protrude slightly from the back surface of the resin layer 4. Further, gold, silver, or the like may be formed on the back surface of the metal layer 2a, the electrode layer 2b, or the like by a method such as flash plating. Further, the back surfaces of the metal layer 2a and the electrode layer 2b can be configured to be slightly recessed from the back surface of the resin layer 4.

(a)は、本発明の半導体装置の一実施例を示す断面図,(b)はその裏面図である。(A) is sectional drawing which shows one Example of the semiconductor device of this invention, (b) is the back view. (a)乃至(e)は、本発明の第1実施例に示す半導体装置の製造方法を説明する断面図である。(A) thru | or (e) is sectional drawing explaining the manufacturing method of the semiconductor device shown in 1st Example of this invention. (a)乃至(e)は、図2(e)に続く半導体装置の製造方法を説明する断面図である。(A) thru | or (e) is sectional drawing explaining the manufacturing method of the semiconductor device following FIG.2 (e). 図2(d)のA−A部分を拡大した断面図(一部拡大図)である。It is sectional drawing (partially enlarged view) which expanded the AA part of FIG.2 (d). 図2(e)のB−B部分を拡大した断面図(一部拡大図)である。It is sectional drawing (partially enlarged view) which expanded the BB part of FIG.2 (e).

符号の説明Explanation of symbols

1 基板
2a 金属層
2b 電極層
4 樹脂層
6 レジストパターン層
S 半導体素子
DESCRIPTION OF SYMBOLS 1 Board | substrate 2a Metal layer 2b Electrode layer 4 Resin layer 6 Resist pattern layer S Semiconductor element

Claims (1)

半導体素子Sが搭載される金属層2aと、該金属層2aの周りに所定の間隔をおいて配置される1以上の電極層2bと、上記金属層2a上に搭載した半導体素子Sと電極層2bとを、ワイヤーボンディング等の方法で電気的に接続した状態で樹脂封止して、金属層2aと電極層2bの各裏面を樹脂層4の底面から露出して形成した半導体装置において、樹脂封止される上記金属層2a及び電極層2b各々の上端部周縁を、庇状に張り出し形成して構成したことを特徴とする半導体装置。   A metal layer 2a on which the semiconductor element S is mounted, one or more electrode layers 2b disposed around the metal layer 2a at a predetermined interval, and a semiconductor element S and an electrode layer mounted on the metal layer 2a In a semiconductor device in which resin 2 is sealed in a state where it is electrically connected by a method such as wire bonding, and the back surfaces of the metal layer 2a and the electrode layer 2b are exposed from the bottom surface of the resin layer 4. A semiconductor device characterized in that the upper edge of each of the metal layer 2a and the electrode layer 2b to be sealed is formed so as to project in a bowl shape.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040689A (en) * 2008-08-04 2010-02-18 Taiyo Yuden Co Ltd Circuit module and method of manufacturing circuit module
JP2015070262A (en) * 2013-09-27 2015-04-13 旭徳科技股▲ふん▼有限公司 Package carrier and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040689A (en) * 2008-08-04 2010-02-18 Taiyo Yuden Co Ltd Circuit module and method of manufacturing circuit module
JP2015070262A (en) * 2013-09-27 2015-04-13 旭徳科技股▲ふん▼有限公司 Package carrier and manufacturing method thereof
US9236364B2 (en) 2013-09-27 2016-01-12 Subtron Technology Co., Ltd. Package carrier and manufacturing method thereof

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