JP2006237440A - Semiconductor device dummy pattern placement method, dummy pattern placement program, and dummy pattern placement device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a treatment of inserting a dummy pattern into a chip through a less number of processes, which is used for improving a manufacturing yield in a case wherein CMP (chemical mechanical polishing) that is one of techniques of manufacturing a semiconductor integrated circuit is carried out. <P>SOLUTION: In a layout processing unit 102, a prescribed dummy pattern that is inserted and a virtual adjusting dummy pattern used for performing a fine adjustment to the prescribed dummy pattern are formed through a dummy pattern forming processor 111 and an adjusting dummy pattern forming processor 112 respectively, based on an area factor obtained through a high-speed area factor analysis processing unit 110. Mask data 105 into which the prescribed pattern is inserted are analyzed through a high-accuracy area factor analysis processor 117 in a dummy pattern adjustment processor 106. Furthermore, an area factor violation is judged, and an adjusting dummy pattern is successively replaced through a dummy pattern selection processor 119 until an area factor rule is satisfied. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a dummy pattern placement method for a semiconductor device, a dummy pattern placement program, and a dummy pattern placement device that determine the placement of a dummy pattern when designing a semiconductor integrated circuit.

  In recent years, there is a technique called CMP (Chemical Mechanical Polishing) as one of manufacturing techniques for semiconductor integrated circuits. This is a technique that improves the yield by polishing the wafer surface in the process of manufacturing a semiconductor integrated circuit, thereby making the thickness of the wafer uniform, and increasing the manufacturing accuracy during exposure. However, when the area occupied by different materials such as wiring (conductor) and insulator is non-uniform, for example, when the density of the wiring area is extreme, the non-uniformity of the wafer surface thickness is induced by CMP. On the contrary, this is a factor that lowers the manufacturing yield. For this reason, it is common to arrange redundant wirings in empty areas where there are no signal wirings or power supply wirings to prevent the wiring areas from becoming dense. This redundant wiring is called a dummy pattern (dummy metal, filler metal, etc.). Previously, this dummy pattern was generally generated in a post-processing step of the manufacturing process. This dummy pattern insertion technique is described in Patent Document 1, for example.

  However, with the recent miniaturization of the process, the inter-wiring capacitance exerted by the dummy pattern can no longer be ignored, and it has become necessary to perform timing analysis and signal integrity analysis in consideration of the dummy pattern. Therefore, a technique for inserting a dummy pattern with an automatic layout tool is becoming widespread. This technology is described in Non-Patent Document 1, for example.

In general, an index of how much a dummy pattern should be inserted is represented by a numerical value called area ratio (aperture ratio). In the automatic layout tool, a dummy pattern is inserted so as to satisfy the area ratio rule.
JP 2003-28269 A S. Raghvendra (Synopsys, Inc., USA), “Integrating design and exposure tools to improve yield and cost”, Nikkei Microdevices September 2003 issue (Nikkei BP), p. 46-51

  However, the analysis of the area ratio with the automatic layout tool gives priority to the processing speed, and is therefore less accurate than the area ratio analysis with the mask verification tool. Therefore, even though the dummy pattern is generated in consideration of the area ratio by the automatic layout tool, the case where the area ratio rule is not actually satisfied and an error occurs in the mask verification is becoming apparent. As a result, the dummy pattern needs to be additionally inserted again, and the man-hour for satisfying the area ratio rule increases.

  The present invention solves the above-described problems, and its object is to perform a high-accuracy area ratio analysis equivalent to the mask verification level on the generated dummy pattern at the dummy pattern placement stage, and to determine the area after the layout is completed. It is to reduce the man-hours for satisfying the area ratio by preventing the occurrence of a defect in the ratio and preventing the return to the process of correcting the area of the dummy pattern and inserting it again.

  In order to achieve the above object, in the present invention, first, a predetermined dummy pattern is generated so as to satisfy an area ratio rule based on an area ratio analysis with a predetermined accuracy, and multiple steps are performed based on the predetermined dummy pattern. If the predetermined dummy pattern does not satisfy the area ratio rule, a plurality of dummy patterns for adjustment with the area changed are generated, and an area ratio analysis with high accuracy is performed. A dummy pattern for adjustment is selected from among the dummy patterns and replaced to finely adjust the area of the dummy pattern, and the dummy pattern that satisfies the area ratio rule with high accuracy is arranged.

  That is, the dummy pattern placement method for a semiconductor device according to claim 1 is a dummy by redundant wiring for satisfying an area ratio rule which is a standard for reducing the deviation of the area occupied by the wiring with respect to the layout of the semiconductor device. In a dummy pattern placement method for a semiconductor device in which a pattern is automatically placed by a computer, a dummy pattern generation step for generating a predetermined dummy pattern for each predetermined region, and a reference for the predetermined dummy pattern for each predetermined region As an adjustment dummy pattern generation step for generating a plurality of adjustment dummy patterns that are changed in multiple stages at predetermined intervals in association with the predetermined dummy patterns, and for each predetermined region, In order to adapt each of the predetermined dummy patterns to the area ratio rule, A dummy pattern selection step of sequentially selecting and replacing the adjustment dummy pattern from one related dummy pattern group including the me pattern and the plurality of adjustment dummy patterns based on the predetermined dummy pattern. It is characterized by including.

  According to a second aspect of the present invention, in the dummy pattern placement method for a semiconductor device according to the first aspect, a predetermined area ratio is calculated for each of the predetermined regions in the layout of each layer before the predetermined dummy pattern is placed. A predetermined area ratio analyzing step for analyzing the suitability of the predetermined area ratio with respect to the area ratio rule, and each layer in which one adjustment dummy pattern of the one related dummy pattern group is arranged A high-accuracy area ratio analysis step for calculating an area ratio with higher accuracy than the predetermined area ratio for each of the predetermined regions in the layout, and analyzing the suitability of the high-precision area ratio with respect to the area ratio rule; The dummy pattern generation step generates the predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio, and In the pattern selection process, when the high-precision area ratio is lower than the area ratio defined in the area ratio rule, the area is reduced by one step from the one related dummy pattern group at the predetermined interval. The large adjustment dummy pattern is sequentially selected and replaced for adjustment.

  According to a third aspect of the present invention, in the dummy pattern placement method for a semiconductor device according to the first aspect, a predetermined area ratio is calculated for each of the predetermined regions in the layout of each layer before the predetermined dummy pattern is placed. A predetermined area ratio analyzing step for analyzing the suitability of the predetermined area ratio with respect to the area ratio rule, and each layer in which one adjustment dummy pattern of the one related dummy pattern group is arranged A high-accuracy area ratio analysis step for calculating an area ratio with higher accuracy than the predetermined area ratio for each of the predetermined regions in the layout, and analyzing the suitability of the high-precision area ratio with respect to the area ratio rule; The dummy pattern generation step generates the predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio, and In the pattern selection process, when the high-accuracy area ratio exceeds the area ratio defined in the area ratio rule, an area corresponding to one step at the predetermined interval is selected from the one related dummy pattern group. The small adjustment dummy patterns are selected and replaced sequentially for adjustment.

  According to a fourth aspect of the present invention, in the dummy pattern placement method for a semiconductor device according to the first aspect, a predetermined area ratio is calculated for each of the predetermined regions in the layout of each layer before the predetermined dummy pattern is placed. A predetermined area ratio analyzing step for analyzing the suitability of the predetermined area ratio with respect to the area ratio rule, and each layer in which one adjustment dummy pattern of the one related dummy pattern group is arranged A high-accuracy area ratio analysis step for calculating an area ratio with higher accuracy than the predetermined area ratio for each of the predetermined regions in the layout, and analyzing the suitability of the high-precision area ratio with respect to the area ratio rule; The dummy pattern generation step generates the predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio, and In the pattern selection process, when the high-precision area ratio is lower than the area ratio defined in the area ratio rule, the area is reduced by one step from the one related dummy pattern group at the predetermined interval. When the large adjustment dummy pattern is selected and replaced sequentially for adjustment, and the high-accuracy area ratio obtained by the high-accuracy area ratio analysis step exceeds the area ratio defined in the area ratio rule The adjustment dummy patterns having a small area by one step at the predetermined interval are sequentially selected and replaced from the one related dummy pattern group for adjustment.

  According to a fifth aspect of the present invention, in the method for placing a dummy pattern of a semiconductor device according to the first aspect, the design for analyzing each of the plurality of adjustment dummy patterns generated in the adjustment dummy pattern generation step according to a design rule. A rule analysis step, and if there is a design rule violation in the design rule analysis step, a design rule violation correction step for correcting a dummy pattern that has violated the design rule or a layout pattern located around the dummy pattern; And the area of the plurality of adjustment dummy patterns is the largest among the plurality of adjustment dummy patterns based on each of the predetermined dummy patterns generated in the dummy pattern generation step for each predetermined region of the layout of each layer. Even for dummy patterns, The said in-rule analyzing step design rule violation correcting step, characterized by arranging the adjustment dummy pattern so as to satisfy the design rule.

  According to a sixth aspect of the present invention, in the dummy pattern placement method according to the first aspect, the design rule analyzing step of analyzing each of the plurality of adjustment dummy patterns generated in the adjustment dummy pattern generation step in accordance with a design rule. And when there is a design rule violation in the design rule analysis step, a dummy rule that has violated the design rule or a design rule violation correction step that corrects a layout pattern located around the dummy pattern, A dummy pattern having the smallest area among the plurality of adjustment dummy patterns based on each of the predetermined dummy patterns generated in the dummy pattern generation step for each predetermined region of the layout of each layer. Even for the above design rules The said the analysis process design rule violation correcting step, characterized by arranging the adjustment dummy pattern so as to satisfy the design rule.

  According to a seventh aspect of the invention, in the dummy pattern placement method for a semiconductor device according to the fifth or sixth aspect, the adjustment dummy pattern generation step includes the design rule analysis step and the design rule violation correction step. Features.

  According to an eighth aspect of the present invention, in the dummy pattern placement method for a semiconductor device according to the second aspect, the dummy pattern selecting step has a maximum area among the plurality of adjustment dummy patterns based on the predetermined dummy pattern. Even if the dummy pattern is selected, if the area ratio is lower than the area ratio set in the area ratio rule, the predetermined dummy pattern among the plurality of adjustment dummy patterns based on the predetermined dummy pattern for the other predetermined area is selected. The adjustment dummy pattern having a large area by one step at intervals is sequentially selected and replaced for adjustment, and the high-precision area ratio analysis step and the dummy pattern selection step are alternately performed until the area ratio rule is satisfied. It is characterized by repetition.

  According to a ninth aspect of the present invention, in the dummy pattern placement method for a semiconductor device according to the third aspect, the dummy pattern selection step has a minimum area among the plurality of adjustment dummy patterns based on the predetermined dummy pattern. Even when the dummy pattern is selected, if the area ratio exceeds the area ratio defined in the area ratio rule, the predetermined dummy pattern among the plurality of adjustment dummy patterns based on the predetermined dummy pattern for the other predetermined area is selected. The adjustment dummy pattern having a small area by one step at intervals is sequentially selected and replaced for adjustment, and the high-precision area rate analysis step and the dummy pattern selection step are alternately performed until the area rate rule is satisfied. It is characterized by repetition.

  According to a tenth aspect of the present invention, in the dummy pattern placement method for a semiconductor device according to the first aspect, the method includes a pattern number designating step of designating the number of the plurality of dummy patterns based on one predetermined dummy pattern. It is characterized by.

  According to a eleventh aspect of the present invention, in the dummy pattern placement method for a semiconductor device according to the first aspect, a size designating step of designating a size of each of the plurality of dummy patterns based on one predetermined dummy pattern. It is characterized by including.

  According to a twelfth aspect of the present invention, the dummy pattern placement method for a semiconductor device according to the first aspect includes a shape designating step of designating the shapes of the plurality of dummy patterns based on one predetermined dummy pattern. Features.

  According to a thirteenth aspect of the present invention, in the dummy pattern placement method for a semiconductor device according to the first aspect, after the area ratio rule is satisfied, all dummy patterns other than one dummy pattern satisfying the area ratio rule are deleted. And an unnecessary dummy pattern information deleting process step.

  According to a fourteenth aspect of the present invention, there is provided a dummy pattern placement program for a semiconductor device in which dummy wiring by a redundant wiring for satisfying an area ratio rule which is a standard for reducing the deviation of the area occupied by wiring with respect to the layout of the semiconductor device A dummy pattern placement program for a semiconductor device for automatically placing a pattern by a computer, calculating a predetermined area ratio for each predetermined region with respect to a layout of each layer, and applying the predetermined area ratio to the area ratio rule A predetermined area ratio analyzing step for analyzing the characteristics, a dummy pattern generating step for generating a predetermined dummy pattern for each of the predetermined regions so as to satisfy the area ratio rule based on the predetermined area ratio, For each predetermined region, the size of the area is changed in multiple steps at predetermined intervals with reference to the predetermined dummy pattern. An adjustment dummy pattern generation step for generating the plurality of adjustment dummy patterns in association with the predetermined dummy patterns, and a higher accuracy than the predetermined area ratio for each predetermined region of the layout of each layer A high accuracy area ratio analysis step for calculating an area ratio and analyzing the suitability of the high accuracy area ratio for the area ratio rule, and the plurality of adjustments based on the predetermined dummy pattern or the predetermined dummy pattern An area rate determination step for determining whether an analysis result of the high-precision area rate analysis step satisfies the area rate rule for one of the dummy patterns for use, and a determination result by the area rate determination step is the area rate A dummy that selects one other dummy pattern for adjustment from the plurality of adjustment dummy patterns when the rule is not satisfied The process consisting of a turn selection step and the high-precision area rate analysis step and the dummy pattern selection step are alternately performed until the plurality of adjustment dummy patterns selected for adjustment satisfy the area rate rule. A process comprising: an iterative process and an unnecessary dummy pattern information deletion process that deletes data other than the dummy pattern that satisfies the area ratio rule when the determination result of the area ratio determination process satisfies the area ratio rule. It is characterized by having a computer perform.

  According to a fifteenth aspect of the present invention, there is provided a dummy pattern placement device for a semiconductor device, comprising: a dummy with redundant wiring for satisfying an area ratio rule which is a standard for reducing the deviation of the area occupied by the wiring with respect to the layout of the semiconductor device. In a dummy pattern placement device of a semiconductor device for placing a pattern, a predetermined area for calculating a predetermined area ratio for each predetermined region of each layer layout and analyzing the suitability of the predetermined area ratio for the area ratio rule A rate analysis unit, a dummy pattern generation unit that generates a predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio for each of the predetermined regions, and for each of the predetermined regions A plurality of adjustment dummy patterns, in which the size of the area is changed in multiple stages at predetermined intervals, with the predetermined dummy pattern as a reference, A dummy pattern generator for adjustment that is generated in association with each dummy pattern, and an area ratio that is more accurate than the predetermined area ratio for each of the predetermined areas of the layout data of each layer, On the other hand, the high-precision area ratio analysis unit that analyzes the high-precision area ratio, and the high-precision area ratio of the predetermined dummy pattern or one of the plurality of adjustment dummy patterns based on the predetermined dummy pattern An area rate determination unit that determines whether the analysis result of the area rate analysis unit satisfies the area rate rule; and the determination result by the area rate determination unit does not satisfy the area rate rule. A dummy pattern selection unit that selects one other dummy pattern for adjustment from among the dummy patterns, and the determination result by the area ratio determination unit is If it meets the area ratio rule, characterized by comprising a unnecessary dummy pattern information deletion section for deleting the data other than the dummy pattern satisfying the area ratio rule.

  According to a sixteenth aspect of the present invention, in the dummy pattern placement device for a semiconductor device according to the fifteenth aspect, the adjustment dummy pattern generation unit is configured to store the plurality of adjustment dummy patterns based on one predetermined dummy pattern. A pattern designating unit for designating a number is provided.

  According to a seventeenth aspect of the present invention, in the dummy pattern placement device for a semiconductor device according to the fifteenth aspect, the adjustment dummy pattern generation unit includes a plurality of adjustment dummy patterns based on one predetermined dummy pattern. A size designating unit for designating each size is provided.

  According to an eighteenth aspect of the present invention, in the dummy pattern placement device for a semiconductor device according to the fifteenth aspect, the adjustment dummy pattern generation unit includes a plurality of adjustment dummy patterns based on one predetermined dummy pattern. It is characterized by comprising shape designating means for designating the shape.

  As described above, according to the first aspect of the present invention, first, in the dummy pattern generation step, a predetermined dummy pattern is generated based on a predetermined dummy pattern so as to satisfy the area ratio rule based on an area ratio analysis with a predetermined accuracy. In order to adjust the area ratio based on the pattern, in the adjustment dummy pattern generation process, a plurality of adjustment dummy patterns having a plurality of sizes are changed in multiple steps with reference to one predetermined dummy pattern. By generating and selecting one of the plurality of patterns in the dummy pattern selection step, a highly accurate dummy pattern can be generated, thus preventing detection of an area ratio defect after layout creation. By eliminating the backtracking to the layout process caused by the area ratio defect, the dummy pattern is inserted and the area ratio rule It is possible to reduce the total man-hours to satisfy.

  In the invention described in claims 2 to 4, the predetermined dummy pattern is generated based on a predetermined area ratio obtained by an area ratio analysis step with a predetermined accuracy, and more accurately than the predetermined area ratio analysis step. As a result of the analysis based on the high-accuracy area ratio calculated by the area ratio analysis process, if the area ratio rule is not met, one of the plurality of adjustment dummy patterns generated by the adjustment dummy pattern generation process is 1 The fine adjustment of the area ratio is added by selecting one dummy pattern whose area has changed by the level. As described above, since the layout satisfying the area ratio rule can be realized with high accuracy by arranging the dummy pattern, it is possible to prevent the area ratio defect from being detected after the layout is created, and to the layout process that causes the area ratio defect. By eliminating the backtracking, the total man-hours for inserting the dummy pattern and satisfying the area ratio rule can be reduced.

  In the invention according to claim 5, even when a pattern is selected in which all dummy patterns for each predetermined region are maximized, for example, a design rule such as a spacing constraint or a maximum area constraint is violated. By arranging dummy patterns so that design rules and area ratios are considered at the same time in the dummy pattern placement stage, it is possible to prevent area ratio defects from being detected after layout creation and cause area ratio defects. By eliminating the return to the layout step, the total man-hour for inserting the dummy pattern and satisfying the area ratio rule can be reduced.

  In the invention described in claim 6, even when all the dummy patterns are selected so as to be minimum, for example, the dummy patterns are set so as not to violate design rules such as spacing constraints and minimum area constraints. Since the design rule and area ratio are considered at the same time in the dummy pattern placement stage, it is possible to prevent the area ratio defect from being detected after the layout is created, and to the layout process that causes the area ratio defect. By eliminating the backtracking, it is possible to reduce the total man-hour for inserting the dummy pattern and satisfying the area ratio rule.

  In the invention according to claim 7, even when a pattern is selected such that all dummy patterns for each predetermined region are maximum or minimum, for example, design rules such as spacing constraints and maximum area constraints. By arranging dummy patterns so that they do not violate, the design rule and area ratio are considered at the same time in the dummy pattern placement stage, so it is possible to prevent area ratio defects from being detected after layout creation and to prevent area ratio defects. By eliminating the backtracking to the layout process caused by this, it is possible to reduce the total man-hour for inserting the dummy pattern and satisfying the area ratio rule.

  In the invention according to claim 8, when the high-accuracy area ratio is lower than the area ratio rule in a certain region as a result of the high-accuracy area-ratio analysis by the high-precision area-ratio analysis step, the area is larger than the dummy pattern in the region. If the pattern is still below the area ratio rule, select a pattern that increases the area occupied by the dummy pattern, and repeat the process until the area ratio rule is satisfied. In order to satisfy the area ratio rule by inserting a dummy pattern by preventing the area ratio defect from being detected after layout creation and eliminating the backtrack to the layout process caused by the area ratio defect Total man-hours can be reduced.

  In a ninth aspect of the invention, as a result of the high-precision area ratio analysis by the high-precision area ratio analysis step, if the high-precision area ratio exceeds the area-rate rule in a certain area, it becomes smaller than the dummy pattern in the area. If the pattern is still below the area rate rule, the pattern occupied by the dummy pattern is further reduced, and the process is repeated until the area rate rule is satisfied. Therefore, it is possible to prevent the area ratio defect from being detected after the layout is created, and to eliminate the return to the layout process caused by the area ratio defect. Man-hours can be reduced.

  In the invention according to claim 10, since the level of area ratio analysis accuracy can be specified by specifying in advance the number of adjustment dummy patterns possessed by one predetermined dummy pattern, the dummy pattern can be arranged with high accuracy. The total man-hours required to satisfy the area ratio rule by inserting a dummy pattern by eliminating the return to the layout process caused by the area ratio defect without detecting the area ratio defect after layout creation Can be reduced.

  According to the invention of claim 11, the level of area ratio analysis accuracy is specified by specifying in advance the size of the adjustment dummy pattern that one predetermined dummy pattern has, that is, the amount of area difference between the adjustment dummy patterns. Therefore, dummy patterns can be placed with high accuracy, and after the layout is created, the area ratio defect is not detected, and the dummy pattern is eliminated by returning to the layout process caused by the area ratio defect. It is possible to reduce the total man-hours for satisfying the area ratio rule by inserting.

  In the twelfth aspect of the invention, the level of area ratio analysis accuracy is designated by designating in advance the shape of the adjustment dummy pattern possessed by one predetermined dummy pattern, that is, the amount of change in shape between the adjustment dummy patterns. Therefore, the dummy pattern can be placed with high accuracy, and the dummy pattern can be inserted by eliminating the return to the layout process caused by the defective area ratio without detecting the defective area ratio after layout creation. Thus, the total man-hours for satisfying the area ratio rule can be reduced.

  In the invention described in claim 13, after the area ratio rule is satisfied, unnecessary dummy pattern information is deleted from the mask data and only the actual dummy pattern is set, so that the handling of data can be simplified. .

  According to the fourteenth to eighteenth aspects of the present invention, first, a predetermined dummy pattern is generated so as to satisfy the area ratio rule based on an area ratio analysis with a predetermined accuracy, and the area ratio can be adjusted based on the predetermined dummy pattern. As described above, on the basis of one predetermined dummy pattern, dummy patterns having a plurality of sizes are generated with a hierarchical data structure in multiple stages, and one of the plurality of patterns having a hierarchical structure is selected. By doing so, it is possible to place dummy patterns with high accuracy, so that it is possible to prevent a failure in the area ratio after the layout is created, and to eliminate the backtrack to the layout process caused by the failure in the area ratio, The total man-hour for inserting the dummy pattern to satisfy the area ratio rule can be reduced.

  As described above, according to the inventions according to claims 1 to 18, dummy pattern placement is performed with high accuracy by overlapping area ratio analysis with different accuracy, so that the yield can be improved in designing a semiconductor integrated circuit. This makes it possible to suppress the backtracking of the design related to the dummy pattern insertion, which is the technique of No. 1, and to reduce the man-hours for satisfying the area ratio rule, thereby shortening the design period of the semiconductor integrated circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, the overall flow will be described in sequence with reference to the configuration diagram of FIG.

  Layout data 101 to be inserted with a dummy pattern is input to the layout processing unit 102. At this time, the layout data and each processing result during the layout process are stored in the data storage device 103, and the processing program is stored in the program storage device 104. After the processing of the layout processing unit 102, mask data 105 into which a dummy pattern is inserted is output.

  Subsequently, the mask data 105 to be subjected to dummy pattern adjustment is input to the dummy pattern adjustment processing unit 106. At this time, the mask data and each processing result during the dummy pattern processing are stored in the data storage device 107, and the processing program is stored in the program storage device 108. After the processing by the dummy pattern adjustment processing unit 106, mask data 109 in which the dummy pattern is adjusted is output. This mask data 109 satisfies the area ratio rule with high accuracy. The above processing of the layout processing unit 102 and the dummy pattern adjustment processing unit 106 is performed by an arithmetic processing unit of a computer.

  Next, the layout processing unit 102 will be described in detail.

  First, the layout data 101 is input to a high-speed area ratio analysis processing unit 110 that executes a process of performing an area ratio analysis process at a high speed (a predetermined area ratio analysis process). The area ratio analysis at this time has low accuracy because of speed priority. In this area ratio analysis, an area ratio (predetermined area ratio) is calculated for each region obtained by dividing the layout surface into predetermined regions for each layer of the layout data 101.

  Next, the dummy pattern generation processing unit 111 that executes the process of the dummy pattern generation process will be described with reference to FIG. FIG. 2A shows the arrangement of the normal wiring 202 area, the empty area 203 where no wiring is performed, and the dummy pattern 204 in the area 201 violating the area ratio rule. In the dummy pattern generation processing unit 111, as shown in FIG. 2A, the design rule for satisfying the design rule between the normal wiring 202 and the area 201 that violates the area ratio rule is satisfied. Insert a dummy pattern (predetermined dummy pattern) 204 so as to satisfy the area ratio rule in the vacant region 203 based on the area ratio (predetermined area ratio) while analyzing and correcting the design rule violation using the analysis result To do. For example, when the predetermined area ratio is 20%, the dummy pattern 204 is inserted so that the area ratio is 20% with respect to the region where the area ratio is less than 20%. The inserted dummy pattern 204 is managed using, for example, a table-type database 205 shown in FIG. This table stores identifiers associated with layers, graphic information (graphic positions and sizes), and dummy patterns 204. Hereinafter, the dummy pattern inserted at this stage is referred to as “real dummy pattern”.

  Next, the adjustment dummy pattern generation processing unit 112 that performs the process of the adjustment dummy pattern generation process will be described with reference to FIGS. 3 and 4. FIG. 3A shows an adjustment dummy pattern (one of a plurality of adjustment dummy patterns) 302 in an area 301 that is the same area 201 as shown in FIG. The arrangement when inserted is shown. The adjustment dummy pattern generation processing unit 112 inserts a large adjustment dummy pattern and a small adjustment dummy pattern into the dummy pattern 204 inserted by the dummy pattern generation processing unit 111. FIG. 3A shows an arrangement in which a large adjustment dummy pattern 302 is inserted so as to exceed the area ratio with respect to the dummy pattern 204, and the broken line region shown inside the region occupied by the adjustment dummy pattern 302 is shown in FIG. FIG. 2A shows the area of the dummy pattern 204 in the layer 201 in the area 201 of FIG. 3B, as in FIG. 2B, the layer and graphic information (the position and size of the graphic) are stored as data in which an identifier is associated with each adjustment dummy pattern 302. This is a table format database 303. Here, the same identifier is given to the database 303 so that the dummy pattern 204 and the adjustment dummy pattern 302 form a pair. For example, for the real dummy pattern of layer name 3, on the database 303, information on the virtual dummy pattern having the same identifier is stored in the layer named layer name 3 (+1) having an area ratio that is one step higher than that of layer name 3. The adjustment dummy pattern 302 is distinguished from the dummy pattern 204 inserted by the dummy pattern generation processing unit 111 on the database of the data storage device 103. Thereafter, an adjustment dummy pattern (a plurality of adjustment dummy patterns) 302 which is a dummy pattern inserted at the processing stage of the adjustment dummy pattern generation processing unit 112 and whose area is changed in multiple stages at a predetermined interval. This is called a “virtual dummy pattern” and is distinguished from a real dummy pattern. Also, the number of virtual dummy patterns is called “hierarchy”.

  FIG. 4A shows an example in which an adjustment dummy pattern 302 larger than the dummy pattern 204 is arranged in FIG. 3A, whereas an adjustment dummy pattern 402 smaller than the dummy pattern 204 is arranged. Show. Reference numeral 401 denotes the same area of a different layer with respect to the area 201. FIG. 4A shows an arrangement in which dummy patterns 402 are inserted in the same region 401 so as to fall below the area ratio defined as a rule, and a broken line surrounding the region of the adjustment dummy pattern 402. Indicates the area of the dummy pattern 204 in the layer of the area 201. In the table shown in FIG. 4B, as in FIGS. 2B and 3B, an identifier is assigned for each adjustment dummy pattern 402 with respect to the layer and figure information (position and size of the figure). It is a table format database 403 stored as associated data. Here, the same identifier is given to the database 403 so that the dummy pattern 204 and the adjustment dummy pattern 402 form a pair combination. For example, for the actual real dummy pattern of layer name 3, on the database 403, information on the virtual dummy pattern having the same identifier is stored in the layer named layer name 3 (-1) whose area ratio is one step smaller than that of layer name 3. To do.

  FIG. 3A and FIG. 4A show one example of the hierarchy in the direction in which the area ratio is large and the direction in which the area ratio is small. Actually, it is possible to further deepen the hierarchy. The depth of the hierarchy can be specified by the process of specifying the number of patterns for specifying the number of layers of the adjustment dummy patterns based on the actual dummy pattern, and the ratio of the area of the virtual dummy pattern to the actual dummy pattern Can be designated by a step of designating the size of each adjustment dummy pattern to be set by changing the actual dummy pattern in multiple steps. That is, as shown in FIG. 1, the adjustment dummy pattern generation processing unit 112 includes a pattern number designating circuit (pattern number designating unit) 121 for performing the pattern number designating process and the size designating process, and a size designating process. A circuit (size designation means) 122. For example, if the depth of the hierarchy is 10 and the ratio of the maximum virtual dummy pattern is + 10%, the virtual dummy pattern of layer name 3 (+1) has an area of + 1% compared to the real dummy pattern of layer name 3, The virtual dummy pattern of name 3 (+2) has an area of + 2%, and finally the virtual dummy pattern of layer name 3 (+10) has an area of + 10%. In this case, when adjusting the actual dummy pattern, finer adjustment is possible by finely setting the adjustment width (predetermined interval) of the area occupied by the virtual dummy pattern. On the other hand, when the depth of the hierarchy is specified as 5 and the increment of the virtual dummy pattern is specified by 2%, for example, the area of the virtual dummy pattern of the layer name 3 (+1) is + 2% with respect to the real dummy pattern of the layer name 3 The virtual dummy pattern of layer name 3 (+2) has an area of + 4%, and finally the virtual dummy pattern of layer name 3 (+5) has an area of + 10%. In this case, when adjusting the dummy pattern 204, the adjustment range of the area occupied by the dummy metal can be increased, and the data amount can be saved.

  It is also possible to specify a shape in which the area of the virtual dummy pattern compared with the actual dummy pattern is specified in the area that changes as the hierarchy becomes deeper. In this case, the adjustment dummy pattern generation processing unit 112 includes a shape designation step for designating the shapes of a plurality of adjustment dummy patterns based on the actual dummy pattern. As shown in FIG. 1, the adjustment dummy pattern 112 includes a shape designation circuit (shape designation means) 123 that performs a shape designation process. For example, when the increase / decrease direction is the horizontal axis direction, for example, when the shape of the virtual dummy pattern of layer name 3 (+1) whose area is increased by + 2% is compared with the real dummy pattern of layer name 3, the horizontal axis direction is The area can be increased by + 1% on the right side and + 1% on the left side. Further, when the increase / decrease direction is an upward direction, for example, when comparing the shape of the virtual dummy pattern of the layer name 3 (+1) whose area is increased by + 2% with respect to the real dummy pattern of the layer name 3, Thus, it is possible to set such that the area increases by + 2% on the upper side. The direction can be designated as top, top right, right, bottom right, bottom, bottom left, left, top left, length, width, all directions, and the like.

  The above virtual dummy patterns are generated so that each shape does not violate the design rule. The arrangement of the adjustment dummy patterns that satisfy this design rule will be described next.

  Subsequent to the process of the adjustment dummy pattern generation processing unit 112, a process of analyzing whether the layout in which the adjustment dummy patterns 302, 402, etc. are inserted violates a design rule (design rule analysis process) Analysis processing by the design rule analysis processing unit 113 is executed.

  As a result of the process of the design rule analysis process performed by the design rule analysis processing unit 113, when a location that violates the design rule is found, the design rule violation correction processing unit 114 that subsequently performs the design rule violation correction process The design rule violation is corrected by changing the shape of the normal wiring other than the adjustment dummy patterns 302 and 402 or the adjustment dummy patterns 302 and 402.

  In particular, if the virtual dummy pattern at the deepest level in the positive direction is regarded as a real dummy pattern, and if the virtual dummy pattern at the deepest level in the negative direction is regarded as a real dummy pattern, is the design rule violated? Check if. That is, when there is a design rule violation, the design rule violation correction processing unit 114 causes the dummy pattern having the maximum or minimum area to be satisfied with the maximum or minimum dummy pattern among the virtual dummy patterns. Alternatively, the layout pattern around the dummy pattern is corrected, and the design rule violation is corrected. Thereby, each virtual dummy pattern is generated so as not to violate the design rule.

  Finally, the mask data creation processing unit 115 outputs the layout data into which the adjustment dummy patterns 302 and 402 are inserted as the mask data 105. At this time, similarly to the databases 303 and 403 storing the information of the adjustment dummy patterns 302 and 402, the layer, the graphic information (position and size of the graphic), and the adjustment dummy pattern information are used as the mask data 105. Output. When the mask data 105 is output in accordance with a general GDS format, for example, the dummy pattern information of the layer name 3 on the layout data is assigned to the layer number 33 on the mask data 105 and the layer name 3 ( +1) dummy pattern information is stored in the layer number 131 on the mask data, and identifier information is stored as text information.

  Next, the dummy pattern adjustment processing unit 106 will be described in detail.

  The actual dummy pattern of the mask data 105 obtained by the layout processing unit 102 is a dummy pattern generated by speed-priority area ratio analysis, and a virtual dummy pattern generated based on this actual dummy pattern is used. It is a dummy pattern before correction that needs to be adjusted. This adjustment process is performed by the dummy pattern adjustment processing unit 106 shown below.

  First, the input mask data 105 is read by a mask data reading processing unit 116 that executes a process of reading mask data. Here, FIG. 5 shows a database 501 in which the identifiers of the dummy pattern 204 and the adjustment dummy patterns 302 and 402 generated in the layout processing unit 102 are associated with the hierarchy in which these dummy patterns are used. All the predetermined dummy patterns arranged as the dummy patterns 204 are patterns calculated by the high-speed area ratio analysis processing unit 110 in the layout processing unit 102, but at this stage, they are based on area ratio analysis with low accuracy. It is not yet deterministic and is treated as a virtual dummy pattern with a depth of zero.

  Next, in the high-precision area rate analysis process by the high-precision area rate analysis processing unit 117, the area rate of the mask data 105 input to the dummy pattern adjustment processing unit 106 and read by the mask data reading processing unit 116 is changed. Analysis is performed. This area ratio analysis is more accurate than the area ratio analysis (predetermined area ratio analysis) in the layout processing unit 102. Here, first, the area ratio (highly accurate area ratio) is calculated for each predetermined region for each layer of the mask data.

  Next, in the area ratio determination unit 118, if there is a violation of the area ratio rule in the analysis result of the area ratio calculated by the high accuracy area ratio analysis processing unit 117, one layer is moved from the virtual dummy pattern. Then, the process of adjusting the area ratio (dummy pattern selection process) by selecting an appropriate dummy pattern is performed by the dummy pattern selection processing unit 119, and is unnecessary if there is no violation of the area ratio rule. The unnecessary dummy pattern information deletion processing unit 120 performs the process of deleting the data of the adjustment dummy pattern (unnecessary dummy pattern information deleting process).

  Here, FIG. 6 shows the arrangement of the wiring region 602 and the adjustment dummy patterns 604 and 606 which are virtual dummy patterns in the chip region 601, and is indicated by a broken line inside each of the adjustment dummy patterns 604. A region larger than the region and the adjustment dummy pattern 606 by a broken line is a dummy pattern 204 generated by the dummy pattern generation processing unit 111 of the layout processing unit 102, that is, a region of an actual dummy pattern. Is shown. The area ratio determining unit 118 that determines the area ratio violation considers the wiring 602 other than the dummy pattern for the chip region 601 to be subjected to the area ratio analysis, and performs dummy pattern selection processing when an area ratio violation occurs. The processing is transferred to the unit 119. If no area ratio violation occurs, the process moves to an unnecessary dummy pattern information deletion processing unit 120 that deletes unnecessary dummy pattern information.

  The dummy pattern selection processing unit 119 refers to the database 501 to check the current dummy pattern hierarchy when, for example, the result of high-precision area ratio analysis of a certain area 603 is below the area ratio determined by the rule. From there, the virtual dummy pattern one level deep in the forward direction, that is, the graphic information of the virtual dummy pattern having a larger area than the current virtual dummy pattern is converted as the real dummy pattern 604. This increases the area occupied by the dummy pattern. Then, the database 501 is updated to a database 607. Here, it is useful when the actual wiring distribution is coarser than the result of the area ratio analysis performed by the layout processing unit 102 and the area ratio is estimated to be large.

  Further, for example, when the result of high-accuracy area ratio analysis of a certain area 605 exceeds the area ratio determined by the rules, the database 501 is referenced to check the current dummy pattern hierarchy. From there, the graphic information of the virtual dummy pattern that is one level deeper in the negative direction is converted as a real dummy pattern 606. That is, the area occupied by the dummy pattern is reduced. Then, the database 501 is updated to a database 607. This is useful when the distribution of macros such as memory is expanded and the distribution of wiring becomes dense.

  After the processing by the dummy pattern selection processing unit 119, the high-precision area ratio analysis processing unit 117 performs high-precision area ratio analysis again. A series of processing steps by the high-precision area rate analysis processing unit 117 to the dummy pattern selection processing unit 119 are repeated until the area rate determining unit 118 that determines the area rate does not cause an area rate violation.

  Finally, all unnecessary dummy dummy pattern information is deleted by the unnecessary dummy pattern information deletion processing unit 120, and mask data 109 whose area ratio has been corrected is output. Since the virtual dummy pattern is handled in the data storage device 103 by the layout processing unit 102 and in the data storage device 107 by the dummy pattern adjustment processing unit 106 on the database, the virtual dummy pattern is always distinguished from the real dummy pattern. The search is easily performed and can be realized by a simple process. This completes the creation of the mask data that satisfies the area ratio.

  A series of processing from the mask data reading processing unit 116 to the unnecessary dummy pattern information deletion processing unit 120 in the dummy pattern adjustment processing unit 106 shown in the present embodiment can be included in the processing of the layout tool. It can also be included in the processing of the mask verification tool.

  Further, FIG. 1 shown in the present embodiment explicitly describes the connection of individual processes by the configuration of the high-speed area ratio analysis processing unit 110 to the unnecessary dummy pattern information deletion processing unit 120. Therefore, the adjustment dummy pattern generation processing unit 112 may include a design rule analysis processing unit 113 and a design rule violation correction processing unit 114.

  As described above, the automatic placement of the dummy pattern by the computer is performed for each predetermined region, and the mask data 109 that is finally output has the area ratio analyzed with high accuracy. It does not include defects, and it is possible to reduce the total man-hours for satisfying the area ratio rule because the return to the process of inserting the dummy pattern due to the area ratio defect is suppressed from this stage. Become.

  A dummy pattern placement method, a dummy pattern placement program, and a dummy pattern placement device for a semiconductor device according to the present invention are wasteful for design return to satisfy an area ratio rule with respect to dummy pattern insertion that plays an important role in improving yield. Since the number of steps can be eliminated and the design period of the semiconductor integrated circuit can be shortened, for example, it is useful in automatic layout of a semiconductor integrated circuit having a CMP chemical mechanical polishing process and having to insert a dummy pattern. It is.

It is a block diagram of the dummy pattern arrangement | positioning apparatus in embodiment of this invention. (A) is a layout diagram of wiring areas and dummy patterns in the embodiment of the present invention, and (b) is a diagram showing a database for managing the dummy patterns of (a) in the embodiment of the present invention. (A) In the embodiment of the present invention, a layout diagram showing candidates for a pattern having a large area with respect to the dummy pattern, and (b) shows a database for managing the dummy pattern of (a) in the embodiment of the present invention. FIG. (A) is a layout diagram showing candidates for patterns having a smaller area with respect to the dummy pattern in the embodiment of the present invention, and (b) shows a database for managing the dummy pattern of (a) in the embodiment of the present invention. FIG. It is a figure which shows the database which manages the dummy pattern in embodiment of this invention. (A) is a layout diagram of wiring areas and various dummy patterns in the embodiment of the present invention, and (b) is a diagram showing a database for managing the dummy patterns of (a) in the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Layout data 102 Layout processing part 103, 107 Data storage device 104, 108 Program storage device 105, 109 Mask data 106 Dummy pattern adjustment processing part 121 Pattern number designation circuit (pattern number designation means)
122 Size designation circuit (size designation means)
123 Shape designation circuit (shape designation means)
201, 301
401, 601 Chip area 202, 602 Normal wiring 203 Empty area 204 Actual dummy pattern (predetermined dummy pattern)
205, 303, 403
, 501, 607 Dummy pattern management database 302, 402 Virtual dummy pattern
(Dummy pattern for adjustment)
604, 606 Real dummy pattern
(Dummy pattern for adjustment)
603, 605 Region 110 High-speed area rate analysis processing unit (predetermined area rate analysis unit)
111 dummy pattern generation processing unit 112 adjustment dummy pattern generation processing unit 113 design rule analysis processing unit 114 mask data creation processing unit 116 mask data read processing unit 117 high-precision area rate analysis unit 118 area rate violation determination processing unit 119 dummy pattern selection Processing part (dummy pattern selection part)
120 Unnecessary dummy pattern information deletion processing unit

Claims (18)

In the dummy pattern placement method of a semiconductor device, a dummy pattern by redundant wiring to satisfy an area ratio rule that is a standard for reducing the deviation of the area occupied by the wiring with respect to the layout of the semiconductor device is automatically arranged by a computer.
A dummy pattern generating step for generating a predetermined dummy pattern for each predetermined region;
Adjustment for generating a plurality of adjustment dummy patterns in which the size of an area is changed in multiple steps at predetermined intervals with respect to the predetermined dummy pattern for each of the predetermined regions. Dummy pattern generation process,
In order to adapt the predetermined dummy pattern to the area ratio rule for each of the predetermined regions, one association including the predetermined dummy pattern and the plurality of adjustment dummy patterns based on the predetermined dummy pattern And a dummy pattern selection step of selecting and replacing the adjustment dummy pattern from the dummy pattern group to be sequentially replaced. The method for arranging a dummy pattern of a semiconductor device according to claim 1,
A predetermined area ratio analysis for calculating a predetermined area ratio for each predetermined area of the layout of each layer before arranging the predetermined dummy pattern, and analyzing the suitability of the predetermined area ratio for the area ratio rule Process,
An area ratio with higher accuracy than the predetermined area ratio is calculated for each predetermined area in the layout of each layer in which one adjustment dummy pattern of the one related dummy pattern group is arranged. And a high-accuracy area ratio analysis step for analyzing suitability of the high-accuracy area ratio with respect to the area ratio rule,
The dummy pattern generation step generates the predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio,
In the dummy pattern selection step, when the high-accuracy area ratio is lower than the area ratio defined in the area ratio rule, the dummy pattern selection step is performed by one step at the predetermined interval from the one related dummy pattern group. A dummy pattern arrangement method for a semiconductor device, wherein the adjustment dummy pattern having a large area is sequentially selected and replaced for adjustment. The method for arranging a dummy pattern of a semiconductor device according to claim 1,
A predetermined area ratio analysis for calculating a predetermined area ratio for each predetermined area of the layout of each layer before arranging the predetermined dummy pattern, and analyzing the suitability of the predetermined area ratio for the area ratio rule Process,
An area ratio with higher accuracy than the predetermined area ratio is calculated for each predetermined area in the layout of each layer in which one adjustment dummy pattern of the one related dummy pattern group is arranged. And a high-accuracy area ratio analysis step for analyzing suitability of the high-accuracy area ratio with respect to the area ratio rule,
The dummy pattern generation step generates the predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio,
In the dummy pattern selection step, when the high-accuracy area ratio exceeds the area ratio defined in the area ratio rule, the dummy pattern selection step is performed by one step at the predetermined interval from the one related dummy pattern group. A dummy pattern arrangement method for a semiconductor device, wherein the dummy patterns for adjustment having a small area are sequentially selected and replaced for adjustment. The method for arranging a dummy pattern of a semiconductor device according to claim 1,
A predetermined area ratio analysis for calculating a predetermined area ratio for each predetermined area of the layout of each layer before arranging the predetermined dummy pattern, and analyzing the suitability of the predetermined area ratio for the area ratio rule Process,
An area ratio with higher accuracy than the predetermined area ratio is calculated for each predetermined area in the layout of each layer in which one adjustment dummy pattern of the one related dummy pattern group is arranged. And a high-accuracy area ratio analysis step for analyzing suitability of the high-accuracy area ratio with respect to the area ratio rule,
The dummy pattern generation step generates the predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio,
In the dummy pattern selection step, when the high-accuracy area ratio is lower than the area ratio defined in the area ratio rule, the dummy pattern selection step is performed by one step at the predetermined interval from the one related dummy pattern group. The adjustment dummy pattern having a large area is sequentially selected and replaced for adjustment, and the high-accuracy area ratio obtained by the high-accuracy area-rate analysis step exceeds the area ratio defined in the area-rate rule. In this case, the adjustment dummy pattern having a small area by one step at the predetermined interval is sequentially selected and replaced from the one related dummy pattern group for adjustment. Dummy pattern placement method. The method for arranging a dummy pattern of a semiconductor device according to claim 1,
A design rule analysis step of analyzing each of the plurality of adjustment dummy patterns generated in the adjustment dummy pattern generation step according to a design rule;
If there is a design rule violation in the design rule analysis step, including a dummy pattern that has violated the design rule or a design rule violation correction step for correcting a layout pattern located around the dummy pattern,
A dummy pattern having the largest area among the plurality of adjustment dummy patterns based on each of the predetermined dummy patterns generated in the dummy pattern generation step for each predetermined region of the layout of each layer. In contrast, the dummy pattern placement method for a semiconductor device, wherein the adjustment dummy pattern is placed so as to satisfy the design rule by the design rule analysis step and the design rule violation correction step. In the dummy pattern arrangement method according to claim 1,
A design rule analysis step of analyzing each of the plurality of adjustment dummy patterns generated in the adjustment dummy pattern generation step according to a design rule;
If there is a design rule violation in the design rule analysis step, including a dummy pattern that has violated the design rule or a design rule violation correction step for correcting a layout pattern located around the dummy pattern,
A dummy pattern having the smallest area among the plurality of adjustment dummy patterns based on each of the predetermined dummy patterns generated in the dummy pattern generation step for each predetermined region of the layout of each layer. In contrast, the dummy pattern placement method for a semiconductor device, wherein the adjustment dummy pattern is placed so as to satisfy the design rule by the design rule analysis step and the design rule violation correction step. In the dummy pattern arrangement method of the semiconductor device according to claim 5 or 6,
The adjustment dummy pattern generation step includes the design rule analysis step and the design rule violation correction step. A dummy pattern arrangement method for a semiconductor device, wherein: The method for arranging a dummy pattern of a semiconductor device according to claim 2,
In the dummy pattern selection step, even when selecting the dummy pattern having the largest area among the plurality of adjustment dummy patterns based on the predetermined dummy pattern, when the area ratio is less than the area ratio defined in the area ratio rule, Of the plurality of adjustment dummy patterns based on the predetermined dummy pattern for the other predetermined region, the adjustment dummy pattern having a large area by one step at the predetermined interval is sequentially selected for adjustment. The dummy pattern placement method for a semiconductor device, wherein the high precision area rate analysis step and the dummy pattern selection step are alternately repeated until the area rate rule is satisfied. The dummy pattern placement method for a semiconductor device according to claim 3,
In the dummy pattern selection step, even if the dummy pattern having the smallest area among the plurality of adjustment dummy patterns based on the predetermined dummy pattern is selected, if the area ratio exceeds the area ratio defined in the area ratio rule, Of the plurality of adjustment dummy patterns based on the predetermined dummy pattern for the other predetermined region, the adjustment dummy pattern having a small area by one step at the predetermined interval is sequentially selected for adjustment. The dummy pattern placement method for a semiconductor device, wherein the high accuracy area rate analysis step and the dummy pattern selection step are alternately repeated until the area rate rule is satisfied. The method for arranging a dummy pattern of a semiconductor device according to claim 1,
A dummy pattern arrangement method for a semiconductor device, comprising: a pattern number designating step of designating a number of the plurality of dummy patterns with reference to one predetermined dummy pattern. The method for arranging a dummy pattern of a semiconductor device according to claim 1,
A dummy pattern arranging method for a semiconductor device, comprising: a size specifying step of specifying the size of each of the plurality of dummy patterns with reference to one predetermined dummy pattern. The method for arranging a dummy pattern of a semiconductor device according to claim 1,
A dummy pattern placement method for a semiconductor device, comprising: a shape designating step of designating a shape of the plurality of dummy patterns with one predetermined dummy pattern as a reference. The method for arranging a dummy pattern of a semiconductor device according to claim 1,
A dummy pattern arrangement method for a semiconductor device, comprising: an unnecessary dummy pattern information deletion processing step of deleting all dummy patterns other than one dummy pattern satisfying the area ratio rule after the area ratio rule is satisfied . This is a dummy pattern placement program for a semiconductor device that automatically places a dummy pattern with redundant wiring to satisfy the area ratio rule, which is a standard for reducing the deviation of the area occupied by the wiring, with respect to the layout of the semiconductor device. And
A predetermined area ratio analysis step for calculating a predetermined area ratio for each predetermined region for the layout of each layer, and analyzing the suitability of the predetermined area ratio for the area ratio rule;
For each of the predetermined regions, a dummy pattern generation step for generating a predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio,
Adjustment for generating a plurality of adjustment dummy patterns in which the size of an area is changed in multiple steps at predetermined intervals with respect to the predetermined dummy pattern for each of the predetermined regions. Dummy pattern generation process,
A high-precision area ratio analysis that calculates an area ratio with higher accuracy than the predetermined area ratio for each predetermined region of the layout of each layer and analyzes the suitability of the high-precision area ratio with respect to the area ratio rule Process,
Determining whether the analysis result of the high-precision area ratio analysis step satisfies the area ratio rule for one of the predetermined dummy pattern or the plurality of adjustment dummy patterns based on the predetermined dummy pattern. To determine the area ratio,
A process comprising: a dummy pattern selection step of selecting another dummy pattern for adjustment from among the plurality of adjustment dummy patterns when the determination result of the area ratio determination step does not satisfy the area ratio rule When,
A process of alternately repeating the high-precision area rate analysis step and the dummy pattern selection step until the plurality of adjustment dummy patterns selected for adjustment satisfy the area rate rule;
Further, when the determination result by the area ratio determination step satisfies the area ratio rule, the computer includes processing including an unnecessary dummy pattern information deletion processing step for deleting data other than the dummy pattern that satisfies the area ratio rule. A dummy pattern placement program for a semiconductor device for execution. In a dummy pattern placement device of a semiconductor device that places a dummy pattern with redundant wiring to satisfy an area ratio rule that is a standard for relaxing the bias of the area occupied by the wiring with respect to the layout of the semiconductor device,
Calculating a predetermined area ratio for each predetermined region of the layout of each layer, and analyzing a conformity of the predetermined area ratio to the area ratio rule;
For each of the predetermined regions, a dummy pattern generation unit that generates a predetermined dummy pattern so as to satisfy the area ratio rule based on the predetermined area ratio,
Adjustment for generating a plurality of adjustment dummy patterns in which the size of an area is changed in multiple steps at predetermined intervals with respect to the predetermined dummy pattern for each of the predetermined regions. Dummy pattern generator for
A high-accuracy area ratio analysis that calculates an area ratio with higher accuracy than the predetermined area ratio for each predetermined region of the layout data of each layer and analyzes the high-precision area ratio with respect to the area ratio rule And
Judgment whether the analysis result of the high accuracy area ratio analysis unit satisfies the area ratio rule for one of the predetermined dummy pattern or one of the plurality of adjustment dummy patterns based on the predetermined dummy pattern. An area ratio determination unit,
A dummy pattern selection unit that selects another dummy pattern for adjustment from among the plurality of adjustment dummy patterns when the determination result by the area rate determination unit does not satisfy the area rate rule;
An unnecessary dummy pattern information deletion processing unit that deletes data other than the dummy pattern that satisfies the area ratio rule when the determination result by the area ratio determination unit satisfies the area ratio rule. Dummy pattern placement device. The dummy pattern placement device for a semiconductor device according to claim 15,
The dummy pattern placement device for a semiconductor device, wherein the adjustment dummy pattern generation unit includes pattern designating means for designating a number of the plurality of adjustment dummy patterns with one predetermined dummy pattern as a reference. The dummy pattern placement device for a semiconductor device according to claim 15,
The adjustment dummy pattern generation unit includes a size designation unit that designates the size of each of the plurality of adjustment dummy patterns based on one predetermined dummy pattern. Pattern placement device. The dummy pattern placement device for a semiconductor device according to claim 15,
The dummy pattern placement device for a semiconductor device, wherein the adjustment dummy pattern generation unit includes shape designating means for designating the shapes of the plurality of adjustment dummy patterns based on one predetermined dummy pattern.

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