JP2006314189A - Power supply regulation circuit and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power regulation circuit for eliminating a secondary constant current controlling circuit, and achieving an excellent constant current drooping characteristic. <P>SOLUTION: A switching element 1 is turned on so as to maintain an on-duty of a secondary current flowing in a secondary winding 110B of a transformer 110 to a fixed value during a constant current operation, and the constant current drooping characteristic is achieved. At this time, a current limit for defining the maximum value of a drain current ID flowing in the switching element 1 is changed between first and second levels during an on-time of the switching element 1. A peak value of the drain current ID becomes constant. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply regulation circuit having a constant current drooping characteristic as an output characteristic, and a semiconductor device.

  Conventionally, as a power supply regulation circuit for a charger, a switching power supply device that has a constant current drooping characteristic by providing a constant current control circuit on the secondary side has been widely used. That is, conventionally, in order to charge a battery or the like with a constant current using a constant current drooping characteristic, an output current detection resistor which is a resistor for detecting an output current, for example, on the secondary side of a switching power supply device And a constant current control circuit for controlling the current flowing through the output current detection resistor to be constant, and a photocoupler for transmitting a signal of the constant current control circuit to the primary side, so that the output current is constant. The constant current control circuit is configured to work when the value exceeds the value, thereby realizing the constant current drooping characteristic.

  However, the switching power supply device that realizes the constant current drooping characteristic by providing the constant current control circuit as described above consumes large power, the constant current control circuit and the photocoupler are expensive, and the number of parts increases. This has hindered energy saving, high efficiency, downsizing, and low cost of the switching power supply. For this reason, there is an increasing need to realize a constant current drooping characteristic without providing a constant current control circuit.

  Hereinafter, a conventional switching power supply device that realizes a constant current drooping characteristic without a constant current control circuit will be described. Conventionally, during constant current operation, constant current drooping characteristics have been realized by lowering the current limit that defines the maximum value of the element current flowing through the switching element as the output voltage decreases (see, for example, Patent Document 1). .)

FIG. 16 is a block diagram showing a configuration of a conventional switching power supply device.
In FIG. 16, the control circuit 200 includes, as input / output units, a PIN terminal that is a startup power supply input unit, a VCC terminal that is an auxiliary power supply voltage input unit, a CS terminal that is a current detection input unit, and a switching element drive output. A switching terminal (MOSFET) 210 connected to the OUT terminal by driving the gate of the switching element (MOSFET) 210 having an OUT terminal that is a control section and a GND terminal that is a GND output section of the control circuit. The switching operation of 210 is controlled.

  The switching element 210 performs on / off control of a current flowing from the primary winding 220 </ b> A of the transformer 220. The element current (drain current) ID flowing through the switching element 210 is a triangular wave having a slope proportional to the input voltage VIN due to the inductance of the primary winding 220A.

  The rectifying / smoothing circuit including the diode 231 and the capacitor 232 converts AC power generated in the secondary winding 220 </ b> B of the transformer 220 by the switching operation of the switching element 210 into DC power and supplies the DC power to the load 233.

  The rectifying / smoothing circuit including the diode 241 and the capacitor 242 is used as an auxiliary power supply unit and an output voltage detection unit of the control circuit 200, and AC power generated in the auxiliary winding 220C of the transformer 220 by the switching operation of the switching element 210. Is converted to DC power and supplied to the VCC terminal via the resistor 243 and the capacitor 244. The AC voltage generated in the auxiliary winding 220C is proportional to the AC voltage generated in the secondary winding 220B.

  The control circuit 200 detects the drain current ID flowing through the switching element 210 based on the voltage of the CS terminal to which the voltage generated in the resistor 250 is applied. The control circuit 200 has an overcurrent protection function for preventing an overcurrent from flowing through the switching element 210. When the peak value Ip of the drain current ID increases to the current limit ILIMIT, the control circuit 200 automatically turns off the switching element 210. .

  Further, when the voltage at the VCC terminal (VCC voltage) is higher than a certain voltage, the control circuit 200 realizes constant voltage characteristics by reducing the on-duty of the switching element 210 as the VCC voltage increases. On the other hand, when the VCC voltage is lower than a certain voltage, the constant current drooping characteristic is realized by lowering the current limit ILIMIT as the current flowing into the VCC terminal decreases. At this time, the current limit ILIMIT changes as a function of the current flowing into the VCC terminal in order to keep the output current IO constant.

  The operation of the switching power supply device configured as described above will be described below with reference to the drawings. FIG. 17 is a timing chart showing the operation of each part in a conventional switching power supply device.

  When the VCC voltage is higher than the constant voltage VCC_A, the switching power supply device reduces the on-duty Don of the switching element 210 in accordance with the increase of the VCC voltage, and realizes constant voltage characteristics.

  When the load becomes heavy, the peak value Ip of the drain current ID flowing through the switching element 210 increases to the current limit ILIMIT, the output power PO becomes maximum, and the output voltage VO decreases, the VCC voltage is proportional to the decrease. descend.

  When the VCC voltage becomes lower than the constant voltage VCC_A, the switching power supply device reduces the current limit ILIMIT according to the decrease in the current flowing into the VCC terminal, thereby realizing a constant current drooping characteristic. At this time, in order to keep the output current IO constant, the current limit ILIMIT is changed by a function of the current flowing into the VCC terminal.

  In this way, as a technique for realizing a constant current drooping characteristic without a constant current control circuit, an overcurrent protection function is provided, and the maximum output power is determined by setting the maximum value of the drain current flowing through the switching element, In general, a method of detecting a decrease in output voltage at a heavier load as an overload and performing a constant current operation therefrom has been generally employed.

  However, in an actual circuit, the peak value Ip of the drain current ID flowing through the switching element is larger than the current limit ILIMIT. This is because there is a certain delay time called an overcurrent detection delay time Td from when it is detected that the drain current ID has increased to the current limit ILIMIT until when the switching element is actually turned off.

  FIG. 18A shows a waveform of the drain current ID when the current limit ILIMIT is constant with respect to an arbitrary input voltage VIN. As described above, the drain current ID is a triangular wave having a slope proportional to the input voltage VIN, but since the overcurrent detection delay time Td is constant, the current limit ILIMIT is constant with respect to an arbitrary input voltage VIN. In this case, inevitably, the increase in the current value of the drain current ID in the overcurrent detection delay time Td changes according to the input voltage VIN. That is, the peak value Ip of the drain current ID varies with the input voltage VIN even with the same current limit ILIMIT. Specifically, as shown in FIG. 18A, when the input voltage VIN is high, the drain current ID has a large slope, the drain current ID has a peak value Ip, and when the input voltage VIN is low, the drain current ID increases. The inclination of ID is small and the peak value Ip is also small.

  Therefore, when the input voltage VIN is high, the maximum value of the drain current ID is larger than when the input voltage VIN is low, and the maximum output power PO is large. This means that the detection of the overload moves to the heavy load side, and therefore the output current IO during constant current operation becomes larger at a high input voltage VIN than when it is low.

  FIG. 19A shows the relationship between the output voltage VO and the output current IO when the constant current operation is performed by the above-described conventional method using the same current limit ILIMIT for an arbitrary input voltage.

If the oscillation frequency is 'fosc', the output power PO in the discontinuous mode is
PO = A × L × Ip ² × fosc
It becomes. However, 'A' is a constant and 'L' is the inductance of the primary winding of the transformer.

  If the oscillation frequency fosc and the peak value Ip of the drain current ID flowing through the switching element are constant, the output power PO is constant even if the input voltage VIN changes. However, when the same current limit ILIMIT is used for an arbitrary input voltage, the maximum value of the drain current ID determined by the current limit ILIMIT changes depending on the input voltage VIN for the reasons described above, and the maximum output power PO also changes. Therefore, as shown in FIG. 19A, at a high input voltage VIN, the detection of overload moves to the heavy load side, and the output current IO during constant current operation is larger than when the input voltage VIN is low. Become.

  As described above, when an overload is detected using the maximum value of the drain current ID flowing through the switching element and the current limit ILIMIT that defines the maximum value of the drain current ID is controlled to achieve the constant current drooping characteristic, Since the maximum value of the drain current ID changes with the input voltage VIN and the maximum output power PO also changes, the output current IO during constant current operation changes with the input voltage VIN.

  Conventionally, the following method is adopted to solve this problem. That is, as shown in FIG. 20, the current limit ILIMIT is increased linearly for a certain time after the switching element is turned on, and then decreased to the value when the switching element is turned on.

  By setting the slope when this current limit ILIMIT rises to an appropriate value, as shown in FIG. 18B, the current limit ILIMIT becomes lower with respect to the drain current ID when the input voltage VIN is high, Since the current limit ILIMIT becomes higher with respect to the drain current ID when the input voltage VIN is low, the change in the peak value Ip of the drain current ID due to the input voltage VIN can be reduced. Therefore, this saw-shaped current limit ILIMIT results in overload detection being nearly constant, and can suppress a change in the output current IO during a constant current operation due to the input voltage VIN.

However, when the overcurrent detection delay time Td is constant, the current limit ILIMIT that makes the peak value Ip of the drain current ID constant with respect to an arbitrary input voltage VIN does not strictly change linearly with respect to time. That is, if the time after the switching element is turned on is “t”, the current limit ILIMIT needs to change with time represented by the following equation.
ILIMIT (t) = Ip × (t−Td) / t

  A current limit ILIMIT1 shown in FIG. 21 represents a current limit ILIMIT that makes the peak value Ip of the drain current ID 1A regardless of the input voltage when the overcurrent detection delay time Td is 150 ns. As shown in FIG. 21, the current limit ILIMIT1 is a simple increase, an upwardly convex function with the primary time differential coefficient being positive and the secondary time differential coefficient being negative, and does not change linearly with respect to time.

  On the other hand, the current limit ILIMIT2 is a current limit ILIMIT that changes linearly with respect to time, the overcurrent detection delay time Td is 150 ns, and the on-time Ton of the switching element is changed in the range of 1.0 to 4.5 μs. In such a case, the error of the peak value Ip of the drain current ID is set to be within about ± 3%. The peak value Ip2 is an actual peak value Ip when the current limit ILIMIT2 is used as the current limit ILIMIT.

  Here, the ON time Ton represents a period during which the switching element is ON. Strictly speaking, after the switching element is turned ON, after the drain current ID increases to the current limit ILIMIT, the overcurrent detection delay time Td. The time until the switching element is turned off with a delay.

  As shown in FIG. 21, even in the current limit ILIMIT2 that linearly changes with respect to the ON time Ton of the switching element, the dependency of the peak value Ip of the drain current ID on the input voltage is reduced as long as it is within the predetermined ON time Ton. can do. The range (1.0 to 4.5 μs) of the on-time Ton given as an example is a range of 4.5 times, and can sufficiently correspond to the input voltage range of the world wide input (AC 85 to 282 V), for example. Therefore, conventionally, for example, as in the current limit ILIMIT2 shown in FIG. 21, the slope when the current limit ILIMIT is increased is set to an appropriate value.

  However, when the on-time Ton is shorter than the overcurrent detection delay time Td, that is, when “Td / Ton” is large, the dependency of the peak value Ip of the drain current ID flowing through the switching element on the input voltage is reduced. Is difficult. For this reason, the long overcurrent detection delay time Td and the short on time Ton are disadvantageous for reducing the input voltage dependence of the peak value Ip using the current limit ILIMIT that changes linearly with time. . This can also be seen from the fact that the peak current Ip2 shown in FIG. 21 deviates significantly from 1 A when the on-time Ton is 1 μs or less.

  As shown in FIG. 17, the conventional switching power supply device realizes a constant current drooping characteristic by reducing the energy supplied to the secondary side by reducing the current limit ILIMIT. The peak value Ip of the flowing drain current ID becomes small, and the on time Ton becomes short.

  Therefore, when the constant current drooping characteristic is realized by reducing the current limit ILIMIT, the peak value Ip of the drain current changes significantly as the on-time Ton becomes shorter when the saw-type current limit ILIMIT that changes linearly with time is used. Therefore, it becomes very difficult to make the output current IO constant with respect to fluctuations in the input voltage VIN and the load weight.

  FIG. 18C shows a waveform of the drain current ID when the current limit ILIMIT is lowered and the peak value Ip of the drain current ID flowing through the switching element is reduced.

As shown in FIG. 18C, the slope of the current limit ILIMIT when the peak value Ip of the drain current ID becomes small and the on-time Ton of the switching element becomes short is the current limit ILIMIT shown in FIG. In the same case, the peak value Ip of the drain current ID changes depending on the input voltage VIN. For this reason, in the conventional method for realizing the constant current drooping characteristic by lowering the saw-shaped current limit ILIMIT during the constant current operation, the constant current drooping characteristic as shown in FIG. 19B is obtained, and the output voltage VO is lowered. It is expected that the output current IO will sometimes change due to the input voltage VIN, which is a conventional problem.
JP 2003-189612 A

  In the present invention, in view of the above problems, the on-duty of the secondary current that starts to flow to the secondary winding (second winding) from the turn-off timing of the switching element is maintained at a constant value in the constant current region. When the switching element is turned on, and the element current flowing through the switching element reaches a current limit that changes between the first and second levels during the ON time (ON period) of the switching element, the switching element is turned off. Power supply regulation circuit that can eliminate the need for constant current control circuit, photocoupler, output current detection resistor, and can control the change of output current in the constant current region due to input voltage and realize good constant current drooping characteristics The purpose is to provide.

  According to a first aspect of the present invention, there is provided a power supply regulation circuit comprising: a transformer having a first winding to which an input voltage is input; a second winding for generating an output voltage; a first terminal; The first winding by oscillating so as to electrically couple or separate the first and second terminals in response to a control signal received at the control terminal. A switching element that performs on / off control of the current flowing through the line, and a control circuit that generates the control signal, and controls energy of the first and second windings by controlling oscillation of the switching element. A power supply regulation circuit for controlling a supply amount and supplying a constant output current to a load connected to the second winding, wherein the control circuit detects an element current flowing through the switching element. And a current limit that defines a maximum value of the element current during the period in which the switching element couples the first and second terminals to a first level and a first level greater than the first level. A current limit variable function that changes between two levels, and a function that outputs a signal that turns off the switching element when the element current reaches the current limit that changes between the first and second levels. A function of detecting an on-duty of a secondary current flowing through the second winding and outputting a signal for turning on the switching element so that the on-duty of the secondary current becomes a constant value; And a function of generating the control signal based on a signal for turning on and a signal for turning off.

  The power supply regulation circuit according to claim 2 of the present invention is the power supply regulation circuit according to claim 1, wherein the current limit variable function changes a detection value of the element current by the element current detection function. Thus, the current limit is changed between the first level and the second level during a period in which the switching element couples the first and second terminals.

  The power supply regulation circuit according to claim 3 of the present invention is the power supply regulation circuit according to claim 1, wherein the variable current limit function changes the switching value by changing a reference value for determining the current limit. The current limit is varied between the first level and the second level during a period in which an element couples the first and second terminals.

  A power supply regulation circuit according to a fourth aspect of the present invention is the power supply regulation circuit according to any one of the first to third aspects, wherein the transformer detects a voltage generated in the second winding. The control circuit further includes a third winding for performing the detection, and the control circuit detects an on-duty of the secondary current based on a voltage generated in the third winding.

  A power supply regulation circuit according to claim 5 of the present invention is the power supply regulation circuit according to any one of claims 1 to 4, wherein the control circuit has an on-duty of the secondary current equal to or less than a predetermined value. If there is, it further has a function of changing the energy supply amount so that the output voltage becomes constant.

  The power supply regulation circuit according to claim 6 of the present invention is the power supply regulation circuit according to claim 5, wherein the control circuit is configured such that when the on-duty of the secondary current is a predetermined value or less, the switching element The output voltage is made constant by changing the energy supply amount by changing the oscillation frequency of the output.

  According to a seventh aspect of the present invention, the power supply regulation circuit according to the fifth aspect is the power supply regulation circuit according to the fifth aspect, wherein the control circuit is configured such that the on-duty of the secondary current is equal to or less than a predetermined value. The output voltage is made constant by changing the energy supply amount by changing a period during which the switching element couples the first and second terminals while keeping the oscillation frequency constant.

  The power supply regulation circuit according to claim 8 of the present invention is the power supply regulation circuit according to claim 5, wherein the control circuit is configured such that the on-duty of the secondary current is a predetermined value or less and the output current is If less than a predetermined value, the energy supply amount is changed by changing a period during which the switching element couples the first and second terminals while keeping the oscillation frequency of the switching element constant, and the output voltage is changed. When the on-duty of the secondary current is not more than a certain value and the output current is not less than a certain value, the energy supply amount is changed by changing the oscillation frequency of the switching element to keep the output voltage constant. It is characterized by.

  A power supply regulation circuit according to a ninth aspect of the present invention is the power supply regulation circuit according to any one of the first to eighth aspects, wherein the control circuit is formed on the same semiconductor substrate. And

  A power supply regulation circuit according to a tenth aspect of the present invention is the power supply regulation circuit according to any one of the first to eighth aspects, wherein the switching element and the control circuit are formed on the same semiconductor substrate. It is characterized by being.

  A semiconductor device according to an eleventh aspect of the present invention is characterized in that the control circuit according to any one of the first to eighth aspects is formed on the same semiconductor substrate.

  A semiconductor device according to a twelfth aspect of the present invention is characterized in that the switching element according to any one of the first to eighth aspects and the control circuit are formed on the same semiconductor substrate.

  According to the present invention, a constant current control circuit, a photocoupler, and an output current detection resistor can be made unnecessary, and furthermore, a change in output current in a constant current region due to an input voltage can be suppressed, and a good constant current drooping characteristic can be obtained. Can be easily obtained. In other words, as in the past, when the drain current is detected and the drain current increases up to the current limit, the current limit is reduced according to the decrease in the output voltage, and the peak value of the drain current is reduced, thereby reducing the constant current drooping characteristic. Instead of realizing, the switching element is turned on so that the on-duty of the secondary current is maintained at a constant value, and the element current is between the first and second levels during the on-time (on period) of the switching element. When the current limit is changed, the switching element is turned off to achieve the constant current drooping characteristic. Therefore, when the output voltage drops in the constant current region, the on-time of the switching element is not shortened. Therefore, the output current does not change depending on the input voltage.

  Moreover, since the current limit is changed between the first level and the second level during the on-time of the switching element by changing the detection value of the element current flowing through the switching element and the reference value for determining the current limit, If the slope of the current limit that changes during the on-time is set appropriately, the output current in the constant current region can be made almost constant regardless of the input voltage.

  In addition, by detecting the voltage change of the third winding of the transformer and detecting the on-duty of the secondary current, the insulation between the primary side and the secondary side of the transformer is maintained with less power loss and additional components. In this way, it is possible to realize control that makes the on-duty of the secondary current constant.

  Further, by making the output voltage constant until the on-duty of the secondary current reaches a constant value, either the constant current drooping characteristic or the constant voltage characteristic can be realized according to the load state. Further, by performing the control to make the output voltage constant by changing the oscillation frequency of the switching element, switching from the constant voltage region to the constant current region can be performed smoothly. Further, if the output voltage is made constant by changing the on-time of the switching element while keeping the oscillation frequency constant, the sound of the transformer can be prevented.

  Further, if the control circuit is formed on the same semiconductor substrate, or if the switching element and the control circuit are formed on the same semiconductor substrate, space saving and cost reduction of the power supply regulation circuit can be realized.

  Hereinafter, a power supply regulation circuit according to an embodiment of the present invention will be specifically described with reference to the drawings. In the present embodiment, a switching power supply device is used as the power supply regulation circuit.

FIG. 1 is a block diagram showing a configuration example of a switching power supply device according to the present embodiment.
In FIG. 1, a switching element 1 is a power MOSFET, and includes three terminals: a DRAIN terminal that is an input terminal (first terminal), a SOURCE terminal that is an output terminal (second terminal), and a GATE terminal that is a control terminal. In response to the control signal received at the control terminal, the input terminal and the output terminal oscillate so as to be electrically coupled or separated. Then, on / off control of the current flowing through the primary winding 110A of the transformer 110 is performed by this oscillation operation.

  Further, the semiconductor device 100 for controlling the switching power supply device includes the switching element 1 and a control circuit, and the control circuit generates a control signal and controls the switching operation (oscillation operation) of the switching element 1. In addition, the semiconductor device 100 includes, as external input terminals, an input terminal (DRAIN terminal) of the switching element 1, an auxiliary power supply voltage input terminal (VCC terminal), a secondary current off timing detection terminal (TR terminal), and an output of the switching element 1. There are four terminals of the GND terminal (SOURCE terminal) of the control circuit which is also a terminal.

  The transformer 110 includes a primary winding (first winding) 110A for inputting an input voltage VIN, a secondary winding (second winding) 110B for outputting an output voltage VO, and a secondary winding. And an auxiliary winding (third winding) 110C for detecting a voltage generated at 110B. Further, the polarities of the primary winding 110A and the secondary winding 110B are reversed, and the switching power supply device is a flyback type.

  A rectifying / smoothing circuit including a diode 120 and a capacitor 121 is connected to the auxiliary winding 110 </ b> C, and this rectifying / smoothing circuit is used as an auxiliary power supply unit of the semiconductor device 100. That is, the auxiliary winding 110C has the same polarity as the secondary winding 110B, and the auxiliary power supply unit rectifies the AC voltage (auxiliary AC voltage) generated in the auxiliary winding 110C by the switching operation of the switching element 1. The auxiliary power supply voltage VCC proportional to the output voltage VO is generated by smoothing and applied to the VCC terminal.

  Resistors 123 and 124 are connected to the auxiliary winding 110C via a diode 122, and the connection point of the resistors 123 and 124 is connected to the TR terminal. The AC voltage generated in the auxiliary winding 110C is rectified by the diode 122, divided by the resistors 123 and 124, and applied to the TR terminal. The voltage applied to the TR terminal (hereinafter referred to as TR terminal voltage VTR) is the timing at which the secondary current flowing through the secondary winding 110B has ended by the switching operation of the switching element 1 (hereinafter referred to as off timing). )).

  A rectifying / smoothing circuit including a diode 130 and a capacitor 131 is connected to the secondary winding 110B, and this rectifying / smoothing circuit is used as an output voltage generation unit of the switching power supply device. That is, the output voltage generator rectifies and smoothes the AC voltage (secondary AC voltage) generated in the secondary winding 110B by the switching operation of the switching element 1, and outputs the output voltage VO (second DC voltage). Is generated and applied to the load 132.

  FIG. 2 is a block diagram illustrating a configuration example of the semiconductor device 100 for controlling the switching power supply that constitutes the switching power supply in the present embodiment. The semiconductor device 100 includes a switching element 1 and a control circuit. The control circuit controls the amount of energy supplied to the primary winding 110A and the secondary winding 110B of the transformer 110 by controlling the oscillation of the switching element 1. The output current IO to the load 132 in the constant current region is made substantially constant.

  In FIG. 2, the regulator 2 supplies a current from either the DRAIN terminal or the VCC terminal to the internal circuit power supply VDD of the semiconductor device 100, and stabilizes the voltage of the internal circuit power supply VDD to a constant value.

  That is, the regulator 2 supplies current from the DRAIN terminal to the internal circuit power supply VDD and also supplies current to the capacitor 121 of the auxiliary power supply unit via the VCC terminal before the switching operation of the switching element 1 is started. The auxiliary power supply voltage VCC and the internal circuit power supply VDD are increased. When the voltage of the internal circuit power supply VDD reaches a certain value, the output signal to the NAND circuit 13 is changed from a signal having a low signal level (hereinafter referred to as a low level signal) to a signal having a high signal level. (Hereinafter referred to as a high level signal), and the switching operation of the switching element 1 is started.

  After the switching operation of the switching element 1 is started, the current supply from the DRAIN terminal to the VCC terminal is stopped, and the current supply terminal to the internal circuit power supply VDD is determined by the value of the auxiliary power supply voltage VCC. That is, when the auxiliary power supply voltage VCC becomes a certain value or more, the regulator 2 supplies a current from the VCC terminal to the internal circuit power supply VDD to reduce the power consumption of the semiconductor device 100. On the other hand, when the auxiliary power supply voltage VCC falls below a certain value, such as when the output voltage VO decreases in the constant current region, the regulator 2 supplies current from the DRAIN terminal to the internal circuit power supply VDD. In this way, the regulator 2 stabilizes the internal circuit power supply VDD to a constant value.

  The error amplifier 3 compares the stabilization reference voltage and the auxiliary power supply voltage VCC, and generates an error voltage signal VEAO from the difference. The drain current detection variable circuit (current limit variable circuit) 4 receives the output signal (FFout signal) of the flip-flop circuit 12 and detects when the switching element 1 is turned on and when it is turned off, and according to the timing. The changing current signal (current limit variable signal) Islope is output to the drain current detection circuit 5. As a result, the drain current detection circuit (element current detection circuit) 5 having the element current detection function for detecting the drain current ID flowing through the switching element 1 has the drain current (element current) ID flowing through the switching element 1 and the current limit variable signal. The element current detection signal VCL, which is a voltage signal corresponding to Islope, is output.

  That is, the drain current detection variable circuit 4 generates the current limit variable signal Islope to change the drain current value (element current detection value) detected by the drain current detection circuit 5, and finally the error voltage signal VEAO. Is larger than the overcurrent protection reference voltage VLIMIT, the current limit ILIMIT that defines the maximum value of the drain current ID is made to have a saw-like waveform that varies linearly as shown in FIG.

  As described above, the detection value of the drain current ID is changed by the current limit variable function of the drain current detection variable circuit 4, and the error voltage signal VEAO is excessively increased by making the current limit ILMIT into a saw-tooth waveform linearly changing with time. When the voltage exceeds the current protection reference voltage VLIMIT, the actual peak value Ip of the drain current ID taking into account the overcurrent detection delay time Td is made to be substantially constant regardless of the input voltage VIN. Regardless, the output current IO in the constant current region is made substantially constant.

  The drain current control circuit (element current control circuit) 6 receives the overcurrent protection reference voltage VLIMIT and the error voltage signal VEAO output from the error amplifier 3 as reference voltages. When the voltage of the element current detection signal VCL reaches the lower voltage of the overcurrent protection reference voltage VLIMIT and the error voltage signal VEAO, the drain current control circuit 6 causes the switching element to switch to the reset terminal of the flip-flop circuit 12. A signal for determining turn-off of 1 (here, a high level signal) is output.

  The oscillator 7 outputs to the clock signal selection circuit 11 a clock signal set_1 (first clock signal) having a fixed period that determines turn-on of the switching element 1. This clock signal set_1 determines the oscillation frequency of the switching element 1 in the constant voltage region.

  The oscillation frequency adjusting circuit 8 increases the frequency of the clock signal set_1 (shortens the cycle) according to the difference in which the voltage of the error voltage signal VEAO output from the error amplifier 3 exceeds the overcurrent protection reference voltage VLIMIT. That is, the oscillation frequency adjustment circuit 8 outputs a signal having a current value corresponding to the voltage difference to the oscillator 7 only when the voltage of the error voltage signal VEAO output from the error amplifier 3 is higher than the overcurrent protection reference voltage VLIMIT. As the voltage difference increases, the frequency of the clock signal set_1 output from the oscillator 7 is increased (the period is shortened). Thereby, even if the load 132 becomes heavy, the output voltage VO can be stabilized at a constant value.

  The secondary current off detection circuit 9 is connected to the TR terminal, detects the off timing of the secondary current based on the TR terminal voltage VTR, that is, the auxiliary AC voltage, and outputs the output signal to the oscillator 7 and the secondary duty limit circuit 10. Output. The output signal D2_on becomes a high level signal after the switching element 1 is turned off until the secondary current off timing is detected, that is, in a period during which the secondary current flows.

  In the flyback type switching power supply, current flows in the primary winding 110A of the transformer 110 during the ON period of the switching element 1 and energy is stored in the transformer 110, and energy is stored in the transformer 110 during the OFF period of the switching element 1. Energy is released and a current flows through the secondary winding 110B of the transformer 110. Thereafter, when the current flowing through the secondary winding 110B becomes zero, a resonance phenomenon occurs due to the inductance of the transformer 110 and the parasitic capacitance of the switching element 1. Since this resonance phenomenon appears in each winding of the transformer 110, the switching power supply apparatus detects the falling edge that appears in the voltage waveform of the auxiliary winding 110 </ b> C after the switching element 1 is turned off to detect the off timing of the secondary current. Is detected.

  The secondary duty limit circuit 10 receives the output signal of the secondary current off detection circuit 9 as an input, and detects a period (secondary current on period) from the turn-off timing of the switching element 1 to the timing when the secondary current ends. Then, the clock signal set_2 (second clock signal) for turning on the switching element 1 is output to the clock signal selection circuit 11 at the timing when the on-duty of the secondary current becomes constant.

  That is, as the current flowing through the load 132 increases, the ON period of the secondary current becomes longer, so the frequency of the output signal set_2 of the secondary duty limiting circuit 10 becomes lower. This clock signal set_2 determines the oscillation frequency of the switching element 1 in the constant current region. As a fixed value, for example, the secondary current on-duty is maintained at about 50% (more preferably 50%).

  The clock signal selection circuit 11 receives the output signal from the oscillator 7 and the output signal from the secondary duty limiting circuit 10 and outputs a set signal set to the flip-flop circuit 12 when both output signals are input. That is, the clock signal having the lower frequency of either one is output to the flip-flop circuit 12. Therefore, when the secondary current on-duty is smaller than a certain value, the first clock signal set_1 is output to the flip-flop circuit 12 when the secondary current on-duty reaches a certain value.

  Here, the flip-flop circuit 12, the NAND circuit 13, and the gate driver 14 constitute a switching control circuit, and this switching control circuit performs the switching operation (on / off operation of the switching element 1) according to the set / reset state of the flip-flop circuit 12. Control).

  The NAND circuit 13 receives an output signal from the regulator 2 and an output signal from the flip-flop circuit 12 and outputs an output signal to the gate driver 14. The gate driver 14 receives the output signal from the NAND circuit 13 and outputs a control signal (turn-on pulse signal) for controlling the switching operation (oscillation operation) of the switching element 1 to the control terminal (GATE terminal) of the switching element 1. .

  As described above, the switching control circuit generates a control signal based on the signal that determines the turn-on of the switching element 1 from the clock signal selection circuit 11 and the signal that determines the turn-off of the switching element 1 from the drain current control circuit 6. The oscillation of the switching element 1 is controlled.

  The switching element 1 repeats an on / off operation in response to a turn-on pulse signal from the gate driver 14 (switching operation), thereby controlling on / off of the current flowing through the primary winding 110A of the transformer 110 to 2 A secondary AC voltage is generated in the secondary winding 110B and an auxiliary AC voltage is generated in the auxiliary winding 110C.

  As described above, when the on-duty of the secondary current that starts to flow into the secondary winding 110B of the transformer 110 after the switching element 1 is turned off reaches a constant value, the secondary current on-duty is maintained at the constant value. Since the constant current operation is realized by controlling the switching operation of the switching element 1, the secondary side constant current control circuit, the output current detection resistor, and the photocoupler can be dispensed with, and the low cost, the minimum number of parts, Moreover, constant current drooping characteristics with sufficient accuracy can be realized with minimum power loss, and the switching power supply for the charger can be reduced in cost, size and energy saving.

  Further, when the error voltage signal VEAO becomes larger than the overcurrent protection reference voltage VLIMIT, the current limit ILIMIT that defines the maximum value of the drain current ID flowing through the switching element 1 is a saw-tooth waveform that linearly changes with time as shown in FIG. Therefore, the actual peak value Ip considering the overcurrent detection delay time Td becomes substantially constant regardless of the input voltage VIN, and the change in the maximum output current PO due to the input voltage VIN can be suppressed. The output current IO during constant current operation can be made substantially constant.

  Further, as in the prior art, when the drain current ID is detected and the drain current ID increases up to the current limit ILIMIT, the current limit ILIMIT is decreased according to the decrease in the output voltage VO, and the peak value Ip of the drain current ID is decreased. Therefore, constant current operation is realized by changing the oscillation frequency fosc so that the secondary current on-duty becomes a constant value instead of realizing constant current drooping characteristics, so that the output voltage VO decreases in the constant current region. In this case, the on-time Ton of the switching element is not shortened as in the prior art. Therefore, when the on-time Ton is shortened, the peak value Ip cannot be controlled without being influenced by the input voltage VIN. The output current can be reduced by the input voltage VIN even when the output voltage VO decreases. O does not change.

  Further, the switching element 1 and its control circuit are formed on the same semiconductor substrate, the connection terminal between the input voltage VIN and the switching element 1 (DRAIN terminal and SOURCE terminal), and the connection between the control circuit and the auxiliary power supply voltage VCC. By configuring as a semiconductor device 100 having a terminal (VCC terminal) and an input terminal (TR terminal) of the secondary current off detection circuit 9, the number of parts for configuring the circuit can be reduced and easily Miniaturization (space saving), weight reduction, and cost reduction can be realized. In this embodiment, a semiconductor device in which the switching element 1 and its control circuit are formed on the same semiconductor substrate will be described as an example. However, only the control circuit is formed on the same semiconductor substrate and the switching element 1 is externally attached. The same effect can be obtained even in the semiconductor device.

  FIG. 3 is a block diagram showing a configuration example of the secondary current off detection circuit 9 and the secondary duty limiting circuit 10 which constitute a part of the semiconductor device 100 for controlling the switching power supply of the switching power supply according to the present embodiment. is there. Here, the secondary current on-duty is detected by the secondary current off detection circuit 9 and the secondary duty limit circuit 10, and a signal for turning off the switching element 1 so that the secondary current on-duty becomes a constant value is provided. Realize output function.

  The secondary current off detection circuit 9 includes a comparator 21, one-pulse signal generation circuits 22 and 23, and a flip-flop circuit 24, and each element is connected as shown in FIG.

  The one-pulse signal generation circuit 23 receives the output signal of the gate driver 14 and generates a one-pulse signal at the fall of the turn-on pulse signal that is the output signal of the gate driver 14, that is, the turn-off timing of the switching element 1. Input to the set terminal.

  The comparator 21 compares the TR terminal voltage VTR with the reference voltage, detects the falling of the TR terminal voltage VTR, that is, the falling that appears in the voltage waveform of the auxiliary winding 110C after the switching element 1 is turned off, and outputs the output signal. Output to the one-pulse signal generation circuit 22. Here, the secondary current off detection circuit 9 detects the off timing of the secondary current based on the voltage of the auxiliary winding 110C.

  The one-pulse signal generation circuit 22 generates a one-pulse signal at the timing when the TR terminal voltage VTR becomes lower than the reference voltage, that is, the secondary current off timing, and inputs the one-pulse signal to the reset terminal of the flip-flop circuit 24. Thereby, the output signal and the inverted output signal of the flip-flop circuit 24 are inverted at the first falling timing (secondary current off timing) of the TR terminal voltage VTR after the switching element 1 is turned off.

  As described above, the output signal of the flip-flop circuit 24 is output from the one-pulse signal generation circuits 22 and 23 until the secondary current flows after the switching element 1 is turned off, that is, during the period when the secondary current flows. It becomes a high level signal, and the inverted output signal becomes a low level signal. The output signal and the inverted output signal are inverted at the turn-off timing of the secondary current, and the next turn-on pulse signal is input to the switching element 1 until the switching element 1 is turned off, that is, a period in which the secondary current does not flow. The output signal of the flip-flop circuit 24 is a low level signal, and the inverted output signal is a high level signal.

  The secondary duty limiting circuit 10 includes an inverter circuit 25, AND circuits 26 and 35, a constant current source 27, switches 28, 29 and 30, Nch MOSFETs 31 and 32, a capacitor 33, a comparator 34, and a one-pulse signal generation circuit 36. Each element is connected as shown in FIG.

  The switches 28 and 29 are turned on / off by the output signal and the inverted output signal of the flip-flop circuit 24 in the secondary current off detection circuit 9. The capacitors 33 are charged and discharged by the operations of the switches 28 and 29.

  That is, the output signal of the flip-flop circuit 24 becomes a high level signal and the inverted output signal is at a low level during the period from when the switching element 1 is turned off until the secondary current ends, that is, during the period when the secondary current flows. Since this is a signal, the switch 28 is turned on and the switch 29 is turned off. As a result, the capacitor 33 is charged by the constant current I2 of the constant current source 27, and the voltage VC2 of the capacitor 33 increases. In addition, the switch 28 is turned off and the switch 29 is turned on during the period from when the secondary current ends to the time when the next turn-on pulse signal is input until the switching element 1 is turned off, that is, during the period when the secondary current is not flowing. Therefore, the capacitor 33 is discharged. The discharge current at this time is determined by the constant current I2 of the constant current source 27 and the current mirror circuit composed of the Nch MOSFETs 31 and 32.

  Here, while the switch 29 is on and the switching element 1 is off, the switch 30 is turned on by the inverter circuit 25 and the AND circuit 26. In this way, the voltage VC2 of the capacitor 33 is the reference while the switch 28 is off, the switch 29 is on, and the switch 30 is on, that is, the period when the secondary current is not flowing and the switching element 1 is off. Since it is held at the voltage VA, there is a period during which the voltage VC2 is held at a constant value (reference voltage VA) during the discharge period of the capacitor 33. Thereby, the discharge start voltage of the capacitor 33 when the switching element 1 is turned on can be fixed.

  The comparator 34 compares the voltage VC2 of the capacitor 33 with the reference voltage VA, and outputs a signal (comparison result) to the AND circuit 35. When the voltage VC2 of the capacitor 33 becomes lower than the reference voltage VA, the output of the comparator 34 becomes a high level signal, and when the voltage VC2 of the capacitor 33 becomes higher than the reference voltage VA, the output of the comparator 34 becomes a low level signal.

  The AND circuit 35 inputs the inverted output signal of the flip-flop circuit 24 in the secondary current off detection circuit 9 and the output signal of the comparator 34, and outputs an output signal to the one-pulse signal generation circuit 36. In the one-pulse signal generation circuit 36, the voltage VC2 of the capacitor 33 reaches the reference voltage VA at the timing when the output signal of the AND circuit 35 is inverted from the low level signal to the high level signal, that is, in the period when the secondary current is not flowing. Then, a one-pulse signal (set_2) is output to the clock signal selection circuit 11.

  With the above configuration, the voltage VC2 of the capacitor 33, which has been fixed at the reference voltage VA when the switching element 1 is turned on, starts discharging simultaneously with the turning on of the switching element 1. Then, switching from discharging to charging is performed at the turn-off timing of the switching element 1, and charging is performed during a period in which the secondary current is flowing, and switching from charging to discharging is performed again when the off-timing of the secondary current is detected. When the voltage drops again to the reference voltage VA, the one-pulse signal (set_2) is output. Therefore, the clock signal set_2 has a timing at which the secondary current on-duty becomes constant regardless of the magnitude and inclination of the secondary current. The output is made to turn on the switching element 1. A clock signal set_2 having a constant period for setting the secondary current on-duty to a constant value is output to the clock signal selection circuit 11.

  As described above, the secondary current off-duty is detected based on the voltage change of the auxiliary winding 110C and the secondary current on-duty is detected. Therefore, the power consumption of the transformer 110 can be reduced with less power loss and additional components. Control that makes the secondary current on-duty constant can be realized while maintaining insulation between the primary side and the secondary side.

  FIG. 4 is a block diagram showing a configuration example of the clock signal selection circuit 11 that constitutes a part of the semiconductor device 100 for controlling the switching power supply of the switching power supply according to the present embodiment.

  The clock signal selection circuit 11 includes one-pulse signal generation circuits 41 and 45, flip-flop circuits 42 and 43, and an AND circuit 44, and each element is connected as shown in FIG.

  The one-pulse signal generation circuit 41 receives the output signal of the gate driver 14 and generates a one-pulse signal at the falling edge of the turn-on pulse signal that is the output signal of the gate driver 14, that is, at the turn-off timing of the switching element 1. , 43 to the reset terminal.

  The flip-flop circuit 42 inputs the output signal set_1 of the oscillator 7 to the set terminal, inputs the output signal of the one-pulse signal generation circuit 41 to the reset terminal, and outputs the output signal to the AND circuit 44.

  The flip-flop circuit 43 inputs the output signal set_2 of the secondary duty limiting circuit 10 to the set terminal, inputs the output signal of the one-pulse signal generation circuit 41 to the reset terminal, and outputs the output signal to the AND circuit 44.

  The AND circuit 44 inputs the output signals of the flip-flop circuits 42 and 43, and outputs the output signal to the one-pulse signal generation circuit 45. The one-pulse signal generation circuit 45 outputs the output signal of the AND circuit 44 from the low level signal to the high level. The one-pulse signal set is output to the set terminal of the flip-flop circuit 12 at the timing of inversion to the signal, that is, at the timing when both the clock signal set_1 and the clock signal set_2 are input.

  As described above, the clock signal selection circuit 11 receives the output signal set_1 from the oscillator 7 and the output signal set_2 from the secondary duty limiting circuit 10, and flips the set signal set when both output signals are input. Output to the set terminal of the circuit 12. That is, the clock signal having the lower frequency is output to the set terminal of the flip-flop circuit 12. Therefore, when the secondary current on-duty is smaller than a certain value, the first clock signal set_1 is sent to the set terminal of the flip-flop circuit 12 when the secondary current on-duty reaches a certain value. Output.

  FIG. 5 is a block diagram showing a configuration example of the oscillator 7 and the oscillation frequency adjusting circuit 8 constituting part of the semiconductor device 100 for controlling the switching power supply of the switching power supply according to the present embodiment.

  The oscillator 7 includes a comparator 51, a reference voltage source 52, a capacitor 53, a one-pulse signal generation circuit 54, an inverter circuit 55, an AND circuit 56, a constant current source 57, switches 58, 59 and 60, and Nch MOSFETs 61 and 62. Each element is connected as shown in FIG.

  The comparator 51 compares the voltage VC1 of the capacitor 53 with the reference voltage of the reference voltage source 52, and outputs a low level signal when the voltage VC1 of the capacitor 53 becomes lower than the reference voltage, and outputs a high level signal when the voltage VC1 becomes higher than the reference voltage. To do.

  In the reference voltage source 52, two different reference voltages V1 and V2 that are switched by the output signal of the comparator 51 are set, and the reference voltage V2 is higher than the reference voltage V1. When the output signal of the comparator 51 is inverted from the high level signal to the low level signal, the reference voltage of the reference voltage source 52 is switched from the reference voltage V1 to the reference voltage V2, and when the output signal from the low level signal is inverted to the high level signal, The voltage V2 is switched to the reference voltage V1.

  That is, when the voltage VC1 of the capacitor 53 becomes lower than the reference voltage V1, the output signal of the comparator 51 is inverted from the high level signal to the low level signal, the switch 58 is turned on and the switch 59 is turned off. Therefore, the constant current I1 of the constant current source 57 charges the capacitor 53, and the voltage VC1 rises. When the voltage VC1 of the capacitor 53 becomes higher than the reference voltage V2, the output signal of the comparator 51 changes from the low level signal to the high level signal, the switch 58 is turned off, the switch 59 is turned on, and the capacitor 53 is discharged. The discharge current at this time is determined by a current mirror circuit composed of the constant current I1 of the constant current source 57 and the Nch MOSFETs 61 and 62.

  As described above, the switches 58 and 59 are turned on / off by the output signal of the comparator 51 to charge and discharge the capacitor 53, and the voltage VC1 of the capacitor 53 has a waveform that oscillates between the two reference voltages V1 and V2.

  However, when the output signal D2_on of the flip-flop circuit 24 in the secondary current off detection circuit 9 is a high level signal, that is, in the period when the secondary current is flowing, the switch 60 is turned on, so the voltage of the capacitor 53 When VC1 drops to the reference voltage VB during the discharge period, VC1 is held at the reference voltage VB.

  The one-pulse signal generation circuit 54 outputs the one-pulse signal set_1 at the timing when the output signal of the comparator 51 is inverted from the high level signal to the low level signal, that is, when the capacitor 53 is switched from the discharging period to the charging period. As a result, a clock signal set_1 having a fixed period is input to the clock signal selection circuit 11.

  As described above, the voltage VC1 of the capacitor 53 does not become lower than the reference voltage VB during the period when the secondary current flows by the AND circuit 56 and the switch 60. Therefore, the clock signal set_1 is not output unless the secondary current flows. That is, the switching power supply device always operates in the discontinuous mode. In this way, the oscillator 7 outputs the clock signal set_1 having a fixed period that determines the oscillation frequency of the switching element 1 to the clock signal selection circuit 11.

  The oscillation frequency adjusting circuit 8 includes NPN transistors 63 and 64, resistors 65 and 66, Pch MOSFETs 67, 68, 69, 70, 73 and 74, and Nch MOSFETs 71 and 72, and each element is connected as shown in FIG. Has been.

  An error voltage signal VEAO is input to the base terminal of the NPN transistor 63, and an error output from the error amplifier 3 by the resistor 65, a current mirror circuit composed of PchMOSFETs 67 and 68, and a current mirror circuit composed of NchMOSFETs 71 and 72. A current proportional to the voltage of the voltage signal VEAO flows through the Nch MOSFET 72.

  On the other hand, an overcurrent protection reference voltage VLIMIT is input to the base terminal of the NPN transistor 64, and a current proportional to the overcurrent protection reference voltage VLIMIT flows through the PchMOSFET 70 by the resistor 66 and the current mirror circuit including the PchMOSFETs 69 and 70.

  Here, when the current flowing through the Nch MOSFET 72 is smaller than the current flowing through the Pch MOSFET 70, no current flows through the current mirror circuit composed of the Pch MOSFETs 73 and 74. On the other hand, when the current flowing through the Nch MOSFET 72 is larger than the current flowing through the Pch MOSFET 70, the difference current between the current flowing through the Nch MOSFET 72 and the current flowing through the Pch MOSFET 70 flows through the current mirror circuit composed of the Pch MOSFETs 73 and 74. The current flowing through the Pch MOSFET 74 is added to the constant current I1 of the constant current source 57, whereby the charge / discharge cycle of the capacitor 53 is shortened.

  Therefore, when the error voltage signal VEAO becomes higher than the overcurrent protection reference voltage VLIMIT, the cycle of the clock signal set_1 output from the oscillator 7 is shortened, and the frequency increases as the difference increases.

  As described above, the oscillation frequency adjusting circuit 8 outputs a signal having a current value corresponding to the voltage difference to the oscillator 7 only when the error voltage signal VEAO is higher than the overcurrent protection reference voltage VLIMIT. As a result, when the voltage of the error voltage signal VEAO becomes higher than the overcurrent protection reference voltage VLIMIT, the frequency of the clock signal set_1 output from the oscillator 7 increases as the difference increases (the cycle becomes shorter).

  The clock signal set_1 is input to the clock signal selection circuit 11 and is selected when the secondary current on-duty is equal to or less than a certain value. As described above, the switching power supply device has a heavy load when the secondary current on-duty is a certain value or less, the output current IO becomes a predetermined value or more, and the error voltage signal VEAO becomes higher than the overcurrent protection reference voltage VLIMIT. A constant voltage operation is performed in which the amount of energy supplied to the primary winding 110A and the secondary winding 110B is changed by changing the oscillation frequency of the switching element 1 to keep the output voltage VO constant.

  FIG. 6 is a block diagram showing a configuration example of the drain current detection variable circuit 4 constituting a part of the semiconductor device 100 for controlling the switching power supply of the switching power supply according to the present embodiment.

  The drain current detection variable circuit 4 includes a charge / discharge circuit 81, a capacitor 82, a PNP transistor 83, an NPN transistor 84, a resistor 85, a constant current source 86, Pch MOSFETs 87 and 88, and Nch MOSFETs 89 and 90. FIG. As shown, each element is connected.

  The charge / discharge circuit 81 receives the FFout signal from the flip-flop circuit 12. When the FFout signal becomes a high level signal, that is, when the switching element 1 is turned on, the charging / discharging circuit 81 charges the capacitor 82 with a constant current, and when it becomes a low level signal, that is, when the switching element 1 is turned off, the capacitor 82 is discharged. To do.

  As shown in FIG. 8, the time change of the voltage Vcap2 of the capacitor 82 continues to rise while the switching element 1 is turned on, and becomes a discontinuous triangular wave that sharply falls when the switching element 1 is turned off. The rising slope of the triangular wave is constant because the charge / discharge circuit 81 charges the capacitor 82 with a constant current.

  The voltage Vcap2 is converted into a current signal by the PNP transistor 83, the NPN transistor 84, the resistor 85, and the constant current source 86. The current mirror circuit including the Pch MOS EFTs 87 and 88 and the current mirror circuit including the Nch MOSFETs 89 and 90 are further multiplied by a constant number. Current signal (current limit variable signal) Islope is input to the drain current detection circuit 5. Therefore, the current limit variable signal Islope becomes a discontinuous triangular wave that changes with time according to the change of the voltage Vcap2 of the capacitor 82 with time.

  FIG. 7 is a block diagram showing a configuration example of the drain current detection circuit 5 constituting a part of the semiconductor device 100 for controlling the switching power supply of the switching power supply according to the present embodiment.

  The drain current detection circuit 5 includes resistors 91 and 92, and each element is connected as shown in FIG. The drain current detection circuit 5 outputs an element current detection signal VCL which is a voltage signal corresponding to the drain current ID flowing through the switching element 1 and the current limit variable signal Islope.

Here, the drain voltage VD of the switching element 1 is expressed as follows:
VD = RON × ID (1)
It becomes.

Further, assuming that the resistance value of the resistor 91 is “R1”, the current flowing through the resistor 91 is “Iref”, and the resistance value of the resistor 92 is “R2”, the drain relationship of the switching element 1 is obtained from the connection relationship shown in FIG. The voltage VD is
VD = VCL + Iref × R1 = VCL × (R1 + R2) / R2 + Islope × R1 (2)
It becomes.

Therefore, from the above equations (1) and (2), the drain current ID is
ID = {(R1 + R2) × VCL + R1 × R2 × Islope} / (RON × R2) (3)
It becomes.

The peak value Ip of the drain current ID changes according to the error voltage signal VEAO when the error voltage signal VEAO is lower than the overcurrent protection reference voltage VLIMIT, and is maximum when the error voltage signal VEAO reaches the overcurrent protection reference voltage VLIMIT. Value. That is, the maximum value ILIMIT of the drain current ID is expressed as follows from the above equation (3).
ILIMIT = {(R1 + R2) × VLIMIT + R1 × R2 × Islope} / (RON × R2) (4)

  Therefore, when the error voltage signal VEAO is equal to or higher than the overcurrent protection reference voltage VLIMIT, the maximum value ILIMIT of the drain current ID is determined by the switching element 1 according to the time change of the current limit variable signal Islope as shown in FIG. In the period when the input terminal and the output terminal are coupled (ON time Ton), the time changes linearly between the first level and the second level that is higher than the first level. This maximum value ILIMIT corresponds to a current limit that defines the maximum value of the drain current ID. Therefore, if the slope of the current limit variable signal Islope is appropriately set, the peak value of the drain current ID taking into account the overcurrent detection delay time Td when the error voltage signal VEAO becomes equal to or higher than the overcurrent protection reference voltage VLIMIT. Ip is substantially constant regardless of the input voltage VIN.

The operation of the switching power supply device configured as described above will be described below with reference to the drawings.
In FIG. 1, for example, an input voltage VIN (first DC voltage) obtained by rectifying and smoothing a commercial AC power supply is input to the input terminal of the switching power supply apparatus. The input voltage VIN is applied to the DRAIN terminal of the semiconductor device 100 via the primary winding 110A of the transformer 110.

  The regulator 2 supplies a current based on the input voltage VIN from the DRAIN terminal to the internal circuit power supply VDD, and also supplies a current based on the input voltage VIN to the capacitor 121 of the auxiliary power supply unit via the VCC terminal. The auxiliary power supply voltage VCC and the internal circuit power supply voltage VDD rise. When the voltage of the internal circuit power supply VDD reaches a certain value, the switching operation of the switching element 1 is started.

  When the switching operation of the switching element 1 is started, energy is supplied to each winding of the transformer 110, an AC voltage is generated in the secondary winding 110B and the auxiliary winding 110C, and a current flows.

  The current (secondary current) flowing through the secondary winding 110B is rectified and smoothed by the diode 130 and the capacitor 131, and supplied to the load 132 as DC power (output voltage VO and output current IO). The current flowing through the auxiliary winding 110 </ b> C is rectified and smoothed by the diode 120 and the capacitor 121 and used as an auxiliary power source for the semiconductor device 110. Since the polarity of the auxiliary winding 110C is the same as that of the secondary winding 110B, the auxiliary power supply voltage VCC is a voltage proportional to the output voltage VO.

  When the switching operation of the switching element 1 starts, the output voltage VO and the auxiliary power supply voltage VCC rise. When the auxiliary power supply voltage VCC increases, the voltage of the error voltage signal VEAO of the error amplifier 3 decreases. When the voltage of the error voltage signal VEAO decreases, the drain current control circuit 6 controls the drain current ID flowing through the switching element 1 to be small. By applying such negative feedback, the output voltage VO is stabilized. That is, the auxiliary power supply voltage VCC is also used for stabilizing the output voltage VO.

  The regulator 2 stops the current supply to the auxiliary power supply unit after starting the switching operation, and supplies the current based on the auxiliary power supply voltage VCC from the VCC terminal to the internal circuit power supply VDD when the auxiliary power supply voltage VCC becomes a certain value or more. Thereby, power consumption by the semiconductor device 100 during normal operation is kept low. On the other hand, when the auxiliary power supply voltage VCC falls below a certain value, a current based on the input voltage VIN is supplied from the DRAIN terminal to the internal circuit power supply VDD.

  The switching operation of the switching element 1 is performed by inputting an output signal from the flip-flop circuit 12 to the gate driver 14 via the NAND circuit 13. Either the clock signal set_1 from the oscillator 7 or the clock signal set_2 from the secondary duty limiting circuit 10 is input to the set terminal of the flip-flop circuit 12 via the clock signal selection circuit 11. On the other hand, the output signal of the drain current control circuit 6 is input to the reset terminal of the flip-flop circuit 12. The output signal of the drain current control circuit 6 is output when the element current detection signal VCL from the drain current detection circuit 5 reaches the lower one of the overcurrent protection reference voltage VLIMIT and the error voltage signal VEAO.

  The operation after the switching operation of the switching element 1 is started and the output voltage VO is stabilized differs depending on the state of the output current IO flowing through the load 132 as shown in FIG. Hereinafter, regarding the operation of the switching power supply apparatus, according to the order in which the load 132 changes from a light load to a heavy load, <(1) constant voltage region 1>, <(2) constant voltage region 2>, <(3) constant voltage The description will be made separately for each state of the boundary region between the region and the constant current region> and <(4) constant current region>.

  10 to 13, VCC is an auxiliary power supply voltage, VD is a voltage of a DRAIN terminal that is an input terminal of the switching element 1, VCL is an element current detection signal (drain current ID), VLIMIT is an overcurrent protection reference voltage, and VEAO. Is the error voltage signal, ID2 is the current flowing through the secondary diode 130, VTR is the TR terminal voltage, VC1 is the voltage of the capacitor 53 in the oscillator 7, set_1 is the clock signal output by the oscillator 7, and VC2 is the secondary duty limit The voltage of the capacitor 33 in the circuit 10, set_2 is a clock signal output from the secondary duty limiting circuit 10, set is a set signal input to the set terminal of the flip-flop circuit 12, and VG is a control terminal (gate terminal) of the switching element. Represents the voltage.

  However, in FIGS. 10 to 13, the peak value of the element current detection signal VCL (drain current ID) is actually larger than the overcurrent protection reference voltage VLIMIT or the error voltage signal VEAO due to the overcurrent detection delay time Td. It is omitted here.

<(1) Constant voltage region 1>
FIG. 10 is a timing chart showing the operation of each part in <constant voltage region 1> of the switching power supply device. This <constant voltage region 1> is a state in which the error voltage signal VEAO output from the error amplifier 3 is lower than the overcurrent protection reference voltage VLIMIT and the output current IO is lower than a predetermined value.

  In this <constant voltage region 1>, the current flowing through the secondary winding 110B is small and the period during which the secondary current flows is shortened. Therefore, the timing at which the output signal set_2 of the secondary duty limiting circuit 10 is output is the oscillator 7 Is faster than the output signal set_1. Therefore, the clock signal set_1 from the oscillator 7 is input to the set terminal of the flip-flop circuit 12 (set signal set).

  In <constant voltage region 1>, for example, when the output current IO flowing through the load 132 decreases, the output voltage VO and the auxiliary power supply voltage VCC slightly increase. As the auxiliary power supply voltage VCC increases, the voltage of the error voltage signal VEAO output from the error amplifier 3 decreases, and the drain current control circuit 6 controls the peak value Ip of the drain current ID flowing through the switching element 1 to decrease. Is done. Conversely, when the output current IO increases, the error voltage signal VEAO increases as the auxiliary power supply voltage VCC decreases, so that the peak value Ip of the drain current ID is controlled to increase.

  As described above, in the <constant voltage region 1>, the switching power supply apparatus uses the clock signal set_1 from the oscillator 7 as the set signal set, the element current detection signal VCL output from the drain current detection circuit 5, and the error amplifier 3. The output signal of the drain current control circuit 6 that is output by comparing the output error voltage signal VEAO is used as a reset signal, and the operation state is based on the fixed oscillation frequency peak current control method, and the oscillation frequency of the switching element 1 is kept constant. The energy supply amount to the primary winding 110A and the secondary winding 110B is changed by changing the ON time Ton of the switching element 1, and the output voltage VO is made constant.

  Further, in this way, in the <constant voltage region 1>, the output voltage VO is made constant by changing the on-time Ton of the switching element 1 while keeping the oscillation frequency of the switching element 1 constant, so that the ringing of the transformer is suppressed. Can be prevented.

<(2) Constant voltage region 2>
FIG. 11 is a timing chart showing the operation of each part in <constant voltage region 2> of the switching power supply device. This <constant voltage region 2> is a state in which the load becomes heavy, the output current IO becomes a predetermined value or more, and the error voltage signal VEAO output from the error amplifier 3 is higher than the overcurrent protection reference voltage VLIMIT. That is.

  When the output current IO flowing through the load 132 becomes larger than <constant voltage region 1> and the error voltage signal VEAO output from the error amplifier 3 becomes higher than the overcurrent protection reference voltage VLIMIT, the drain current control circuit 6 The element current detection signal VCL output from the current detection circuit 5 is compared with the overcurrent protection reference voltage VLIMIT, and when the element current detection signal VCL reaches the overcurrent protection reference voltage VLIMIT (a constant value), the switching element 1 is turned off. The signal to be output is output.

  Thereby, in the constant voltage region 2, the peak value Ip of the drain current ID flowing through the switching element 1 is fixed at a current value determined by the overcurrent protection reference voltage VLIMIT.

  In the <constant voltage region 2>, the current flowing through the secondary winding 110B reaches the maximum value, but the secondary current on-duty does not reach the constant value set by the secondary duty limiting circuit 10. Therefore, the output timing of the output signal set_2 from the secondary duty limiting circuit 10 is faster than the output signal set_1 from the oscillator 7. Therefore, the clock signal set_1 from the oscillator 7 is input to the set terminal of the flip-flop circuit 12 (set signal set).

further,
Error voltage signal VEAO> Overcurrent protection reference voltage VLIMIT
In this state, the oscillation frequency adjusting circuit 8 outputs a signal for increasing the oscillation frequency of the switching element 1 to the oscillator 7 according to the difference between the error voltage signal VEAO and the overcurrent protection reference voltage VLIMIT.

  As described above, in <constant voltage region 2>, the switching power supply device uses the clock signal set_1 from the oscillator 7 whose oscillation frequency increases as the load becomes heavier as the set signal set, and the element output from the drain current detection circuit 5 The output state of the drain current control circuit 6 that is output by comparing the current detection signal VCL and the overcurrent protection reference voltage VLIMIT is used as a reset signal, and the operation state by the oscillation frequency control method of the fixed peak current is obtained. By changing the oscillation frequency, the amount of energy supplied to the primary winding 110A and the secondary winding 110B is changed to make the output voltage VO constant.

  When the output current IO flowing through the load 132 increases, the oscillation frequency of the switching element 1 increases. However, while the output signal D2_on from the secondary current off detection circuit 9 to the oscillator 7 is a high level signal, Since the clock signal set_1 is not output, the next turn-on pulse signal is generated after the secondary current has finished flowing. That is, the switching power supply device is in a discontinuous mode operation.

<(3) Boundary region between constant voltage region and constant current region>
FIG. 12 is a timing chart showing the operation of each part in <the boundary region between the constant voltage region and the constant current region> of the switching power supply device. The <boundary region between the constant voltage region and the constant current region> is a first clock signal output from the oscillator 7 when the error voltage signal VEAO output from the error amplifier 3 is higher than the overcurrent protection reference voltage VLIMIT. This is a state in which the timings of the set_1 and the second clock signal set_2 output from the secondary duty limiting circuit 10 are the same, that is, a state in which the on-duty of the secondary current has reached the set value.

  In <constant voltage region 2>, the peak value Ip of the drain current ID flowing through the switching element 1 is fixed at a current value determined by the overcurrent protection reference voltage VLIMIT, and the clock signal set_1 is increased as the load becomes heavier by the oscillation frequency adjusting circuit 8. The oscillation frequency is controlled to be high. Therefore, in <constant voltage region 2>, when the output current IO flowing through the load 132 increases, the oscillation frequency of the clock signal set_1 increases and the secondary current on-duty increases.

  When the secondary current on-duty becomes a constant value set by the secondary duty limiting circuit 10, the timings of the clock signal set_2 from the secondary duty limiting circuit 10 and the clock signal set_1 from the oscillator 7 become equal. Thus, the region where the clock signal input to the clock signal selection circuit 11 switches from the clock signal set_1 to the clock signal set_2, that is, the moment when the secondary current on-duty reaches a constant value set by the secondary duty limiting circuit 10 is reached. The region is <the boundary region between the constant voltage region and the constant current region>.

Since the switching power supply device is in the discontinuous mode operation, the energy supplied to the load 132 includes the output voltage VO, the output current IO, the inductance Lp of the primary winding 110A of the transformer 110, and the drain flowing through the switching element 1. From the peak value Ip of the current ID and the oscillation frequency fosc of the switching element 1,
VO × IO = (1/2) × Lp × Ip × Ip × fosc (5)
It is expressed.

  Here, in this <boundary region between the constant voltage region and the constant current region>, the error voltage signal VEAO output from the error amplifier 3 is higher than the overcurrent protection reference voltage VLIMIT, and therefore the peak value of the drain current ID. Ip is fixed at a current value determined by the overcurrent protection reference voltage VLIMIT. Further, the current value when the switching element 1 is turned off and the current starts to flow through the secondary winding 110B, that is, the peak value of the secondary current is the turn ratio of the primary winding 110A and the secondary winding 110B of the transformer 110. Therefore, the peak value of the secondary current is also constant.

  Furthermore, if the error voltage signal VEAO is higher than the overcurrent protection reference voltage VLIMIT, the current limit ILIMIT that defines the maximum value of the drain current ID becomes a saw-shaped waveform that changes linearly as shown in FIG. Considering the overcurrent detection delay time Td, the peak value Ip of the drain current ID is substantially constant regardless of the input voltage VIN.

  Further, when the output voltage VO is constant, the slope of the secondary current is also constant, so that the period during which the secondary current flows when the peak value of the secondary current is constant is always constant. Therefore, in this <boundary region between the constant voltage region and the constant current region>, the period during which the secondary current flows is always constant. As a result, in <the boundary region between the constant voltage region and the constant current region>, the oscillation frequency fosc of the switching element 1 is always a constant value.

  On the other hand, when the inductance Lp of the primary winding 110A of the transformer 110 changes, the slope of the secondary current also changes. When the peak value of the secondary current is constant, as the inductance Lp increases, the slope of the secondary current increases and the period during which the secondary current flows becomes longer. As a result, the oscillation frequency fosc of the switching element 1 is lowered. On the contrary, when the inductance Lp is reduced, the slope of the secondary current is reduced and the period during which the secondary current flows is shortened. As a result, the oscillation frequency fosc of the switching element 1 is increased.

  As described above, in the <boundary region between the constant voltage region and the constant current region>, the product of the inductance Lp of the primary winding 110A of the transformer 110 and the oscillation frequency fosc of the switching element 1 is constant. ), The output current IO is constant. Therefore, the output current IO in <the boundary region between the constant voltage region and the constant current region> is not affected by the oscillation frequency, the variation in the inductance value of the transformer, the overcurrent detection delay time Td, and the input voltage VIN.

<(4) Constant current region>
FIG. 13 is a timing chart showing the operation of each part in the <constant current region> of the switching power supply device. This <constant current region> means that the error voltage signal VEAO output from the error amplifier 3 is higher than the overcurrent protection reference voltage VLIMIT, and the clock signal set_2 output from the secondary duty limiting circuit 10 determines the switching element 1 This is a region where a switching operation is performed.

  When the load is increased so that the output current IO flowing through the load 132 is larger than the output current IO in the <boundary region between the constant voltage region and the constant current region>, the peak value of the secondary current and the secondary current on as described above Since the duty is constant and the energy supplied to the secondary winding 110B of the transformer 110 has already become maximum, the output voltage VO decreases.

  When the output voltage VO decreases, the slope of the secondary current increases and the period during which the secondary current flows increases. Therefore, the timing at which the output signal set_2 from the secondary duty limiting circuit 10 is output is the output from the oscillator 7. It is slower than the signal set_1. Therefore, the clock signal selection circuit 11 outputs the second clock signal set_2. Since the second clock signal set_2 is output so that the secondary current on-duty is constant, the oscillation frequency of the switching element 1 is lowered while the secondary current on-duty is controlled to a constant value. Therefore, as the load becomes heavier, control is performed so that the oscillation frequency of the switching element 1 decreases while the peak value of the secondary current and the secondary current on-duty remain constant.

Here, when the secondary current on-duty is a constant value, the output current IO is expressed by the following equation, where the secondary current on-duty is “D2” and the peak value of the secondary current is “I2p”.
IO = (1/2) × I2p × D2 (6)
The peak value I2p of the secondary current is constant because the peak value Ip of the drain current ID flowing through the switching element 1 is controlled by the current value determined by the overcurrent protection reference voltage VLIMIT. Further, since the current limit ILIMIT that defines the maximum value of the drain current ID changes with time as shown in FIG. 8, the peak value Ip of the drain current ID depends on the input voltage VIN in consideration of the overcurrent detection delay time Td. Almost constant.

  Therefore, a constant output current IO can be obtained regardless of variations in the inductance Lp of the primary winding 110A of the transformer 110, the oscillation frequency fosc of the switching element 1, the overcurrent detection delay time Td, and the input voltage VIN. High-accuracy constant current drooping characteristics can be obtained.

  As described above, according to the present embodiment, the secondary-side constant current control circuit, the output current detection resistor, and the photocoupler can be dispensed with, and the low cost, the minimum number of parts, and the minimum power loss are sufficiently accurate. A constant current drooping characteristic can be realized. Therefore, a switching power supply for a charger with sufficient accuracy can be configured with a small number of parts, and the cost, size and energy saving of the switching power supply for a charger can be realized.

  Further, the peak value Ip of the drain current ID flowing through the switching element is set to a constant value, the secondary current on-duty is controlled to a constant value, and a current limit ILIMIT that defines the maximum value of the drain current ID is as shown in FIG. Since the time changes, if the slope of the current limit variable signal Islope is appropriately set, the peak value Ip of the drain current ID when the overcurrent detection delay time Td is taken into consideration becomes almost constant regardless of the input voltage VIN. The variation in the oscillation frequency and the inductance of the transformer does not affect the constant current value of the output current IO, and a highly accurate constant current drooping characteristic with a very small total variation can be realized.

  Furthermore, instead of reducing the peak value Ip of the drain current ID, the peak value Ip is constant, and the constant current drooping characteristic is realized by changing the oscillation frequency fosc to make the secondary current on-duty constant. The on-time Ton of the switching element does not change, and the on-time Ton does not become short in the constant current region. Therefore, the conventional problem that the peak value Ip cannot be controlled without being affected by the input voltage VIN when the on-time Ton is shortened can be avoided, and even when the output voltage VO decreases in the constant current region, As described above, the output current IO is not changed by the input voltage VIN.

  Further, the switching element and the control circuit can be provided in the same semiconductor and can be easily unified. Of course, only the control circuit can be provided in the same semiconductor for easy integration. Therefore, by providing the main circuit components in a single semiconductor, the number of components for configuring the circuit can be reduced, and the power supply device can be easily reduced in size, weight, and cost. Can do.

  In addition, the output voltage VO is kept constant until the secondary current on-duty reaches a constant value, and when the secondary current on-duty reaches a certain value, the output current IO is kept constant. Either can be realized.

  Further, since the constant current drooping characteristic is realized by controlling the oscillation frequency of the switching element 1, the constant voltage characteristic of <constant voltage region 2> also controls the oscillation frequency of the switching element 1 as in the present embodiment. If this is realized, the switching from the constant voltage region to the constant current region becomes smooth.

  In the present embodiment, by changing the detected value of the drain current flowing through the switching element 1, a current limit that linearly changes during the ON period of the switching element as shown in FIG. 8 is realized. The means may be different as long as a current limit that changes from the first level to the second level higher than the first level during the ON period can be realized.

  FIG. 14 shows another configuration example of the semiconductor device 100 that realizes a current limit that linearly changes during the ON period of the switching element. However, the same members as those described with reference to FIG.

  This semiconductor device (control circuit) 100 changes the overcurrent protection reference voltage input as the reference voltage to the drain current control circuit 6 instead of the detected value of the drain current flowing through the switching element 1 to turn on the switching element. A current limit is realized that changes from a first level to a higher second level over a period of time.

  That is, in the semiconductor device 100 shown in FIG. 14, the drain current detection variable circuit 4 is omitted and the current limit variable circuit 15 is added, compared to the semiconductor device 100 shown in FIG. The current limit variable circuit 15 receives the output signal (FFout signal) of the flip-flop circuit 12 and the overcurrent protection reference voltage VLIMIT, and the overcurrent protection reference voltage VLIMIT changes according to the timing when the switching element is turned on and turned off. ′ Is generated and output to the drain current control circuit 6. That is, the current limit variable circuit 15 has a function of generating an overcurrent protection reference voltage VLIMIT ′ that changes linearly as shown in FIG. 15 based on the overcurrent protection reference voltage VLIMIT and the FFout signal that are constant values. Have.

  When the error voltage signal VEAO is higher than the overcurrent protection reference voltage VLIMIT ′, the switching element 1 is turned off when the element current detection signal VCL reaches the overcurrent protection reference voltage VLIMIT ′. Therefore, as shown in FIG. By changing the reference voltage VLIMIT ′, a time change of the current limit ILIMIT as shown in FIG. 15 can be obtained.

  As described above, the semiconductor device 100 shown in FIG. 14 changes the overcurrent protection reference voltage (reference value for determining the current limit ILIMIT) that is input to the drain current control circuit 6 as the reference voltage over time, thereby changing the switching element 1. A current limit that changes from the first level to a second level higher than the first level during the ON period can be realized, and the same effect as when the semiconductor device 100 shown in FIG. 2 is used can be exhibited. it can.

  According to the power supply regulation circuit of the present invention, a sufficiently accurate constant current drooping characteristic can be realized with a low cost and a minimum number of parts, so that a charger for portable devices such as a mobile phone and a digital still camera, etc. Useful for.

The block diagram which shows the example of 1 structure of the switching power supply device in embodiment of this invention 1 is a block diagram showing a configuration example of a semiconductor device for controlling a switching power supply that constitutes the switching power supply of the embodiment The block diagram which shows the example of 1 structure of the secondary current OFF detection circuit and secondary duty limiting circuit in the switching power supply device of the embodiment FIG. 3 is a block diagram showing a configuration example of a clock signal selection circuit in the switching power supply device according to the embodiment. The block diagram which shows the example of 1 structure of the oscillator and oscillation frequency adjustment circuit in the switching power supply device of the embodiment The block diagram which shows one structural example of the drain current detection variable circuit in the switching power supply device of the embodiment The block diagram which shows the example of 1 structure of the drain current detection circuit in the switching power supply device of the embodiment The figure for demonstrating operation | movement of the drain current detection variable circuit in the switching power supply device of the embodiment The figure which shows the output voltage-output current characteristic in the switching power supply device of the embodiment The figure which shows the time chart showing operation | movement of <constant voltage area | region 1> in the switching power supply device of the embodiment The figure which shows the time chart showing operation | movement of <constant voltage area | region 2> in the switching power supply device of the embodiment The figure which shows the time chart showing the operation | movement of the <boundary area | region of a constant voltage area | region and a constant current area | region> in the switching power supply device of the embodiment The figure which shows the time chart showing operation | movement of the <constant current area> in the switching power supply device of the embodiment The block diagram which shows one structural example of the semiconductor device for switching power supply device which comprises the switching power supply device in other embodiment of this invention The figure for demonstrating operation | movement of the current limit variable circuit in the switching power supply device of the embodiment Block diagram showing the configuration of a conventional switching power supply device The figure which shows the timing chart showing the operation | movement of each part in the conventional switching power supply device (A) is a diagram showing a waveform of the drain current ID when the current limit ILIMIT is constant with respect to an arbitrary input voltage VIN, and (b) is a waveform of the drain current ID when the current limit ILIMIT changes linearly with time. FIG. 8C is a diagram showing a waveform of the drain current ID when the peak value Ip of the drain current ID flowing through the switching element in the conventional switching power supply device is reduced. (A) is a figure which shows the relationship between output voltage VO and output current IO at the time of using the same current limit ILIMIT for arbitrary input voltages in the conventional switching power supply device, (b) is linear in the conventional switching power supply device. The figure which shows the relationship between the output voltage VO and the output current IO at the time of using the current limit ILIMIT which changes to time Waveform diagram of current limit ILIMIT in a conventional switching power supply device The figure for demonstrating the relationship between the peak value of current limit ILIMIT and drain current ID

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Switching element 2 Regulator 3 Error amplifier 4 Drain current detection variable circuit 5 Drain current detection circuit 6 Drain current control circuit 7 Oscillator 8 Oscillation frequency adjustment circuit 9 Secondary current off detection circuit 10 Secondary duty control circuit 11 Clock signal selection circuit 12 Flip-flop circuit 13 NAND circuit 14 Gate driver 15 Current limit variable circuit 21 Comparator 22, 23 One-pulse signal generation circuit 24 Flip-flop circuit 25 Inverter circuit 26, 35 AND circuit 27 Constant current source 28, 29, 30 Switch 31, 32 Nch MOSFET
33 Capacitor 34 Comparator 36 One-pulse signal generation circuit 41, 45 One-pulse signal generation circuit 42, 43 Flip-flop circuit 44 AND circuit 51 Comparator 52 Reference voltage source 53 Capacitor 54 One-pulse signal generation circuit 55 Inverter circuit 56 AND circuit 57 Constant current source 58, 59, 60 Switch 61, 62 Nch MOSFET
63, 64 NPN transistor 65, 66 Resistor 67, 68, 69, 70, 73, 74 Pch MOSFET
71, 72 Nch MOSFET
81 Charging / discharging circuit 82 Capacitor 83 PNP transistor 84 NPN transistor 85 Resistor 86 Constant current source 87, 88 PchMOSFET
89, 90 Nch MOSFET
91, 92 Resistor 100 Semiconductor device for switching power supply control 110 Transformer 110A Primary winding 110B Secondary winding 110C Auxiliary winding 120 Diode 121 Capacitor 122 Diode 123, 124 Resistor 130 Diode 131 Capacitor 132 Load 200 Control circuit 210 Switching element 220 Transformer 220A Primary winding 220B Secondary winding 220C Auxiliary winding 231 Diode 232 Capacitor 233 Load 241 Diode 242 Capacitor 243 Resistor 244 Capacitor 250 Resistor

Claims (12)

A transformer having a first winding to which an input voltage is input and a second winding for generating an output voltage;
It includes three terminals of a first terminal, a second terminal, and a control terminal, and oscillates so as to electrically couple or separate the first and second terminals in response to a control signal received at the control terminal. A switching element for performing on / off control of the current flowing through the first winding,
A control circuit for generating the control signal;
And controlling the oscillation of the switching element to control the amount of energy supplied to the first and second windings to supply a constant output current to the load connected to the second winding Power supply regulation circuit,
The control circuit includes:
An element current detection function for detecting an element current flowing through the switching element;
During a period in which the switching element couples the first and second terminals, a current limit that defines a maximum value of the element current is set to a first level and a second level that is greater than the first level. Current limit variable function to change between
A function of outputting a signal for turning off the switching element when the element current reaches the current limit changing between the first and second levels;
A function of detecting an on-duty of a secondary current flowing through the second winding and outputting a signal for turning on the switching element so that the on-duty of the secondary current becomes a constant value;
And a function of generating the control signal based on a signal for turning on the switching element and a signal for turning off the switching element.   2. The power supply regulation circuit according to claim 1, wherein the variable current limit function changes a detection value of the element current by the element current detection function so that the switching element connects the first and second terminals. A power supply regulation circuit, wherein the current limit is changed between the first level and the second level during the coupling period.   2. The power supply regulation circuit according to claim 1, wherein the current limit variable function is configured such that the switching element couples the first and second terminals by changing a reference value for determining the current limit. 3. A power supply regulation circuit, wherein the current limit is changed between the first level and the second level during a period. A power supply regulation circuit according to any one of claims 1 to 3,
The transformer further includes a third winding for detecting a voltage generated in the second winding,
The power supply regulation circuit, wherein the control circuit detects an on-duty of the secondary current based on a voltage generated in the third winding. A power supply regulation circuit according to any one of claims 1 to 4,
The control circuit further has a function of changing the energy supply amount so that the output voltage becomes constant when the on-duty of the secondary current is a certain value or less.   When the on-duty of the secondary current is a certain value or less, the control circuit changes the energy supply amount by changing the oscillation frequency of the switching element to make the output voltage constant. The power supply regulation circuit according to claim 5.   When the on-duty of the secondary current is a predetermined value or less, the control circuit changes a period during which the switching element couples the first and second terminals while keeping the oscillation frequency of the switching element constant. 6. The power supply regulation circuit according to claim 5, wherein the output voltage is made constant by changing the energy supply amount.   When the on-duty of the secondary current is less than a predetermined value and the output current is smaller than a predetermined value, the control circuit keeps the oscillation frequency of the switching element constant and the switching element is the first and second The output voltage is made constant by changing the energy supply amount by changing a period for coupling the terminals of the secondary current, and when the on-duty of the secondary current is a predetermined value or less and the output current is a predetermined value or more, 6. The power supply regulation circuit according to claim 5, wherein the output voltage is made constant by changing the energy supply amount by changing an oscillation frequency of a switching element.   The power supply regulation circuit according to claim 1, wherein the control circuit is formed on the same semiconductor substrate.   9. The power supply regulation circuit according to claim 1, wherein the switching element and the control circuit are formed on the same semiconductor substrate.   9. A semiconductor device, wherein the control circuit according to claim 1 is formed on the same semiconductor substrate. 9. A semiconductor device, wherein the switching element according to claim 1 and the control circuit are formed on the same semiconductor substrate.

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