JP2006339556A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably perform element isolation of a semiconductor layer formed on an insulator while suppressing an increase in the number of steps and improve an effect of suppressing current leakage by a parasitic transistor.
By performing isotropic etching of the etch stop layer 4, the etch stop layer 4 is reduced so that the shoulder of the upper end portion of the single crystal semiconductor layer 3 is exposed, and the sidewall of the single crystal semiconductor layer 3 is formed. After the insulating film 5 is formed on the etch stop layer 4 so as to be covered, the insulating film 5 is etched back until the etch stop layer 4 is exposed, thereby exposing the single crystal semiconductor layer exposed from the etch stop layer 4 3 and the side walls 5 a and 5 b are formed on the side walls of the single crystal semiconductor layer 3.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a method for manufacturing a field effect transistor formed on a (Silicon On Insulator) substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted.

  Here, when the SOI transistor is formed in the SOI layer, there is a method of using a mesa isolation method for element isolation. This mesa isolation method has many advantages such as no transistor is formed between adjacent semiconductor layers because transistors are formed in an island-shaped semiconductor layer that is completely isolated from the surrounding semiconductor layers. It has been reported. However, when element isolation is performed by the mesa isolation method, an inversion layer serving as a channel of the parasitic transistor is formed on the side surface and corner portion of the isolated SOI layer. For this reason, in the Vg-Id characteristic of the MOS transistor formed in the SOI layer, even when the gate voltage is relatively low, a leak current flows in the source / drain region, and an abnormality may be observed in the rising characteristic of the current. .

Further, in Patent Document 1, when element isolation is performed by a mesa isolation method, in order to prevent a parasitic transistor from being formed on the side surface or corner portion of the isolated SOI layer, SiO ₂ is formed at the mesa isolation end. A method of forming a sidewall made of is disclosed.
Further, Patent Document 2 discloses that a mesa isolation method is used by etching the SOI layer using a nitride film formed on the SOI layer and a polysilicon side wall formed on the sidewall of the nitride film as a mask. A method for rounding the edge of the isolated SOI layer is disclosed.
JP-A-8-335702 JP 2000-91580 A

However, the method disclosed in Patent Document 1 has a problem in that the effect of suppressing current leakage due to a parasitic transistor may not be sufficiently obtained because the edge of the separated SOI layer remains as it is.
Also, in the method disclosed in Patent Document 2, a nitride film is formed on the SOI layer and the sidewall of the nitride film is made of polysilicon in order to round the edge of the SOI layer that is element-isolated by the mesa isolation method. Since the SOI layer needs to be etched after forming the sidewall, there is a problem in that the number of steps is increased.

  Accordingly, an object of the present invention is to stably perform element isolation of a semiconductor layer formed on an insulator while suppressing an increase in the number of processes, and to improve an effect of suppressing current leakage by a parasitic transistor. And a manufacturing method of the semiconductor device.

In order to solve the above problem, according to a semiconductor device of one embodiment of the present invention, a single crystal semiconductor layer formed in a mesa shape over an insulating layer and an upper end portion of the single crystal semiconductor layer are rounded. The formed rounding portion, the sidewall formed on the side wall of the single crystal semiconductor layer and disposed below the rounding portion, the gate electrode formed on the single crystal semiconductor layer, and the gate electrode sandwiched between Thus, even when the semiconductor layer is separated into a mesa shape, the side wall of the single crystal semiconductor layer under the gate electrode is side-sided. It can be covered with a wall, and the upper end portion of the single crystal semiconductor layer can be rounded. Therefore, it is possible to form a transistor on an island-like semiconductor layer completely isolated from the surrounding semiconductor layer while preventing the formation of a parasitic transistor on the side surface of the mesa-isolated semiconductor layer. In addition, it is possible to stably perform element isolation of the semiconductor layer formed on the substrate, and to suppress current leakage due to the parasitic transistor. As a result, it is possible to increase the operation speed, lower voltage, and lower power consumption of the field effect transistor while suppressing deterioration of the characteristics of the field effect transistor, and causes a phenomenon such as latch-up. Without any problem, a plurality of SOI transistors can be integrated on the same substrate.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of preparing a substrate in which a single crystal semiconductor layer is formed over an insulating layer, and an etch stop layer is formed over the single crystal semiconductor layer. A step of etching the single crystal semiconductor layer on which the etch stop layer is formed in a mesa shape, and isotropic etching of the etch stop layer, whereby the shoulder of the upper end portion of the single crystal semiconductor layer is Reducing the etch stop layer to be exposed, forming an insulating film on the reduced etch stop layer so as to cover the single crystal semiconductor layer, and until the etch stop layer is exposed By etching back the insulating film, the shoulder of the upper end portion of the single crystal semiconductor layer exposed from the etch stop layer is rounded, and the single crystal semiconductor layer Forming a sidewall on the wall; removing the etch stop layer on the single crystal semiconductor layer; forming a gate insulating film on the single crystal semiconductor layer with a rounded shoulder at the upper end; Forming a gate electrode on the gate insulating film; and forming a source / drain layer disposed so as to sandwich the gate electrode in the single crystal semiconductor layer.

  Thus, even when the semiconductor layer is separated into a mesa shape, the sidewall of the single crystal semiconductor layer under the gate electrode can be covered with the sidewall in the same manufacturing process, and the upper end of the single crystal semiconductor layer can be covered. The part can be rounded. For this reason, while suppressing an increase in the number of steps, it is possible to stably perform element isolation of the semiconductor layer formed on the insulator, and to improve the effect of suppressing current leakage by the parasitic transistor. While suppressing deterioration of transistor characteristics, it is possible to increase the operation speed, lower voltage, and lower power consumption of a field effect transistor, and it is possible to achieve a plurality of SOI without causing a phenomenon such as latch-up. Transistors can be integrated on the same substrate.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of preparing a substrate in which a single crystal semiconductor layer is formed over an insulating layer, and an etch stop layer is formed over the single crystal semiconductor layer. A step of etching the single crystal semiconductor layer on which the etch stop layer is formed in a mesa shape, and isotropic etching of the etch stop layer, whereby the shoulder of the upper end portion of the single crystal semiconductor layer is Reducing the etch stop layer so as to be exposed, performing isotropic etching of the single crystal semiconductor layer using the etch stop layer as a mask, rounding an end of the single crystal semiconductor layer, and Removing the etch stop layer on the single crystal semiconductor layer; forming a gate insulating film on the single crystal semiconductor layer with the rounded end; and the gate insulating film Characterized in that it comprises a step of forming a gate electrode, and forming a source / drain layer disposed so as to sandwich the gate electrode on the monocrystalline semiconductor layer.

  Accordingly, even when the semiconductor layer is separated in a mesa shape, the end portion of the single crystal semiconductor layer can be rounded by performing isotropic etching of the single crystal semiconductor layer using the etch stop layer as a mask. Therefore, it is possible to stably isolate the semiconductor layer formed on the insulator while suppressing an increase in the number of steps, and to suppress current leakage due to the parasitic transistor.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of preparing a substrate in which a single crystal semiconductor layer is formed over an insulating layer, and an antioxidant film is formed over the single crystal semiconductor layer. A step of etching the single crystal semiconductor layer on which the antioxidant film is formed in a mesa shape, and isotropic etching of the antioxidant film, so that the shoulder of the upper end portion of the single crystal semiconductor layer is Shrinking the antioxidant film so as to be exposed, performing thermal oxidation of the single crystal semiconductor layer using the antioxidant film as a mask, rounding an end of the single crystal semiconductor layer, and the single crystal Removing an anti-oxidation film on the semiconductor layer; forming a gate insulating film on the single crystal semiconductor layer with rounded ends; forming a gate electrode on the gate insulating film; The gate electrode The source / drain layer disposed so as to sandwich, characterized in that it comprises a step of forming the single crystal semiconductor layer.

  Accordingly, even when the semiconductor layer is separated into a mesa shape, the end portion of the single crystal semiconductor layer can be rounded by performing thermal oxidation of the single crystal semiconductor layer using the antioxidant film as a mask. Therefore, it is possible to stably isolate the semiconductor layer formed on the insulator while suppressing an increase in the number of steps, and to suppress current leakage due to the parasitic transistor.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
In FIG. 1A, an insulating layer 2 is formed on a semiconductor substrate 1, and a single crystal semiconductor layer 3 is formed on the insulating layer 2. For example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, or ZnSe can be used as the material of the semiconductor substrate 1 and the single crystal semiconductor layer 3. For example, SiO ₂ , SiON, or Si ₃ N ₄ can be used. In addition, as the semiconductor substrate 1 on which the semiconductor layer 3 is formed on the insulating layer 2, for example, an SOI substrate can be used. As the SOI substrate, a SIMOX (Separation by Implanted Oxgen) substrate, a bonded substrate, or laser annealing is used. A substrate or the like can be used. In addition to the semiconductor substrate 1, an insulating substrate such as sapphire, glass or ceramic may be used. Then, an etch stop layer 4 is formed on the single crystal semiconductor layer 3 by a method such as CVD. For example, a silicon oxide film can be used as the material of the etch stop layer 4.

Next, as shown in FIG. 1B, the etch stop layer 4 and the single crystal semiconductor layer 3 are patterned by using a photolithography technique and an etching technique, so that the etch stop layer 4 is formed on the single crystal semiconductor layer 3. The single crystal semiconductor layer 3 over the insulating layer 2 is processed into a mesa shape while remaining.
Next, as shown in FIG. 1C, the etch stop layer 4 is reduced by performing isotropic etching of the etch stop layer 4 so that the shoulder of the upper end portion of the single crystal semiconductor layer 3 is exposed. Here, as the isotropic etching of the etch stop layer 4, for example, when the etch stop layer 4 is a silicon oxide film, wet etching using a hydrofluoric acid-based etchant may be performed, or CF ₄ may be used. Plasma etching using gas may be performed.

  Next, as shown in FIG. 2A, an insulating film 5 is formed on the etch stop layer 4 so as to cover the sidewall of the single crystal semiconductor layer 3 by a method such as CVD. For example, a silicon nitride film can be used as the insulating film 5. Here, when the insulating film 5 is formed on the etch stop layer 4, the thickness of the insulating film 5 is made thinner on the shoulder of the upper end portion of the single crystal semiconductor layer 3 than on the flat portion on the etch stop layer 4. be able to. In order to effectively reduce the thickness of the insulating film 5 as compared with the flat portion on the etch stop layer 4, HDP (High Density Plasma) -CVD is performed at the same time as the insulating film is sputtered with Ar. As described above, it is preferable to use a method in which the insulating film 5 is hardly formed on the shoulder of the upper end portion of the single crystal semiconductor layer 3.

Next, as shown in FIG. 2B, the insulating film 5 is etched back until the etch stop layer 4 is exposed, whereby the shoulder of the upper end portion of the single crystal semiconductor layer 3 exposed from the etch stop layer 4 is covered. While rounding, side walls 5 a and 5 b are formed on the side walls of the single crystal semiconductor layer 3.
Here, for example, when the single crystal semiconductor layer 3 is made of silicon, the etch stop layer 4 is made of a silicon oxide film, and the insulating film 5 is made of a silicon nitride film, a fluorocarbon such as CH ₂ F ₂ or CH ₃ F is used as an etching gas. It is preferable to use this gas. Thereby, the etching rate of the single crystal semiconductor layer 3 and the insulating film 5 can be ensured with respect to the etch stop layer 4, and the etching of the etch stop layer 4 can be suppressed and the single crystal semiconductor layer 3 and the insulating film 5 can be reduced. It can be etched.

  Next, as shown in FIG. 2C, after the etch stop layer 4 is removed, the single crystal semiconductor layer 3 is thermally oxidized to form the gate insulating film 6 on the single crystal semiconductor layer 3. Then, a polycrystalline silicon layer is formed on the single crystal semiconductor layer 3 on which the gate insulating film 6 is formed by a method such as CVD, and the polycrystalline silicon layer is patterned using a photolithography technique and a dry etching technique. As a result, the gate electrode 7 is formed on the gate insulating film 5. Then, ion implantation of impurities such as As, P, and B is performed in the single crystal semiconductor layer 3 using the gate electrode 7 as a mask, so that the source / drain layers arranged so as to sandwich the gate electrode 7 are formed in the single crystal semiconductor. Layer 3 is formed.

  Thereby, in the same manufacturing process, the side wall of the single crystal semiconductor layer 3 under the gate electrode 7 can be covered with the sidewalls 5a and 5b, and the upper end portion of the single crystal semiconductor layer 3 can be rounded. . For this reason, even when the single crystal semiconductor layer 3 is separated in a mesa shape, a parasitic transistor is prevented from being formed on the side surface of the mesa-isolated single crystal semiconductor layer 3 while suppressing an increase in the number of steps. In addition, a transistor can be formed in the island-shaped single crystal semiconductor layer 3 that is completely isolated from the surrounding semiconductor layers, and element isolation of the single crystal semiconductor layer 3 formed over the insulator 2 can be stabilized. Thus, current leakage due to the parasitic transistor can be suppressed. As a result, it is possible to increase the operation speed, lower voltage, and lower power consumption of the field effect transistor while suppressing deterioration of the characteristics of the field effect transistor, and causes a phenomenon such as latch-up. It is possible to integrate a plurality of SOI transistors on the same semiconductor substrate 1 without any problem.

  In the above-described embodiment, the method of using the silicon oxide film as the material of the etch stop layer 4 and the silicon nitride film as the material of the insulating film 5 has been described, but the silicon nitride film and the insulating film 5 are used as the material of the etch stop layer 4. A silicon oxide film may be used as the material. In the embodiment described above, the shoulder of the upper end portion of the single crystal semiconductor layer 3 is rounded using the etch stop layer 4 in FIG. 1C as a mask, and the side walls 5 a and 5 b are formed on the side walls of the single crystal semiconductor layer 3. Although the method for performing the above is described, the shoulder of the upper end portion of the single crystal semiconductor layer 3 is formed using the etch stop layer 4 of FIG. 1C as a mask without forming the side walls 5a and 5b on the side walls of the single crystal semiconductor layer 3. It may be simply rounded.

3 and 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the second embodiment of the present invention.
In FIG. 3A, an insulating layer 22 is formed on a semiconductor substrate 21, and a single crystal semiconductor layer 23 is formed on the insulating layer 22. Then, an antioxidant layer 24 is formed on the single crystal semiconductor layer 23 by a method such as CVD. As the antioxidant layer 24, for example, a silicon nitride film or the like can be used.

Next, as shown in FIG. 3B, the antioxidant film 24 and the single crystal semiconductor layer 23 are patterned by using a photolithography technique and an etching technique to form the antioxidant film 24 on the single crystal semiconductor layer 23. The single crystal semiconductor layer 23 over the insulating layer 22 is processed into a mesa shape while remaining.
Next, as shown in FIG. 3C, the antioxidant film 24 is reduced so that the shoulder of the upper end portion of the single crystal semiconductor layer 23 is exposed by performing isotropic etching of the antioxidant film 24.

  Next, as shown in FIG. 4A, the single crystal semiconductor layer 23 is thermally oxidized using the antioxidant film 24 as a mask to oxidize the sidewall of the single crystal semiconductor layer 23 exposed from the antioxidant film 24. A film 25 is formed. Here, since the shoulder of the upper end portion of the single crystal semiconductor layer 23 is exposed from the antioxidant film 24, an oxide film 25 is also formed on the shoulder of the upper end portion of the single crystal semiconductor layer 23, and the single crystal semiconductor layer 23 The upper shoulder can be rounded. Note that in the case of performing thermal oxidation of the single crystal semiconductor layer 23, dry oxidation is preferably performed at a high temperature of 1100 ° C. or higher, whereby the shoulder of the upper end portion of the single crystal semiconductor layer 23 can be efficiently rounded.

  Next, as shown in FIG. 4B, after removing the antioxidant film 24 and the oxide film 25, the single crystal semiconductor layer 23 is thermally oxidized, whereby the gate insulating film 26 is formed on the single crystal semiconductor layer 23. Form. Then, a polycrystalline silicon layer is formed on the single crystal semiconductor layer 23 on which the gate insulating film 26 is formed by a method such as CVD, and the polycrystalline silicon layer is patterned by using a photolithography technique and a dry etching technique. As a result, the gate electrode 27 is formed on the gate insulating film 26. Then, ion implantation of impurities such as As, P, and B is performed in the single crystal semiconductor layer 23 using the gate electrode 27 as a mask, so that the source / drain layers arranged so as to sandwich the gate electrode 27 are formed in the single crystal semiconductor. Layer 23 is formed.

  Accordingly, even when the single crystal semiconductor layer 23 is separated into a mesa shape, the end portion of the single crystal semiconductor layer 23 can be rounded by performing thermal oxidation of the single crystal semiconductor layer 23 using the antioxidant film 24 as a mask. . Therefore, it is possible to stably perform element isolation of the single crystal semiconductor layer 23 formed over the insulating layer 22 while suppressing an increase in the number of steps, and to suppress current leakage due to a parasitic transistor.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  1, 21 Semiconductor substrate, 2, 22 Insulating layer, 3, 23 Single crystal semiconductor layer, 4 Etch stop layer, 5 Insulating film, 5a, 5b Side wall, 6, 26 Gate insulating film, 7, 27 Gate electrode, 24 Oxidation Prevention film, 25 oxide film

Claims (4)

A single crystal semiconductor layer formed in a mesa shape on the insulating layer;
A rounded portion formed to round the upper end of the single crystal semiconductor layer;
A sidewall formed on a side wall of the single crystal semiconductor layer and disposed below the rounded portion;
A gate electrode formed on the single crystal semiconductor layer;
A semiconductor device comprising: a source / drain layer formed in the single crystal semiconductor layer so as to sandwich the gate electrode. Preparing a substrate having a single crystal semiconductor layer formed over an insulating layer;
Forming an etch stop layer on the single crystal semiconductor layer;
Etching the single crystal semiconductor layer in which the etch stop layer is formed into a mesa shape;
Performing the isotropic etching of the etch stop layer to reduce the etch stop layer so that the shoulder of the upper end portion of the single crystal semiconductor layer is exposed;
Forming an insulating film on the reduced etch stop layer so as to cover the single crystal semiconductor layer;
The insulating film is etched back until the etch stop layer is exposed, thereby rounding the shoulder of the upper end portion of the single crystal semiconductor layer exposed from the etch stop layer and forming a sidewall on the side wall of the single crystal semiconductor layer. Forming a step;
Removing an etch stop layer on the single crystal semiconductor layer;
Forming a gate insulating film on the single crystal semiconductor layer whose upper end shoulder is rounded;
Forming a gate electrode on the gate insulating film;
Forming a source / drain layer disposed so as to sandwich the gate electrode in the single crystal semiconductor layer. A method for manufacturing a semiconductor device, comprising: Preparing a substrate having a single crystal semiconductor layer formed over an insulating layer;
Forming an etch stop layer on the single crystal semiconductor layer;
Etching the single crystal semiconductor layer in which the etch stop layer is formed into a mesa shape;
Performing the isotropic etching of the etch stop layer to reduce the etch stop layer so that the shoulder of the upper end portion of the single crystal semiconductor layer is exposed;
Rounding the edge of the single crystal semiconductor layer by performing isotropic etching of the single crystal semiconductor layer using the etch stop layer as a mask;
Removing an etch stop layer on the single crystal semiconductor layer;
Forming a gate insulating film on the single crystal semiconductor layer with rounded ends; and
Forming a gate electrode on the gate insulating film;
Forming a source / drain layer disposed so as to sandwich the gate electrode in the single crystal semiconductor layer. A method for manufacturing a semiconductor device, comprising: Preparing a substrate having a single crystal semiconductor layer formed over an insulating layer;
Forming an antioxidant film on the single crystal semiconductor layer;
Etching the single crystal semiconductor layer on which the antioxidant film is formed into a mesa shape;
Performing the isotropic etching of the antioxidant film to reduce the antioxidant film so that the shoulder of the upper end portion of the single crystal semiconductor layer is exposed;
Rounding edges of the single crystal semiconductor layer by performing thermal oxidation of the single crystal semiconductor layer using the antioxidant film as a mask;
Removing an antioxidant film on the single crystal semiconductor layer;
Forming a gate insulating film on the single crystal semiconductor layer with rounded ends; and
Forming a gate electrode on the gate insulating film;
Forming a source / drain layer disposed so as to sandwich the gate electrode in the single crystal semiconductor layer. A method for manufacturing a semiconductor device, comprising:

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