JP2007048788A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of adjusting timing without changing the size of a transistor.
A first conductive type first and second gate electrodes GP1 and GP2 formed on a semiconductor substrate 1, an element isolation region 2 formed on the semiconductor substrate 1, and a semiconductor substrate 1 are provided. The shortest distance DP1s from the second MOSFET (P1, P2) to the element isolation region 2 in the gate length direction from the first gate electrode GP1 is from the second gate electrode GP2 to the element isolation region 2 in the gate length direction. Third and fourth MOSFETs (N1, N2) of the second conductivity type formed on the semiconductor substrate 1 and having the third and fourth gate electrodes GN1, GN2 shorter than the shortest distance DP2s, and a third gate The shortest distance DN1s from the electrode GN1 to the element isolation region 2 in the gate length direction is shorter than the shortest distance DN2s from the fourth gate electrode GN2 to the element isolation region 2 in the gate length direction. And a second MOSFET (P1, P2) and a third and fourth MOSFET (N1, N2), respectively, an inverter combined.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having transistors with different driving currents.

In recent years, a large number of transistors are integrated in a semiconductor device, and the scale is increased. As a result, a signal transmission path in the semiconductor device becomes long, and a signal is not transmitted to the transistor at a desired timing, and the semiconductor device may not operate. Therefore, a method of changing the size of the transistor has been proposed in order to adjust the timing (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 9-27554

  The present invention provides a semiconductor device capable of adjusting timing without changing the size of a transistor.

  According to one aspect of the present invention, a first conductivity type first and second gate electrode formed on a semiconductor substrate, an element isolation region formed on the semiconductor substrate, and first and second gate electrodes formed on the semiconductor substrate. The shortest distance from the second MOSFET to the element isolation region in the gate length direction from the first gate electrode is shorter than the shortest distance from the second gate electrode to the element isolation region in the gate length direction. The second conductivity type third and fourth MOSFETs formed on the semiconductor substrate and having third and fourth gate electrodes, and the shortest distance from the third gate electrode to the element isolation region in the gate length direction Is a combination of the first and second MOSFETs and the third and fourth MOSFETs, each being shorter than the shortest distance from the fourth gate electrode to the element isolation region in the gate length direction. The semiconductor device having the inverters are provided.

  According to one aspect of the present invention, a semiconductor substrate, an element isolation region formed in the semiconductor substrate, a first impurity region of a first conductivity type surrounded by the element isolation region on the semiconductor substrate, First and second gate electrodes having a second conductivity type second impurity region surrounded by the element isolation region on the semiconductor substrate and first and second gate electrodes formed on the first impurity region. 2 and the shortest distance from the first gate electrode to the element isolation region in the gate length direction is shorter than the shortest distance from the second gate electrode to the element isolation region in the gate length direction. The third and fourth MOSFETs having the third and fourth gate electrodes formed on the impurity region and the shortest distance from the third gate electrode to the element isolation region in the gate length direction are the fourth gate. From electrode to gate length direction Shorter than the shortest distance to the isolation region, wherein the first and second MOSFET third and fourth MOSFET semiconductor device having a combined inverter respectively are provided.

  According to the semiconductor device of one embodiment of the present invention, a semiconductor device capable of adjusting timing without changing the size of the transistor can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In addition, although embodiment of this invention is described below based on drawing, it is only for illustration and this invention is not limited to those drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. It should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  As shown in FIG. 1, the semiconductor device 1 according to the first embodiment crosses the element isolation region 2, the active regions 3 and 4 surrounded by the element isolation region 2, and the active regions 3 and 4. Gate electrodes GP1, GP2, GN1 and GN2 are arranged above the active regions 3 and 4 and the element isolation region 2.

  FIG. 2 is a layout diagram of the MOS transistors P1, P2, N1, and N2 included in the semiconductor device 1 according to the first embodiment. As shown in FIGS. 1 and 2, the pMOS transistor P <b> 1 has a gate electrode GP <b> 1 and source / drain regions arranged on both sides of the gate electrode GP <b> 1 of the active region 3. The distance from the gate electrode GP1 in the direction of the gate length of the gate electrode GP1 to the element isolation region 2 can be defined as two distances on both sides of the gate electrode GP1, and the two distances can be defined as the shorter distance DP1s and the longer distance. It can be defined as DP1l.

  The pMOS transistor P2 has a gate electrode GP2 and source / drain regions arranged on both sides of the gate electrode GP2 of the active region 3. One source / drain region of the pMOS transistor P2 is integrated with and electrically connected to one source / drain region of the pMOS transistor P1. The distance from the gate electrode GP2 to the element isolation region 2 in the direction of the gate length of the gate electrode GP2 can be defined as two distances on both sides of the gate electrode GP2, and the two distances can be defined as the shorter distance DP2s and the longer distance. It can be defined as DP2l.

  The shorter distance DP1s of the pMOS transistor P1 is set to be shorter than the shorter distance DP2s of the pMOS transistor P2. As shown in FIG. 4, the drive current Ion of the pMOS transistors P1 and P2 tends to increase as the distances DP1s and DP2s become shorter. Therefore, the pMOS transistor P1 has a larger driving current Ion and a larger driving force than the pMOS transistor P2.

  As shown in FIGS. 1 and 2, the nMOS transistor N1 has a gate electrode GN1 and source / drain regions disposed on both sides of the gate electrode GN1 of the active region 4. The distance from the gate electrode GN1 in the direction of the gate length of the gate electrode GN1 to the element isolation region 2 can be defined as two distances on both sides of the gate electrode GN1, and the two distances can be defined as the shorter distance DN1s and the longer distance. It can be defined as DN1l.

  The nMOS transistor N2 has a gate electrode GN2 and source / drain regions arranged on both sides of the gate electrode GN2 of the active region 4. One source / drain region of the nMOS transistor N2 is integrated with and electrically connected to one source / drain region of the nMOS transistor N1. The distance from the gate electrode GN2 in the direction of the gate length of the gate electrode GN2 to the element isolation region 2 can be defined as two distances on both sides of the gate electrode GN2, and the two distances can be defined as the shorter distance DN2s and the longer distance. It can be defined as DN2l.

  The shorter distance DN1s of the nMOS transistor N1 is set to be shorter than the shorter distance DN2s of the nMOS transistor N2. As shown in FIG. 3, the drive current Ion of the nMOS transistors N1 and N2 tends to decrease as the distances DN1s and DN2s become shorter. Therefore, the nMOS transistor N1 has a smaller driving current Ion and a smaller driving force than the nMOS transistor N2.

  The difference in driving power between the pMOS transistors P1 and P2 and the driving power between the nMOS transistors N1 and N2 are considered to be due to transistor characteristics varying due to process-induced stress as the semiconductor device 1 is miniaturized. . That is, in the MOS transistors P1, P2, N1, and N2, from the gate ends of the gate electrodes GP1, GP2, GN1, and GN2, only through the active regions 3 and 4 to the ends of the source / drain regions, the active regions 3 and 4 Depending on the distances DP1s, DP1l, DP2s, DP2l, DN1s, DN1l, DN2s, DN2l in the gate length direction of the gate electrodes GP1, GP2, GN1, GN2 to the boundary of the element isolation region 2, in particular, the distances DP1s, DP1l , DP2s, DP2l, DN1s, DN1l, DN2s, DN2l depending on the shorter distance DP1s, DP2s, DN1s, DN2s of the gate electrodes GP1, GP2, GN1, GN2 of the MOS transistors P1, P2, N1, N2 The stresses in the lower channel regions 3 and 4 are different. The mobility of the MOS transistors P1, P2, N1, and N2 differs depending on the stress, and the driving current Ion and further the driving force are different.

When the silicon oxide film (SiO ₂ ) is used for the element isolation region 2, the channel regions 3 and 4 below the gate electrodes GP1, GP2, GN1, and GN2 of the MOS transistors P1, P2, N1, and N2 A compressive stress is applied in the direction. The compressive stress increases as the distances DP1s, DP1l, DP2s, DP2l, DN1s, DN1l, DN2s, DN2l, especially the shorter distances DP1s, DP2s, DN1s, DN2s are shorter. This is because as the distance from the element isolation region 2 increases, the influence of stress is less likely to occur. In the pMOS transistors P1 and P2, when the distances DP1s and DP2s are shortened, the compressive stress increases and the mobility increases, and the driving current Ion increases and the driving force increases as shown in FIG. The driving current Ion and the driving force can be changed by about 10% depending on the distances DP1s and DP2s. In the nMOS transistors N1 and N2, when the distances DN1s and DN2s are shortened, the compressive stress increases and the mobility decreases, and the driving current Ion decreases and the driving force decreases as shown in FIG. The driving current Ion and the driving force can be changed by about 10% depending on the distances DN1s and DN2s. Thus, the driving force can be adjusted without changing the gate length L and the gate width W. Conventionally, in order to change the driving force, the gate length L and the gate width W are changed. According to the first embodiment, it is not necessary to change the gate length L and the gate width W in order to change the driving force.

  As shown in FIG. 5, the buffer Buf1 can be formed by connecting the pMOS transistors P1 and P2 and the nMOS transistors N1 and N2 arranged in the same manner as in FIGS. The buffer Buf1 can be rewritten into a simple circuit diagram as shown in FIG. Thus, as shown in FIG. 9B, the buffer Buf1 has the inverter Inv1 at the input stage and the inverter Inv2 at the output stage connected in series to the inverter Inv1.

  The inverter Inv1 includes a pMOS transistor P2 and an nMOS transistor N1. One source / drain region of the pMOS transistor P2 is connected to one source / drain region of the nMOS transistor N1 and the node n1. The other source / drain region of the pMOS transistor P2 is connected to the power supply potential VDD. The other source / drain region of the nMOS transistor N1 is connected to the ground potential VSS. The gate electrodes GP2 and GN1 of the pMOS transistor P2 and the nMOS transistor N1 are connected to the input terminal IN.

  The inverter Inv2 includes a pMOS transistor P1 and an nMOS transistor N2. One source / drain region of the pMOS transistor P1 is connected to one source / drain region of the nMOS transistor N2 and the output terminal OUT. The other source / drain region of the pMOS transistor P1 is connected to the power supply potential VDD. The other source / drain region of the nMOS transistor N2 is connected to the ground potential VSS. The gate electrodes GP1 and GN2 of the pMOS transistor P1 and the nMOS transistor N2 are connected to the node n1.

  As described above, in the buffer Buf1, the transistors P2 and N1 having a weak driving ability are arranged in the inverter Inv1 in the input stage, and the transistors P1 and N2 having a strong driving ability are arranged in the inverter Inv2 in the output stage. As shown in FIG. 10, the signal Vin is input to the input terminal IN, the signal Vin starts to rise at time t1, the signal Vin starts to fall at time t2, and the time T1 from time t1 to time t2 is from time t1. It is assumed that it is half of the time T2 of one cycle until time t3. The signal Vn1 at the node n1 falls with a delay of time T4 required for the transistor N1 to fall from the time t1 by the transistor N1 having a weak driving ability. Further, the signal Vn1 at the node n1 rises with a delay of a time T5 required for the transistor P2 to rise from the time t2 by the transistor P2 having a weak driving capability.

  Compared with the delay of the time T4 required for the fall of the transistor N1, the delay of the time required for the rise of the transistor P1 having a strong driving force is sufficiently small. The transistor P1 starts to rise when the voltage of the signal Vn1 reaches the threshold value of the transistor P1. The Vout does not rise when the voltage of the signal Vn1 has fallen completely, and the transistor P1 rises before the time T4 elapses. P1 starts to rise. As a result, the delay time caused by the transistor N1 with weak driving ability can be shortened with the transistor P1 with strong driving ability.

  In addition, the time delay required for the transistor N2 having a strong driving force to fall is sufficiently smaller than the delay of the time T5 required for the transistor P2 to rise. The transistor N2 starts to fall when the voltage of the signal Vn1 reaches the threshold value of the transistor N2, and Vout does not fall when the voltage of the signal Vn1 is fully raised, before the time T5 elapses. At the same time, the transistor N2 starts to fall. As a result, the delay time caused by the transistor P2 with weak driving capability can be shortened with the transistor N2 having strong driving capability. In this way, the signal Vout can be adjusted with respect to the signal Vin so as to delay both rising and falling.

  As shown in FIG. 6, the buffer Buf2 can be formed by connecting the pMOS transistors P1 and P2 and the nMOS transistors N1 and N2 that are arranged in the same manner as in FIGS. The buffer Buf2 can be rewritten into a simple circuit diagram as shown in FIG. Thus, as shown in FIG. 11B, the buffer Buf2 has the inverter Inv2 at the input stage and the inverter Inv1 at the output stage connected in series to the inverter Inv2.

  In the buffer Buf2, transistors P1 and N2 having high driving power are arranged in the inverter Inv2 in the input stage, and transistors P2 and N1 having low driving power are arranged in the inverter Inv1 in the output stage. As shown in FIG. 12, with respect to the input of the signal Vin to the input terminal IN, the signal Vn2 of the node n2 that is the output terminal of the inverter Inv2 and the input terminal of the inverter Inv1 is The transistor N2 falls with a delay of time required for the transistor N2 to fall from t1. The signal Vn2 at the node n2 rises with a delay of time required for the transistor P1 to rise from the time t2 by the transistor P1 having a strong driving capability. The signal Vout output from the output terminal OUT rises with a delay obtained by adding the time T4 required for the rise of the transistor P2 to the time required for the fall of the transistor N2 from the time t1 due to the transistor P2 having a weak driving ability. Further, the signal Vout falls by the transistor N1 having a weak driving capability with a delay obtained by adding the time T5 required for the fall of the transistor N1 to the time taken for the rise of the transistor P1 from the time t2. Since the wiring connected to the node n2 is shorter than the wiring connected to the output end OUT, the propagation delay caused by the wiring connected to the node n2 is smaller than the propagation delay caused by the wiring connected to the output end OUT. Therefore, the buffer Buf2 It can be used for timing adjustment to increase the propagation delay.

  As shown in FIG. 7, the buffer Buf3 can be formed by connecting the pMOS transistors P1 and P2 and the nMOS transistors N1 and N2 having the same arrangement as those in FIGS. The buffer Buf3 can be rewritten into a simple circuit diagram as shown in FIG. Thus, as shown in FIG. 13B, the buffer Buf3 has the inverter Inv3 at the input stage and the inverter Inv4 at the output stage connected in series to the inverter Inv3.

  The inverter Inv3 includes a pMOS transistor P1 and an nMOS transistor N1. One source / drain region of the pMOS transistor P1 is connected to one source / drain region of the nMOS transistor N1 and the node n3. The other source / drain region of the pMOS transistor P1 is connected to the power supply potential VDD. The other source / drain region of the nMOS transistor N1 is connected to the ground potential VSS. The gate electrodes GP1 and GN1 of the pMOS transistor P1 and the nMOS transistor N1 are connected to the input terminal IN.

  The inverter Inv4 includes a pMOS transistor P2 and an nMOS transistor N2. One source / drain region of the pMOS transistor P2 is connected to one source / drain region of the nMOS transistor N2 and the output terminal OUT. The other source / drain region of the pMOS transistor P2 is connected to the power supply potential VDD. The other source / drain region of the nMOS transistor N2 is connected to the ground potential VSS. The gate electrodes GP2 and GN2 of the pMOS transistor P2 and the nMOS transistor N2 are connected to the node n3.

  As described above, the buffer Buf3 includes the transistor P1 having a strong driving capability and the transistor N1 having a low driving capability arranged in the inverter Inv3 in the input stage, and the transistor P2 having a low driving capability and the transistor N2 having a high driving capability are arranged in the inverter Inv4 in the output stage. Is arranged. As shown in FIG. 14, the signal Vin is input to the input terminal IN, the signal Vin rises at time t1, the signal Vin falls at time t2, and the time T1 from time t1 to time t2 is from time t1 to time t3. It is assumed that it is half the time T2 of one cycle until. The signal Vn3 at the node n3 falls with a delay of time T5 required for the fall of the transistor N1 from the time t1 by the transistor N1 having a weak driving ability. Further, the signal Vn3 at the node n3 rises with a short delay required for the transistor P1 to rise from the time t2 by the transistor P1 having a strong driving capability. The signal Vout output from the output terminal OUT is required for the transistor P2 to rise when the transistor P2 having a weak driving force reaches the threshold value of the transistor P2 shorter than the time T5 required for the transistor N1 to fall from the time t1. It rises with a delay of time T7 including time T4. The signal Vout rises with a short delay by adding the time required for the transistor N2 to fall to the time required for the transistor P1 to rise from the time t2 due to the transistor N2 having a strong driving capability. Since the wiring connected to the node n3 is shorter than the wiring connected to the output end OUT, the propagation delay caused by the wiring connected to the node n3 is smaller than the propagation delay caused by the wiring connected to the output end OUT. Therefore, the buffer Buf3 It can be used for timing adjustment to increase the rising propagation delay.

  As shown in FIG. 8, the buffer Buf4 can be formed by connecting the pMOS transistors P1 and P2 and the nMOS transistors N1 and N2 arranged in the same manner as in FIGS. The buffer Buf4 can be rewritten into a simple circuit diagram as shown in FIG. Thus, as shown in FIG. 15B, the buffer Buf4 has the inverter Inv4 at the input stage and the inverter Inv3 at the output stage connected in series to the inverter Inv4.

  In the buffer Buf4, the transistor P2 having a low driving capability and the N2 having a high driving capability are arranged in the inverter Inv4 at the input stage, and the transistor P1 having a high driving capability and the N1 having a low driving capability are arranged in the inverter Inv3 at the output stage. As shown in FIG. 16, with respect to the input of the signal Vin to the input terminal IN, the signal Vn4 of the node n4 that is the output terminal of the inverter Inv4 and the input terminal of the inverter Inv3 is timed by the transistor N2 having a strong driving force. It falls with a short delay required for the fall of the transistor N2 from t1. Further, the signal Vn4 at the node n4 rises with a delay of time T5 required for the transistor P2 to rise from the time t2 by the transistor P2 having a weak driving capability. The signal Vout rises with a short delay by adding the time required for the transistor P1 to rise to the time required for the transistor N2 to fall from the time t1 due to the transistor P1 having strong driving power. The signal Vout output from the output terminal OUT is caused to rise by the transistor N1 having a weak driving capability when the transistor N1 rises at a time when the threshold value of the transistor N1 is shorter than the time T5 required for the transistor P2 to rise from time t2. It rises with a delay of time T6 including time T4 required. Since the wiring connected to the node n4 is shorter than the wiring connected to the output terminal OUT, the propagation delay caused by the wiring connected to the node n4 is smaller than the propagation delay caused by the wiring connected to the output terminal OUT. Therefore, the buffer Buf4 It can be used for timing adjustment to increase the falling propagation delay.

  Comparing the buffers Buf1 to Buf4 of FIGS. 5 to 8 with each other, it can be seen that they have MOS transistors P1, P2, N1, and N2, and their arrangement positions are also the same. On the contrary, four types of buffers Buf1 to Buf4 having driving characteristics capable of different timing adjustments are configured by changing only the wiring connection by the metal wiring layer with respect to the MOS transistors P1, P2, N1, and N2. Can do. Thus, the timing adjustment of the semiconductor device 1 can be performed only by changing the connection of the wiring. The driving force can be adjusted without changing the gate length L and the gate width W. Along with the timing adjustment, the area of the semiconductor device 1 does not vary. In addition, the gate electrodes GP1, GP2, GN1, GN2, and the like due to the miniaturization of the semiconductor device 1 are less affected by the shape dependency because the gate electrodes have the same shape.

  Next, a method for creating a design layout of a semiconductor device based on the semiconductor device of Example 1 will be described. As shown in FIG. 17, in the method for creating a design layout of a semiconductor device, first, in step S1, nMOS transistors N1 and N2 having different driving capabilities and pMOS transistors P1 and P2 having different driving capabilities in FIG. The other transistors necessary for the semiconductor device are arranged on the layout plane 5 in FIG.

  In step S2, inverters Inv1 to Inv4 in which nMOS transistors N1 and N2 having different driving capabilities and pMOS transistors P1 and P2 having different driving capabilities are combined and connected are formed on the layout plane 5. Further, as shown in FIG. 18, buffers Buf11 to Buf15 connected by combining the inverters Inv1 to Inv4 are formed on the layout plane 5. Further, wirings for connecting transistors necessary for the semiconductor device, inverters Inv1 to Inv4 and buffers Buf11 to Buf15 are formed on the layout plane 5. For example, the buffer Buf1 of FIG. 5 is formed as the buffer Buf11, the buffer Buf2 of FIG. 6 is formed as the buffer Buf12, the buffer Buf3 of FIG. 7 is formed as the buffer Buf13, and the buffer Buf4 of FIG. And the buffer Buf1 of FIG. 5 is formed as the buffer Buf15. As described above, the semiconductor device 1 can be formed on the layout plane 5.

  In step S3, it is determined whether or not the semiconductor device operates normally by simulation. If it operates normally, the semiconductor device design layout creation method is terminated. If it does not operate normally, the process proceeds to step S4.

  In step S4, as shown in FIG. 18, for example, by changing the buffer Buf11 to a buffer Buf2 different from its own buffer Buf1, it is possible to perform timing adjustment that increases the propagation delay of the buffer.

  By changing the buffer Buf12 to a buffer Buf1 different from its own buffer Buf2, it is possible to perform timing adjustment to reduce the propagation delay of the buffer.

  By changing the buffer Buf13 to a buffer Buf4 different from its own buffer Buf3, it is possible to adjust the timing so that the rising propagation delay of the buffer is reduced and the falling propagation delay is increased.

  By changing the buffer Buf14 to a buffer Buf3 different from its own buffer Buf4, it is possible to adjust the timing so as to increase the rising propagation delay of the buffer and reduce the falling propagation delay.

  Through step S4 as described above, timing adjustment of the semiconductor device 1 can be performed, and the semiconductor device 1 can be operated normally. Thus, it is possible to obtain a determination of normal operation of the semiconductor device 1 by executing step S3 again.

  Note that step S5 may be performed instead of step S4. Further, step S5 may be performed before or after step S4. Timing adjustment can also be performed by step S5.

  As shown in FIG. 18, depending on step S5, the buffer Buf15 is not changed from the buffer Buf1 to the other buffers Buf2 to Buf4 before and after the execution. As shown in FIG. 19, the distance DN1s is increased to change the driving power of the nMOS transistor N1 to the same level as the driving power of the nMOS transistor N2. This utilizes the fact that the slope of the graph decreases as the distances DN1s and DN2s increase, as shown in FIG. Conversely, the distance DN2s or DN2l may be reduced to change the driving power of the nMOS transistor N2 to the same level as the driving power of the nMOS transistor N1. Similarly, the distance DP1s may be increased to change the driving power of the pMOS transistor P1 to the same level as the driving power of the pMOS transistor P2. This utilizes the fact that the slope of the graph decreases as the distances DP1s and DP2s increase, as shown in FIG. Further, the driving force of the pMOS transistor P2 may be changed to the same level as that of the pMOS transistor P1 by decreasing the distance DP2s or DP2l. According to these things, the driving force of the transistors P1, P2, N1, and N2 can be adjusted. The timings of the inverters Inv1 to Inv4 and the buffers Buf1 to Buf4 can be changed, and the timing of the semiconductor device 1 can be adjusted.

  The timing adjustment in step S5 is also performed for the pMOS transistor P1 and the nMOS transistor N1 as shown in FIG. 20 that do not constitute the inverters Inv1 to Inv4 and the buffers Buf1 to Buf4. By increasing the distances DP1s and DP1l of the pMOS transistor P1 from FIG. 20A to FIG. 20B, the driving power of the pMOS transistor P1 can be reduced from FIG. An increase in the distances DP1s and DP1l increases the active region D1. Conversely, by reducing the distances DP1s and DP1l from FIG. 20B to FIG. 20A, the driving force of the pMOS transistor P1 can be increased. As a result, the timing of the semiconductor device 1 can be adjusted. The same applies to the nMOS transistor N1. Further, if it is considered that the cell C1 is constituted by the pair of pMOS transistor P1 and nMOS transistor N1, it can be considered in the same manner as the inverters Inv1 to Inv4. The waveform of Vn1 in FIG. 10, the waveform of Vn2 in FIG. The timing adjustment of the semiconductor device 1 can be performed by changing the waveforms to each other like the waveform of Vn3 and the waveform of Vn4 in FIG.

  In this way, by arranging a plurality of buffers Buf1 to Buf4 on the semiconductor device 1, in the timing adjustment after layout, only the wiring in the buffers Buf1 to Buf4 is changed, so that the driving force and the rise / fall characteristics are changed. It is possible to change the timing and adjust the timing. Conversely, in the timing adjustment after the layout, only the boundary between the element isolation region 2 and the active regions 3 and 4 is moved as shown in FIGS. 1 to 19 without changing the wiring in the buffers Buf1 to Buf4. Thus, it becomes possible to adjust the timing by changing the driving force and the rising / falling characteristics.

As illustrated in FIG. 21, the semiconductor device 1 according to the second embodiment is different from the semiconductor device 1 according to the first embodiment in FIG. 1 in that the element isolation region 2 is an element isolation region 12. In the first embodiment, a silicon oxide film is used for the element isolation region 2, and the channel regions 3 and 4 below the gate electrodes GP1, GP2, GN1, and GN2 of the MOS transistors P1, P2, N1, and N2 are arranged in the gate length direction. Although compressive stress was generated, in Example 2, a silicon nitride film (Si ₃ N ₄ ) was used in the element isolation region 12, and the gate electrodes GP1, GP2, GN1, and GN2 of the MOS transistors P1, P2, N1, and N2 were used. A tensile stress is generated in the channel regions 3 and 4 below in the gate length direction.

  The distances DP1s, DP1l, DP2s, DP2l, DN1s, DN1l, DN2s, DN2l existing on both sides of the gate electrodes GP1, GP2, GN1, GN2 of the MOS transistors P1, P2, N1, N2, in particular, the shorter distance DP1s on one side , DP2s, DN1s, DN2s are shorter, the tensile stress is larger. In the pMOS transistors P1 and P2, when the distances DP1s and DP2s are shortened, the tensile stress increases and the mobility decreases, and the driving current Ion decreases and the driving force decreases as shown in FIG. The driving current Ion and the driving force can be changed by about 10% depending on the magnitudes of the distances DP1s and DP2s. In the nMOS transistors N1 and N2, when the distances DN1s and DN2s are shortened, the tensile stress increases and the mobility increases, and the drive current Ion increases and the drive power increases as shown in FIG. The driving current Ion and the driving force can be changed by about 10% depending on the distances DN1s and DN2s.

  Therefore, as shown in FIG. 22, the pMOS transistor P1 is a pMOS transistor Plow having a small driving capability, and the pMOS transistor P2 is a pMOS transistor Phi having a large driving capability. The nMOS transistor N1 is an nMOS transistor Nhi having a large driving capability, and the nMOS transistor N2 is an nMOS transistor Nlow having a small driving capability. The MOS transistors Phi and Nhi having high driving power are surrounded by dotted circles to clarify the difference between the arrangement of the MOS transistors Phi and Nhi having high driving power in FIG. From this difference, it can be seen that if the MOS transistors P1, P2, N1, and N2 in FIG. 22 are connected like the buffer Buf1 in FIG. 5, the waveform of Buf2 in FIG. 12 is obtained. Similarly, if the connection is made like the buffer Buf2 in FIG. 6, the waveform of Buf1 in FIG. 10 is obtained. Further, if the connection is made like the buffer Buf3 of FIG. 7, the waveform of Buf4 of FIG. 16 is obtained, and if the connection is made like the buffer Buf4 of FIG. 8, the waveform of Buf3 of FIG. 14 is obtained.

  Therefore, according to the second embodiment, the timing adjustment of the semiconductor device 1 can be performed similarly to the first embodiment.

  As shown in FIG. 25, in the semiconductor device 1 according to the third embodiment, the element isolation region 2 around the active region 4 is the element isolation region 12 as compared with the semiconductor device 1 according to the first embodiment in FIG. The point is different. On the other hand, the element isolation region 2 around the active region 3 is the same as that of the first embodiment. The point that the periphery of the active region 4 is the element isolation region 12 is the same as that of the second embodiment. For these reasons, in Example 3, a silicon oxide film is used for the element isolation region 2, and compressive stress is generated in the channel region 3 below the gate electrodes GP1 and GP2 of the pMOS transistors P1 and P2 in the gate length direction. A silicon nitride film is used for the element isolation region 12, and tensile stress is generated in the channel region 4 below the gate electrodes GN1 and GN2 of the nMOS transistors N1 and N2 in the gate length direction.

  In the pMOS transistors P1 and P2, when the distances DP1s and DP2s are shortened, the compressive stress increases and the mobility increases, and the driving current Ion increases and the driving force increases as shown in FIG. The driving current Ion and the driving force can be changed by about 10% depending on the magnitudes of the distances DP1s and DP2s. In the nMOS transistors N1 and N2, when the distances DN1s and DN2s are shortened, the tensile stress increases and the mobility increases, and as shown in FIG. 27, the driving current Ion increases and the driving force increases. The driving current Ion and the driving force can be changed by about 10% depending on the distances DN1s and DN2s.

  Therefore, as shown in FIG. 26, the pMOS transistor P1 is a pMOS transistor Phi having a large driving capability, and the pMOS transistor P2 is a pMOS transistor Plow having a small driving capability. The nMOS transistor N1 is an nMOS transistor Nhi having a large driving capability, and the nMOS transistor N2 is an nMOS transistor Nlow having a small driving capability. The MOS transistors Phi and Nhi having high driving power are surrounded by dotted circles to clarify the difference between the arrangement of the MOS transistors Phi and Nhi having high driving power in FIG. From this difference, it can be seen that if the MOS transistors P1, P2, N1, and N2 in FIG. 26 are connected like the buffer Buf1 in FIG. 5, the waveform of Buf4 in FIG. 16 is obtained. Similarly, if the connection is made like the buffer Buf2 in FIG. 6, the waveform of Buf3 in FIG. 14 is obtained. If the connection is made like the buffer Buf3 in FIG. 7, the waveform of Buf2 in FIG. 12 is obtained, and if the connection is made like the buffer Buf4 in FIG. 8, the waveform of Buf1 in FIG. 10 is obtained.

  Therefore, according to the third embodiment, the timing adjustment of the semiconductor device 1 can be performed similarly to the first embodiment. Further, according to the third embodiment, the high driving current Ion obtained by the stress can be used for both the pMOS transistor and the nMOS transistor, and the driving power of the semiconductor device 1 as well as the buffers Buf1 to Buf4 can be increased.

  As shown in FIG. 29, the semiconductor device 1 according to the fourth embodiment includes pMOS transistors P3 and P4 and nMOS transistors N3 and N4 as compared with the semiconductor device 1 according to the first embodiment shown in FIG. The gate electrode GP4 of the pMOS transistor P4 is disposed at a position symmetrical to the gate electrode GP1 of the pMOS transistor P1 with respect to the center line of the active region 3. The gate electrode GP3 of the pMOS transistor P3 is disposed at a position symmetrical with respect to the center line of the active region 3 with respect to the gate electrode GP2 of the pMOS transistor P2. The gate electrode GN4 of the nMOS transistor N4 is disposed at a position symmetrical with respect to the center line of the active region 4 with respect to the gate electrode GN1 of the nMOS transistor N1. The gate electrode GN3 of the nMOS transistor N3 is arranged at a position symmetrical with respect to the center line of the active region 4 with respect to the gate electrode GN2 of the nMOS transistor N2. Then, compressive stress is generated in the gate length direction in the channel regions 3 and 4 below the gate electrodes GP1 to GP4 and GN1 to GN4 of the MOS transistors P1 to P4 and N1 to N4.

  The distances DP1s to DP4s, DP1l to DP4l, DN1s to DP4l, DN1s to DN4s, DN1l to DN4l on one side of the gate electrodes GP1 to GP4, GN1 to GN4 of the MOS transistors P1 to P4, N1 to N4, in particular, the shorter distance DP1s on one side The compressive stress increases as DP4s and DN1s through DN4s are shorter. In the pMOS transistors P1 to P4, when the distances DP1s to DP4s are shortened, the compressive stress increases and the mobility increases, and the driving current Ion increases and the driving force increases as shown in FIG. The driving current Ion and the driving force can be changed by about 10% depending on the distance DP1s to DP4s. In the nMOS transistors N1 to N4, when the distances DN1s to DN4s are shortened, the compressive stress increases and the mobility decreases, and the driving current Ion decreases and the driving force decreases as shown in FIG. The drive current Ion and the drive force can be changed by about 10% depending on the distances DN1s to DN4s.

  Therefore, as shown in FIG. 30, the pMOS transistors P1 and P4 are pMOS transistors Phi having a large driving capability, and the pMOS transistors P2 and P3 are pMOS transistors Plow having a small driving capability. The nMOS transistors N1 and N4 are nMOS transistors Nlow having a small driving capability, and the nMOS transistors N2 and N3 are nMOS transistors Nhi having a large driving capability. The MOS transistors P1 to P4 and N1 to N4 in FIG. 30 are connected like the buffer Buf1 in FIG. Since pMOS transistors P1 and P4 are connected in parallel, pMOS transistors P2 and P3 are connected in parallel, nMOS transistors N1 and N4 are connected in parallel, and nMOS transistors N2 and N3 are connected in parallel. Buf1 is equivalent to the buffer Buf1 in FIG. 5 in which the driving power of the transistors P1, P2, N1, and N2 is doubled. Therefore, a waveform having the same tendency as the waveform of Buf1 in FIG. 10 is obtained. Similarly, if the connection is made like the buffer Buf2 in FIG. 32, the driving force is twice that of the buffer Buf2 in FIG. 6, and a waveform having the same tendency as the waveform of Buf2 in FIG. 12 is obtained. If the connection is made like the buffer Buf3 in FIG. 33, the driving force becomes twice that of the buffer Buf3 in FIG. 7, and a waveform having the same tendency as the waveform of Buf3 in FIG. 14 is obtained. If the connection is made like the buffer Buf4 in FIG. 34, the driving force becomes twice that of the buffer Buf4 in FIG. 8, and a waveform having the same tendency as the waveform of Buf4 in FIG. 16 is obtained.

  Therefore, according to the fourth embodiment, the timing adjustment of the semiconductor device 1 can be performed similarly to the first embodiment. Further, according to the fourth embodiment, the driving force can be doubled as compared with the first embodiment without increasing the areas of the buffers Buf1 to Buf4. As a result, the driving force of the semiconductor device 1 can also be increased.

1 is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a layout diagram of MOS transistors included in a semiconductor device according to an embodiment of the present invention. 4 is a graph of drive current Ion with respect to the shortest distance from the gate in the direction of the gate length of the nMOS transistor included in the semiconductor device according to the embodiment of the present invention to the element isolation region. 5 is a graph of drive current Ion with respect to the shortest distance from the gate in the gate length direction of the pMOS transistor included in the semiconductor device according to the embodiment of the present invention to the element isolation region. It is a wiring diagram of buffer Buf1 which the semiconductor device concerning one embodiment of the present invention has. It is a wiring diagram of buffer Buf2 which the semiconductor device concerning one embodiment of the present invention has. It is a wiring diagram of buffer Buf3 which the semiconductor device concerning one embodiment of the present invention has. It is a wiring diagram of buffer Buf4 which the semiconductor device concerning one embodiment of the present invention has. FIG. 7 is a wiring diagram (a) and a connection diagram (b) of inverters Inv1 and Inv2 included in the buffer Buf1. It is a wave form diagram which shows the output waveform with respect to the input waveform of inverter Inv1 and Inv2 of buffer Buf1. FIG. 7 is a wiring diagram (a) and a connection diagram (b) of inverters Inv1 and Inv2 included in the buffer Buf2. It is a wave form diagram which shows the output waveform with respect to the input waveform of inverter Inv1 and Inv2 of buffer Buf2. FIG. 7 is a wiring diagram (a) and a connection diagram (b) of inverters Inv3 and Inv4 included in the buffer Buf3. It is a wave form diagram which shows the output waveform with respect to the input waveform of inverter Inv3 and Inv4 of buffer Buf3. FIG. 7 is a wiring diagram (a) and a connection diagram (b) of inverters Inv3 and Inv4 included in the buffer Buf4. It is a wave form diagram which shows the output waveform with respect to the input waveform of inverter Inv3 and Inv4 of buffer Buf4. 5 is a flowchart of a method for creating a design layout of a semiconductor device according to an embodiment of the present invention. It is a layout diagram of a semiconductor device arranged on a layout plane. It is a figure explaining change of the shortest distance from the gate of the direction of the gate length of the nMOS transistor which the semiconductor device concerning one embodiment of the present invention has to the element isolation region. It is a figure explaining the change of the shortest distance from the gate of the direction of the gate length of the pMOS transistor which the semiconductor device concerning one embodiment of the present invention has to the element isolation region. 1 is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a layout diagram of MOS transistors included in a semiconductor device according to an embodiment of the present invention. 4 is a graph of drive current Ion with respect to the shortest distance from the gate in the direction of the gate length of the nMOS transistor included in the semiconductor device according to the embodiment of the present invention to the element isolation region. 5 is a graph of drive current Ion with respect to the shortest distance from the gate in the gate length direction of the pMOS transistor included in the semiconductor device according to the embodiment of the present invention to the element isolation region. 1 is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a layout diagram of MOS transistors included in a semiconductor device according to an embodiment of the present invention. 4 is a graph of drive current Ion with respect to the shortest distance from the gate in the direction of the gate length of the nMOS transistor included in the semiconductor device according to the embodiment of the present invention to the element isolation region. 5 is a graph of drive current Ion with respect to the shortest distance from the gate in the gate length direction of the pMOS transistor included in the semiconductor device according to the embodiment of the present invention to the element isolation region. 1 is a top view of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a layout diagram of MOS transistors included in a semiconductor device according to an embodiment of the present invention. It is a wiring diagram of buffer Buf1 which the semiconductor device concerning one embodiment of the present invention has. It is a wiring diagram of buffer Buf2 which the semiconductor device concerning one embodiment of the present invention has. It is a wiring diagram of buffer Buf3 which the semiconductor device concerning one embodiment of the present invention has. It is a wiring diagram of buffer Buf4 which the semiconductor device concerning one embodiment of the present invention has.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Element isolation region (silicon oxide film)
3 Active region 4 Active region 5 Layout plane 12 Element isolation region (silicon nitride film)

Claims (5)

A short pMOS transistor having the shortest short p distance from the gate in the direction of the gate length to the element isolation region, and a shortest p distance from the gate in the direction of the gate length to the element isolation region and having a long p distance longer than the short p distance Accordingly, a long pMOS transistor having a driving force different from that of the short pMOS transistor, a short nMOS transistor having the shortest short n distance from the gate in the gate length direction to the element isolation region, and element isolation from the gate in the gate length direction A semiconductor device having a long nMOS transistor that has a long n distance that is the shortest to the region and longer than the short n distance, and has a driving force different from that of the short nMOS transistor,
A first inverter having the short pMOS transistor and the short nMOS transistor;
A second inverter having the short pMOS transistor and the long nMOS transistor;
A third inverter having the long pMOS transistor and the short nMOS transistor;
A semiconductor device comprising at least two inverters of a fourth inverter having the long pMOS transistor and the long nMOS transistor. A first buffer in which the first inverter is an input stage and the fourth inverter is an output stage;
A second buffer in which the fourth inverter is an input stage and the first inverter is an output stage;
A third buffer in which the second inverter is an input stage and the third inverter is an output stage;
2. The semiconductor device according to claim 1, further comprising at least two buffers of a fourth buffer in which the third inverter is an input stage and the second inverter is an output stage. A short pMOS transistor having the shortest short p distance from the gate in the direction of the gate length to the element isolation region, and a shortest p distance from the gate in the direction of the gate length to the element isolation region and having a long p distance longer than the short p distance Accordingly, a long pMOS transistor having a driving force different from that of the short pMOS transistor, a short nMOS transistor having the shortest short n distance from the gate in the gate length direction to the element isolation region, and element isolation from the gate in the gate length direction A long nMOS transistor having a short driving distance and a long n distance that is longer than the short n distance and having a driving force different from that of the short nMOS transistor is arranged in a layout plane;
A first inverter connecting the short pMOS transistor and the short nMOS transistor; a second inverter connecting the short pMOS transistor and the long nMOS transistor; a third inverter connecting the long pMOS transistor and the short nMOS transistor; Forming a semiconductor device having at least two uncorrected inverters of a fourth inverter connecting the long pMOS transistor and the long nMOS transistor on the layout plane;
Determine whether the semiconductor device operates normally by simulation,
If the semiconductor device does not operate normally, the pre-correction inverter is changed to the first to fourth inverters different from the pre-correction inverter. In forming the semiconductor device,
A first buffer in which the first inverter is an input stage and the fourth inverter is an output stage;
A second buffer in which the fourth inverter is an input stage and the first inverter is an output stage;
A third buffer in which the second inverter is an input stage and the third inverter is an output stage;
4. The method of creating a design layout of a semiconductor device according to claim 3, wherein at least two buffers of a fourth buffer, wherein the third inverter is an input stage and the second inverter is an output stage, are formed. A short pMOS transistor having the shortest short p distance from the gate in the direction of the gate length to the element isolation region, and a shortest p distance from the gate in the direction of the gate length to the element isolation region and having a long p distance longer than the short p distance Accordingly, a long pMOS transistor having a driving force different from that of the short pMOS transistor, a short nMOS transistor having the shortest short n distance from the gate in the gate length direction to the element isolation region, and element isolation from the gate in the gate length direction Forming a semiconductor device having a long nMOS transistor having a short driving distance and a long n distance which is longer than the short n distance and having a driving force different from that of the short nMOS transistor on a layout plane;
Determine whether the semiconductor device operates normally by simulation,
If the semiconductor device does not operate normally, at least one of the short p distance, the long p distance, the short n distance, and the long n distance is changed. .

Images