JP2007058979A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reading data at high speed while suppressing an increase in area.
In the semiconductor memory device of the present invention, when data is read from a memory cell, the precharged bit line BIT0 is discharged by the memory cell and the read auxiliary circuit. As a result, the bit line BIT0 is discharged at a high speed, so that the reading of data from the memory cell 100 can be speeded up. In the semiconductor memory device according to the present embodiment, the read auxiliary circuit 603 includes the P-type transistor TP5 that supplies the power supply voltage VDD, so that the potential of the bit line BIT0 drops to the “L” level due to noise or the like. To prevent. Thereby, malfunction of the semiconductor memory device can be prevented.
[Selection] Figure 10

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that enables high-speed reading.

One factor that determines the speed of reading from the semiconductor memory device is a delay in the bit line. Therefore, conventionally, a method for reducing the delay in the bit line has been proposed in order to speed up reading from the semiconductor memory device. As an example, the memory cell is divided into a large number of memory cell groups, thereby reducing the length of the local bit line to which each memory cell group is connected, and the memory cell connected to one local bit line. Has been proposed (see Non-Patent Document 1). According to this method, since the total load capacity of the local bit line can be reduced, the discharge of the local bit line can be speeded up and data can be read out at high speed.
Tetsuo Serizawa and three others, “8 Mbit SRAM Macro by Large Signal Sensing Scheme”, IEICE Technical Report (ICD 2003-25), IEICE, May 28, 2003, p. 69-72

  However, in the conventional method described above, in order to perform high-speed reading, the memory cells must be divided into a large number of memory cell groups, and a reading unit is required for each memory cell group. When divided into memory cell groups, there is a problem that the area of the semiconductor memory device increases.

  Therefore, an object of the present invention is to provide a semiconductor memory device capable of reading data at high speed while suppressing an increase in area.

  A semiconductor memory device according to the present invention provides a plurality of memory cells, a word line connected to the memory cells, a first bit line and a second bit line connected to the memory cells, a global bit line, A read auxiliary circuit for controlling the potential of the first bit line to a predetermined potential based on the control signal and the signal on the second bit line, and the global bit line based on the potential of the first bit line And a reading unit that controls the potential to a predetermined potential.

  In this case, it is preferable that the read assist circuit grounds the first bit line when the control signal is in an active state and the potential of the second bit line is equal to or higher than a predetermined potential.

  The read assist circuit includes a first transistor whose control signal is supplied to the gate electrode, and a second transistor whose gate electrode is electrically connected to the second bit line. The transistors may be connected in series between the first bit line and ground.

  In this case, the read assist circuit further includes a third transistor whose control signal is supplied to the gate electrode, and a fourth transistor whose gate electrode is electrically connected to the first bit line. The fourth transistor may be connected in series between the second bit line and ground.

  Further, the reading auxiliary circuit includes a first transistor whose control signal is supplied to the gate electrode, a P-type in which the gate electrode is electrically connected to the second bit line, and a predetermined power supply voltage is applied to the source electrode. A second transistor, an N-type third transistor having a gate electrode electrically connected to the second bit line, a source electrode grounded, and a drain electrode connected to the drain electrode of the second transistor; The first transistor may be connected to the drain electrode of the second transistor and the first bit line.

  In this case, the read assist circuit includes a fourth transistor whose control signal is supplied to the gate electrode, a gate electrode that is electrically connected to the first bit line, and a predetermined power supply voltage that is applied to the source electrode. Type fifth transistor, N-type sixth transistor whose gate electrode is electrically connected to the first bit line, source electrode is grounded, and drain electrode is connected to the drain electrode of the fifth transistor The fourth transistor may be connected to the drain electrode of the fifth transistor and the second bit line.

  In addition, in the read assist circuit, a P-type first transistor whose gate electrode is electrically connected to the second bit line, a predetermined power supply voltage is applied to the source electrode, and a control signal is supplied to the gate electrode. A second transistor and an N-type third transistor whose gate electrode is electrically connected to the second bit line. The second and third transistors are connected to the drain of the first transistor and the ground. May be connected in series.

  In this case, in the read assist circuit, a P-type fourth transistor whose gate electrode is electrically connected to the first bit line, a predetermined power supply voltage is applied to the source electrode, and a control signal is supplied to the gate electrode And a N-type sixth transistor whose gate electrode is electrically connected to the second bit line, and the fifth and sixth transistors are connected to the drain of the fourth transistor. It may be connected in series with the ground.

  The control signal may be activated almost simultaneously with the activation of the word line.

  The control signal may be activated before the word line is activated.

  Further, a plurality of read assist circuits may be connected to the first and second bit lines, and the plurality of read assist circuits may be activated simultaneously.

  Two or more read assist circuits may be arranged for a plurality of memory cells connected to the same first and second bit lines.

  The layout of the plurality of transistors included in the read auxiliary circuit is preferably the same as the layout of the plurality of transistors included in the memory cell except for the connection relation of the metal wiring.

  In the semiconductor memory device of the present invention, when data “0” is read from the memory cell, the first bit line is discharged by the memory cell and the read auxiliary circuit. As a result, the first bit line is discharged at a high speed, so that the reading of data from the memory cell can be speeded up.

  Further, the semiconductor memory device of the present invention includes a P-type transistor for supplying a predetermined power supply voltage to the first bit line in the read auxiliary circuit, so that noise or the like is read when reading “1” data from the memory cell. This prevents the potential of the first bit line from becoming lower than a predetermined level. Thereby, malfunction of the semiconductor memory device due to noise or the like can be prevented.

  In addition, the semiconductor memory device of the present invention includes two transistors connected in series between the bit line and the ground in the read auxiliary circuit for each of the first and second bit lines. The potential drop of the first bit line in reading “1” data is reduced. Thus, the potential of the first bit line can be prevented from becoming lower than a predetermined level due to noise or the like, and malfunction of the semiconductor memory device can be prevented.

  In addition, the semiconductor memory device of the present invention discharges the first bit line at higher speed by providing a plurality of read assist circuits for one memory cell group. Thereby, reading of data from the memory cell can be further accelerated.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to the first embodiment of the present invention. A semiconductor memory device 10 shown in FIG. 1 includes two memory cell groups 101 including a plurality of memory cells 100, a read unit 102, two read auxiliary circuits 103, a word line WL, two auxiliary circuit activation signal lines EN, Bit lines BIT0, NBIT0, BIT1 and NBIT1, and a global bit line RGBIT are provided. Memory cell 100 is connected to word line WL and bit lines BIT0 and NBIT0 (or bit lines BIT1 and NBIT1).

  Next, the configuration of the memory cell 100 will be described with reference to FIG. The memory cell 100 shown in FIG. 2 includes P-type transistors MP1 and MP2 and N-type transistors MN1 to MN4. The source electrodes of the P-type transistors MP1 and MP2 are both connected to the power supply terminal to which the power supply voltage VDD is applied. The drain electrodes of the P-type transistors MP1 and MP2 are connected to the storage nodes N1 and N2 of the memory cell 100, respectively.

  The source electrodes of the N-type transistors MN1 and MN2 are both connected to the ground terminal. The drain electrodes of N-type transistors MN1 and MN2 are connected to storage nodes N1 and N2, respectively.

  The source electrodes of N-type transistors MN3 and MN4 are connected to storage nodes N1 and N2, respectively. The gate electrodes of the N-type transistors MN3 and MN4 are both connected to the word line WL. The drain electrodes of N-type transistors MN3 and MN4 are connected to bit lines BIT0 and NBIT0, respectively.

  Storage node N1 is connected to the gate electrodes of P-type transistor MP2 and N-type transistor MN2. Storage node N2 is connected to the gate electrodes of P-type transistor MP1 and N-type transistor MN1. As described above, the P-type transistors MP1 and MP2 and the N-type transistors MN1 and MN2 constitute the memory cell 100.

  The memory cell 100 reads data stored when the word line is in an active state. In addition, when the word line is in an inactive state, the memory cell 100 does not read stored data but holds data. Hereinafter, it is assumed that the memory cell 100 stores “1” data when the potential of the storage node N1 is “H” level, and stores “0” data when it is “L” level.

  Returning to FIG. 1, the configuration of the reading unit 102 will be described. The reading unit 102 includes an N-type transistor TN1 and a NAND circuit ND1. The drain electrode of the N-type transistor TN1 is connected to the global bit line RGBIT, and the source electrode is connected to the ground terminal. The gate electrode of the N-type transistor TN1 is connected to the output of the NAND circuit ND1. The input of NAND circuit ND1 is connected to bit lines BIT0 and BIT1.

  Next, the configuration of the read assist circuit 103 will be described. Since the two read auxiliary circuits 103 are the same, FIG. 1 shows only the read auxiliary circuit 103 connected to the bit lines BIT0 and NBIT0 in detail, and the read auxiliary circuit 103 connected to the bit lines BIT1 and NBIT1. The configuration of was omitted.

  The read assist circuit 103 includes N-type transistors TN2 and TN3. The drain electrode of the N-type transistor TN2 is connected to the bit line BIT0. The source electrode of the N-type transistor TN2 is connected to the drain electrode of the N-type transistor TN3. The gate electrode of the N-type transistor TN2 is connected to the auxiliary circuit activation signal line EN. The source electrode of the N-type transistor TN3 is connected to the ground terminal. The gate electrode of the N-type transistor TN3 is connected to the bit line NBIT0.

  Next, the operation of the semiconductor memory device 10 according to this embodiment will be described. First, in the initial state, the bit lines BIT0, NBIT0, BIT1 and NBIT1, and the global bit line RGBIT are precharged to a predetermined potential (“H” level). Therefore, the N-type transistor TN3 is on in the initial state. In the initial state, the NAND circuit ND1 outputs an “L” level signal to the gate electrode of the N-type transistor TN1. Therefore, the N-type transistor TN1 is off in the initial state.

  Next, the word line WL connected to the memory cell 100 is activated, and a certain memory cell 100 is selected. Further, almost simultaneously with the selection of the memory cell 100, the auxiliary circuit activation signal line EN is controlled to be activated. Here, as an example, it is assumed that the memory cell 100 connected to the bit lines BIT0 and NBIT0 is selected. When the word line WL is activated, the data stored in the memory cell 100 is transferred to the bit line BIT0.

  When the data stored in the memory cell 100 is “0”, a current flows from the bit line BIT0 to the memory cell 100, and discharging of the bit line BIT0 is started. Further, the N-type transistor TN2 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 103.

  As described above, since the bit line BIT0 is discharged by the selected memory cell 100 and the read auxiliary circuit 103, the potential of the bit line BIT0 changes from “H” level to “L” level at high speed.

  When the potential of the bit line BIT0 transits to the “L” level, the NAND circuit ND1 outputs an “H” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is turned on to discharge the global bit line RGBIT. By detecting the potential of the global bit line RGBIT by a read circuit (not shown), data “0” is read from the semiconductor memory device 10.

  When the data stored in the memory cell 100 is “1”, the N-type transistor TN2 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 103.

  On the other hand, a current flows from the bit line NBIT0 to the selected memory cell 100, and discharging of the bit line NBIT0 is started. When the potential of the bit line NBIT0 becomes “L” level due to this discharge, the N-type transistor TN3 is turned off, and the discharge of the bit line BIT0 by the read assist circuit 103 is stopped.

  When the discharge of the bit line BIT0 stops before the potential of the bit line BIT0 reaches the “L” level (that is, when the potential of the bit line BIT0 is maintained at the “H” level), the NAND circuit ND1 The “L” level signal is continuously output to the gate electrode of TN1. By this output signal, the N-type transistor TN1 is maintained in the off state, and the potential of the global bit line RGBIT is maintained at the “H” level. By detecting the potential of the global bit line RGBIT by the read circuit, data “1” is read from the semiconductor memory device 10.

  FIG. 3 is a diagram showing a change in the potential of the bit line in the conventional SRAM and the semiconductor memory device 10. FIG. 3A shows a change in the potential of the bit line when the word line is activated in the conventional SRAM. A curve A0 and a straight line A1 indicate the potential of the bit line when the data stored in the memory cell is “0” and “1”, respectively.

  FIG. 3B shows a change in the potential of the bit line BIT0 in the semiconductor memory device 10 when the word line WL and the auxiliary circuit activation signal line EN are activated. Curves B0 and B1 indicate the potential of the bit line BIT0 when the data stored in the memory cell is “0” and “1”, respectively. As shown by the curve B0, when reading “0” data from the memory cell 100, in the semiconductor memory device 10, the potential of the bit line BIT0 is increased from “H” level to “L” at a higher speed than in the conventional SRAM. Transition to level.

  Further, as represented by the curve B1, when the data “1” is read from the memory cell 100, the potential of the bit line BIT0 decreases from the potential in the initial state. This is because the read auxiliary circuit 103 discharges the bit line BIT0 while the N-type transistor TN3 is in the ON state (that is, while the bit line NBIT0 is discharged). Note that even if the potential of the bit line BIT0 is lowered, the potential of the bit line BIT0 does not have to be "L" level.

  As described above, in the semiconductor memory device according to the present embodiment, when “0” data is read from the memory cell, the memory cell and the read auxiliary circuit discharge the bit line. As a result, the bit line is discharged at a high speed, so that the reading of data from the memory cell can be speeded up.

  In the semiconductor memory device according to this embodiment, the auxiliary circuit activation signal line EN is connected to the gate electrode of the N-type transistor TN2, but it may be connected to the gate electrode of the N-type transistor TN3. . In this case, the bit line NBIT0 is connected to the gate electrode of the N-type transistor TN2.

(Second Embodiment)
FIG. 4 is a diagram showing a configuration of a semiconductor memory device according to the second embodiment of the present invention. The semiconductor memory device 20 shown in FIG. 4 is obtained by replacing the read auxiliary circuit 103 included in the semiconductor memory device 10 according to the first embodiment with a read auxiliary circuit 203. Among the constituent elements of the present embodiment, the same constituent elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The read auxiliary circuit 203 includes a P-type transistor TP1 and N-type transistors TN4 and TN5. The source electrode of the P-type transistor TP1 is connected to the power supply terminal to which the power supply voltage VDD is applied. The drain electrode of the P-type transistor TP1 is connected to the drain electrode of the N-type transistor TN4. The source electrode of the N-type transistor TN4 is connected to the ground terminal. The gate electrodes of the P-type transistor TP1 and the N-type transistor TN4 are both connected to the bit line NBIT0.

  A connection point Q1 shown in FIG. 4 is a point where the P-type transistor TP1 and the N-type transistor TN4 are connected. The source electrode of the N-type transistor TN5 is connected to this connection point Q1. The drain electrode of the N-type transistor TN5 is connected to the bit line BIT0. The gate electrode of the N-type transistor TN5 is connected to the auxiliary circuit activation signal line EN.

  Next, the operation of the semiconductor memory device 20 according to this embodiment will be described. First, the initial state of the semiconductor memory device 20 is the same as that of the semiconductor memory device 10 according to the first embodiment except for the following points. That is, in the semiconductor memory device 20, the N-type transistor TN4 is on in the initial state instead of the N-type transistor TN3. The P-type transistor TP1 is in an off state in the initial state.

  Next, the word line WL connected to the memory cell 100 is activated, and a certain memory cell 100 is selected. Further, almost simultaneously with the selection of the memory cell 100, the auxiliary circuit activation signal line EN is controlled to be activated. Also here, as an example, it is assumed that the memory cell 100 connected to the bit lines BIT0 and NBIT0 is selected.

  When the data stored in the memory cell 100 is “0”, a current flows from the bit line BIT0 to the memory cell 100, and discharging of the bit line BIT0 is started. Further, the N-type transistor TN5 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 203.

  Similarly to the first embodiment, since the bit line BIT0 is discharged by the memory cell 100 and the read assist circuit 203 in the semiconductor memory device 20, the potential of the bit line BIT0 is changed from “H” level to “L” at high speed. “Transition to level.

  When the potential of the bit line BIT0 transits to the “L” level, the NAND circuit ND1 outputs an “H” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is turned on to discharge the global bit line RGBIT. As described above, data “0” is read from the semiconductor memory device 20.

  When the data stored in the memory cell 100 is “1”, the N-type transistor TN5 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 203.

  On the other hand, a current flows from the bit line NBIT0 to the selected memory cell 100, and discharging of the bit line NBIT0 is started. When the potential of the bit line NBIT0 becomes “L” level due to this discharge, the N-type transistor TN4 is turned off, and the discharge of the bit line BIT0 by the read assist circuit 203 is stopped. At the same time, the P-type transistor TP1 is turned on, and current starts to flow from the power supply terminal to which the power supply voltage VDD is applied to the bit line BIT0 via the P-type transistor TP1 and the N-type transistor TN5.

  When a current flows from the power supply terminal to the bit line BIT0, the potential of the bit line BIT0 gradually rises to a potential (VDD−Vth) obtained by subtracting the threshold voltage Vth of the N-type transistor TN5 from the power supply voltage VDD. The reason why the potential of the bit line BIT0 becomes VDD-Vth is that a voltage drop occurs between the source electrode and the drain electrode of the N-type transistor TN5. The semiconductor memory device 20 includes the P-type transistor TP1 that supplies the power supply voltage VDD, thereby preventing the potential of the bit line BIT0 from dropping to “L” level due to noise or the like.

  Since the potential of the bit line BIT0 is at “H” level, the NAND circuit ND1 continues to output an “L” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is maintained in the off state, and the potential of the global bit line RGBIT is maintained at the “H” level. As described above, data “1” is read from the semiconductor memory device 20.

  FIG. 5 is a diagram showing changes in the potential of the bit line BIT0 in the semiconductor memory device 20 when the word line WL and the auxiliary circuit activation signal line EN are activated. Curves C0 and C1 indicate the potential of the bit line BIT0 when the data stored in the memory cell is “0” and “1”, respectively.

  As shown by the curve C1, when data “1” is read from the memory cell 100, the potential of the bit line BIT0 once falls from the potential in the initial state, starts to rise from a certain point, and finally reaches the VDD It rises to a potential of −Vth. This is because the bit line BIT0 is discharged by the read assist circuit 203 while the N-type transistor TN4 is in the ON state, and then the P-type transistor TP1 is turned ON when the discharge of the bit line BIT is stopped. This is because a current flows through the line BIT0.

  As described above, in the semiconductor memory device according to the present embodiment, when “0” data is read from the memory cell, the memory cell and the read auxiliary circuit discharge the bit line. As a result, the bit line is discharged at a high speed, so that the reading of data from the memory cell can be speeded up. In addition, the semiconductor memory device according to the present embodiment includes a P-type transistor that supplies the power supply voltage VDD in the read auxiliary circuit, so that when the data “1” is read from the memory cell, the potential of the bit line due to noise or the like. Is prevented from dropping to the “L” level. Thereby, malfunction of the semiconductor memory device due to noise or the like can be prevented.

(Third embodiment)
FIG. 6 is a diagram showing a configuration of a semiconductor memory device according to the third embodiment of the present invention. The semiconductor memory device 30 illustrated in FIG. 6 is obtained by replacing the read auxiliary circuit 103 included in the semiconductor memory device 10 according to the first embodiment with a read auxiliary circuit 303. Among the constituent elements of the present embodiment, the same constituent elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The read auxiliary circuit 303 includes a P-type transistor TP2 and N-type transistors TN6 and TN7. The source electrode of the P-type transistor TP2 is connected to the power supply terminal to which the power supply voltage VDD is applied. The drain electrode of the P-type transistor TP2 is connected to the drain electrode of the N-type transistor TN6. The source electrode of the N-type transistor TN6 is connected to the drain electrode of the N-type transistor TN7. The source electrode of the N-type transistor TN7 is connected to the ground terminal. The gate electrodes of the P-type transistor TP2 and the N-type transistor TN7 are both connected to the bit line NBIT0. The gate electrode of the N-type transistor TN6 is connected to the auxiliary circuit activation signal line EN.

  A connection point Q2 shown in FIG. 4 is a point where the P-type transistor TP2 and the N-type transistor TN6 are connected. Bit line BIT0 is connected to this connection point Q2.

  Next, the operation of the semiconductor memory device 30 according to this embodiment will be described. First, the initial state of the semiconductor memory device 30 is the same as that of the semiconductor memory device 10 according to the first embodiment except for the following points. That is, in the semiconductor memory device 30, the N-type transistor TN7 is in an on state in the initial state instead of the N-type transistor TN3. The P-type transistor TP2 is in an off state in the initial state.

  Next, the word line WL connected to the memory cell 100 is activated, and a certain memory cell 100 is selected. Further, almost simultaneously with the selection of the memory cell 100, the auxiliary circuit activation signal line EN is controlled to be activated. Also here, as an example, it is assumed that the memory cell 100 connected to the bit lines BIT0 and NBIT0 is selected.

  When the data stored in the memory cell 100 is “0”, a current flows from the bit line BIT0 to the memory cell 100, and discharging of the bit line BIT0 is started. Further, the N-type transistor TN6 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 303.

  Similarly to the first embodiment, since the bit line BIT0 is discharged by the memory cell 100 and the read assist circuit 303 in the semiconductor memory device 30, the potential of the bit line BIT0 is changed from “H” level to “L” at high speed. “Transition to level.

  When the potential of the bit line BIT0 transits to the “L” level, the NAND circuit ND1 outputs an “H” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is turned on to discharge the global bit line RGBIT. As described above, data “0” is read from the semiconductor memory device 30.

  When the data stored in the memory cell 100 is “1”, the N-type transistor TN6 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 303.

  On the other hand, a current flows from the bit line NBIT0 to the selected memory cell 100, and discharging of the bit line NBIT0 is started. When the potential of the bit line NBIT0 becomes “L” level due to this discharge, the N-type transistor TN7 is turned off, and the discharge of the bit line BIT0 by the read assist circuit 303 is stopped. At the same time, the P-type transistor TP2 is turned on, and current starts to flow from the power supply terminal to which the power supply voltage VDD is applied to the bit line BIT0 via the P-type transistor TP2. When a current flows from the power supply terminal to the bit line BIT0, the potential of the bit line BIT0 gradually rises to the power supply voltage VDD.

  Since the potential of the bit line BIT0 is at “H” level, the NAND circuit ND1 continues to output an “L” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is maintained in the off state, and the potential of the global bit line RGBIT is maintained at the “H” level. As described above, data “1” is read from the semiconductor memory device 30.

  FIG. 7 shows changes in the potential of bit line BIT0 when word line WL and auxiliary circuit activation signal line EN are activated in semiconductor memory device 30. In FIG. Curves D0 and D1 indicate the potential of the bit line BIT0 when the data stored in the memory cell is “0” and “1”, respectively.

  As shown by the curve D1, when data “1” is read from the memory cell 100, the potential of the bit line BIT0 once drops from the potential in the initial state, starts to rise from a certain point in time, and finally the power supply Rise to voltage VDD. This is because the bit line BIT0 is discharged by the read assist circuit 303 while the N-type transistor TN7 is in the on state, and then the P-type transistor TP2 is turned on when the discharge of the bit line BIT is stopped. This is because a current flows through the line BIT0.

  As described above, in the semiconductor memory device according to the present embodiment, when “0” data is read from the memory cell, the memory cell and the read auxiliary circuit discharge the bit line. As a result, the bit line is discharged at a high speed, so that the reading of data from the memory cell can be speeded up. In addition, the semiconductor memory device according to the present embodiment includes a P-type transistor that supplies the power supply voltage VDD to the read assist circuit, so that when the data “1” is read from the memory cell, the potential of the bit line due to noise or the like. Is prevented from dropping to the “L” level. Thereby, malfunction of the semiconductor memory device due to noise or the like can be prevented.

  In the semiconductor memory device according to the present embodiment, the auxiliary circuit activation signal line EN is connected to the gate electrode of the N-type transistor TN6. However, the auxiliary circuit activation signal line EN may be connected to the gate electrode of the N-type transistor TN7. . In this case, the bit line NBIT0 is connected to the gate electrode of the N-type transistor TN2. The semiconductor memory device configured as described above can also achieve the same effects as the semiconductor memory device according to the present embodiment.

(Fourth embodiment)
FIG. 8 is a diagram showing a configuration of a semiconductor memory device according to the fourth embodiment of the present invention. A semiconductor memory device 40 shown in FIG. 8 is obtained by replacing the read auxiliary circuit 103 included in the semiconductor memory device 10 according to the first embodiment with a read auxiliary circuit 403. Among the constituent elements of the present embodiment, the same constituent elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The read auxiliary circuit 403 includes N-type transistors TN8 to TN11. The drain electrode of the N-type transistor TN8 is connected to the bit line BIT0. The source electrode of the N-type transistor TN8 is connected to the drain electrode of the N-type transistor TN9. The gate electrode of the N-type transistor TN8 is connected to the auxiliary circuit activation signal line EN. The source electrode of the N-type transistor TN9 is connected to the ground terminal. The gate electrode of the N-type transistor TN9 is connected to the bit line NBIT0.

  The drain electrode of the N-type transistor TN10 is connected to the bit line NBIT0. The source electrode of the N-type transistor TN10 is connected to the drain electrode of the N-type transistor TN11. The gate electrode of the N-type transistor TN10 is connected to the auxiliary circuit activation signal line EN. The source electrode of the N-type transistor TN11 is connected to the ground terminal. The gate electrode of the N-type transistor TN11 is connected to the bit line BIT0.

  Next, the operation of the semiconductor memory device 40 according to this embodiment will be described. First, the initial state of the semiconductor memory device 20 is the same as that of the semiconductor memory device 10 according to the first embodiment except for the following points. That is, in the semiconductor memory device 40, the N-type transistors TN9 and TN11 are on in the initial state instead of the N-type transistor TN3.

  Next, the word line WL connected to the memory cell 100 is activated, and a certain memory cell 100 is selected. Further, almost simultaneously with the selection of the memory cell 100, the auxiliary circuit activation signal line EN is controlled to be activated. Also here, as an example, it is assumed that the memory cell 100 connected to the bit lines BIT0 and NBIT0 is selected.

  When the data stored in the memory cell 100 is “0”, a current flows from the bit line BIT0 to the memory cell 100, and discharging of the bit line BIT0 is started. Further, the N-type transistors TN8 and TN10 are turned on, and the discharge of the bit lines BIT0 and NBIT0 is started by the read auxiliary circuit 403.

  Similarly to the first embodiment, since the bit line BIT0 is discharged by the memory cell 100 and the read assist circuit 403 in the semiconductor memory device 40, the potential of the bit line BIT0 is changed from “H” level to “L” at high speed. “Transition to level.

  When the potential of the bit line BIT0 transits to the “L” level, the NAND circuit ND1 outputs an “H” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is turned on to discharge the global bit line RGBIT. As described above, data “0” is read from the semiconductor memory device 40.

  When the data stored in the memory cell 100 is “1”, the N-type transistor TN8 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 403.

  Further, when a current flows from the bit line NBIT0 to the selected memory cell 100, the discharge of the bit line NBIT0 is started. Further, the discharge of the bit line NBIT0 is started by the read auxiliary circuit 403 when the N-type transistor TN10 is turned on. When the potential of the bit line NBIT0 becomes “L” level due to these discharges, the N-type transistor TN9 is turned off, and the discharge of the bit line BIT0 by the read assist circuit 403 is stopped.

  In the semiconductor memory device 40, since the discharge of the bit line NBIT0 is performed by the read auxiliary circuit 403 in addition to the selected memory cell 100, the bit line NBIT0 is compared with the semiconductor memory device 10 according to the first embodiment. Transitions to the “L” level more quickly. Therefore, since the N-type transistor TN9 is turned off more quickly, the period during which the bit line BIT0 is discharged is shortened, and the potential drop of the bit line BIT0 can be reduced. Thus, the potential of the bit line can be prevented from dropping to “L” level due to noise or the like, and malfunction of the semiconductor memory device can be prevented.

  Since the potential of the bit line BIT0 is at “H” level, the NAND circuit ND1 continues to output an “L” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is maintained in the off state, and the potential of the global bit line RGBIT is maintained at the “H” level. As described above, data “1” is read from the semiconductor memory device 40.

  As described above, in the semiconductor memory device according to the present embodiment, when “0” data is read from the memory cell, the memory cell and the read auxiliary circuit discharge the bit line. As a result, the bit line is discharged at a high speed, so that the reading of data from the memory cell can be speeded up. In addition, the semiconductor memory device according to this embodiment includes two N-type transistors connected in series between the bit line and the ground terminal in the read auxiliary circuit for each of the bit lines BIT and NBIT. The potential drop of the bit line BIT when data “1” is read from the memory cell is reduced. As a result, the potential of the bit line BIT can be prevented from dropping to the “L” level due to noise or the like, and malfunction of the semiconductor memory device can be prevented.

  In the semiconductor memory device according to the present embodiment, the auxiliary circuit activation signal line EN is connected to the gate electrodes of the N-type transistors TN8 and TN10. However, the auxiliary circuit activation signal line EN is connected to the gate electrodes of the N-type transistors TN9 and / or TN11. It does not matter if it is connected. When the auxiliary circuit activation signal line EN is connected to the N-type transistor TN9, the bit line NBIT0 is connected to the N-type transistor TN8. When the auxiliary circuit activation signal line EN is connected to the N-type transistor TN11, the bit line BIT0 is connected to the N-type transistor TN10.

(Fifth embodiment)
FIG. 9 is a diagram showing a configuration of a semiconductor memory device according to the fifth embodiment of the present invention. A semiconductor memory device 50 shown in FIG. 9 is obtained by replacing the read auxiliary circuit 103 included in the semiconductor memory device 10 according to the first embodiment with a read auxiliary circuit 503. Among the constituent elements of the present embodiment, the same constituent elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The read assist circuit 503 includes P-type transistors TP3 and TP4 and N-type transistors TN12 to TN15. The source electrode of the P-type transistor TP3 is connected to the power supply terminal to which the power supply voltage VDD is applied. The drain electrode of the P-type transistor TP3 is connected to the drain electrode of the N-type transistor TN12. The source electrode of the N-type transistor TN12 is connected to the ground terminal. The gate electrodes of the P-type transistor TP3 and the N-type transistor TN12 are both connected to the bit line NBIT0.

  A connection point Q3 shown in FIG. 9 is a point where the P-type transistor TP3 and the N-type transistor TN12 are connected. The source electrode of the N-type transistor TN13 is connected to this connection point Q3. The drain electrode of the N-type transistor TN13 is connected to the bit line BIT0. The gate electrode of the N-type transistor TN13 is connected to the auxiliary circuit activation signal line EN.

  The source electrode of the P-type transistor TP4 is connected to the power supply terminal to which the power supply voltage VDD is applied. The drain electrode of the P-type transistor TP4 is connected to the drain electrode of the N-type transistor TN14. The source electrode of the N-type transistor TN14 is connected to the ground terminal. The gate electrodes of the P-type transistor TP4 and the N-type transistor TN14 are both connected to the bit line BIT0.

  A connection point Q4 shown in FIG. 9 is a point where the P-type transistor TP4 and the N-type transistor TN14 are connected. The source electrode of the N-type transistor TN14 is connected to this connection point Q4. The drain electrode of the N-type transistor TN15 is connected to the bit line NBIT0. The gate electrode of the N-type transistor TN15 is connected to the auxiliary circuit activation signal line EN.

  Next, the operation of the semiconductor memory device 50 according to this embodiment will be described. First, the initial state of the semiconductor memory device 50 is the same as that of the semiconductor memory device 10 according to the first embodiment except for the following points. That is, in the semiconductor memory device 50, the N-type transistors TN12 and TN14 are on in the initial state instead of the N-type transistor TN3. The P-type transistors TP3 and TP4 are off in the initial state.

  Next, the word line WL connected to the memory cell 100 is activated, and a certain memory cell 100 is selected. Further, almost simultaneously with the selection of the memory cell 100, the auxiliary circuit activation signal line EN is controlled to be activated. Also here, as an example, it is assumed that the memory cell 100 connected to the bit lines BIT0 and NBIT0 is selected.

  When the data stored in the memory cell 100 is “0”, a current flows from the bit line BIT0 to the memory cell 100, and discharging of the bit line BIT0 is started. Further, the N-type transistors TN13 and TN15 are turned on, and the discharge of the bit lines BIT0 and NBIT0 is started by the read auxiliary circuit 503.

  Similarly to the first embodiment, in the semiconductor memory device 50, the bit line BIT0 is discharged by the memory cell 100 and the read assist circuit 503, so that the potential of the bit line BIT0 is changed from “H” level to “L” at high speed. “Transition to level.

  When the potential of the bit line BIT0 transits to the “L” level, the NAND circuit ND1 outputs an “H” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is turned on to discharge the global bit line RGBIT. As described above, data “0” is read from the semiconductor memory device 50.

  When the data stored in the memory cell 100 is “1”, the N-type transistor TN13 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 503.

  Further, when a current flows from the bit line NBIT0 to the selected memory cell 100, the discharge of the bit line NBIT0 is started. Further, the discharge of the bit line NBIT0 is started by the read auxiliary circuit 503 by turning on the N-type transistor TN15. When the potential of the bit line NBIT0 becomes “L” level due to these discharges, the N-type transistor TN12 is turned off, and the discharge of the bit line BIT0 by the read assist circuit 503 is stopped. At the same time, the P-type transistor TP3 is turned on, and current starts to flow from the power supply terminal to which the power supply voltage VDD is applied to the bit line BIT0 via the P-type transistor TP3 and the N-type transistor TN13.

  When a current flows from the power supply terminal to the bit line BIT0, the potential of the bit line BIT0 gradually rises to a potential (VDD−Vth) obtained by subtracting the threshold voltage Vth of the N-type transistor TN13 from the power supply voltage VDD. The reason why the potential of the bit line BIT0 becomes a value obtained by subtracting the threshold voltage Vth from the power supply voltage VDD has been described in the second embodiment, and is omitted here.

  In the semiconductor memory device 50 according to the present embodiment as well, similarly to the semiconductor memory device 40 according to the fourth embodiment, the discharge of the bit line NBIT0 is performed by the read auxiliary circuit 503 in addition to the selected memory cell 100. Compared with the semiconductor memory device 20 according to the second embodiment, the bit line NBIT0 changes to the “L” level more quickly. Therefore, since the N-type transistor TN12 is turned off more quickly, the period during which the bit line BIT0 is discharged is shortened, and the potential drop of the bit line BIT0 can be reduced.

  Since the potential of the bit line BIT0 is at “H” level, the NAND circuit ND1 continues to output an “L” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is maintained in the off state, and the potential of the global bit line RGBIT is maintained at the “H” level. As described above, data “1” is read from the semiconductor memory device 50.

  As described above, in the semiconductor memory device according to the present embodiment, when “0” data is read from the memory cell, the memory cell and the read auxiliary circuit discharge the bit line. As a result, the bit line is discharged at a high speed, so that the reading of data from the memory cell can be speeded up. In addition, the semiconductor memory device according to this embodiment includes two N-type transistors connected in series between the bit line and the ground terminal in the read auxiliary circuit for each of the bit lines BIT and NBIT. The potential drop of the bit line BIT when data “1” is read from the memory cell is reduced. Furthermore, the semiconductor memory device according to the present embodiment includes a P-type transistor that supplies the power supply voltage VDD in the read assist circuit, so that the potential of the bit line BIT drops to “L” level due to noise or the like. To prevent. Thereby, malfunction of the semiconductor memory device can be prevented.

(Sixth embodiment)
FIG. 10 is a diagram showing a configuration of a semiconductor memory device according to the sixth embodiment of the present invention. A semiconductor memory device 60 shown in FIG. 10 is obtained by replacing the read auxiliary circuit 103 included in the semiconductor memory device 10 according to the first embodiment with a read auxiliary circuit 603. Among the constituent elements of the present embodiment, the same constituent elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The read auxiliary circuit 603 includes P-type transistors TP5 and TP6, and N-type transistors TN16 to TN19. The source electrode of the P-type transistor TP5 is connected to the power supply terminal to which the power supply voltage VDD is applied. The drain electrode of the P-type transistor TP5 is connected to the drain electrode of the N-type transistor TN16. The source electrode of the N-type transistor TN16 is connected to the drain electrode of the N-type transistor TN17. The source electrode of the N-type transistor TN17 is connected to the ground terminal. The gate electrodes of the P-type transistor TP5 and the N-type transistor TN17 are both connected to the bit line NBIT0. The gate electrode of the N-type transistor TN16 is connected to the auxiliary circuit activation signal line EN.

  A connection point Q5 shown in FIG. 10 is a point at which the P-type transistor TP5 and the N-type transistor TN16 are connected. Bit line BIT0 is connected to this connection point Q5.

  The source electrode of the P-type transistor TP6 is connected to the power supply terminal to which the power supply voltage VDD is applied. The drain electrode of the P-type transistor TP6 is connected to the drain electrode of the N-type transistor TN18. The source electrode of the N-type transistor TN18 is connected to the drain electrode of the N-type transistor TN19. The source electrode of the N-type transistor TN19 is connected to the ground terminal. The gate electrodes of the P-type transistor TP6 and the N-type transistor TN19 are both connected to the bit line BIT0. The gate electrode of the N-type transistor TN18 is connected to the auxiliary circuit activation signal line EN.

  A connection point Q6 shown in FIG. 10 is a point at which the P-type transistor TP6 and the N-type transistor TN18 are connected. Bit line NBIT0 is connected to this connection point Q6.

  Next, the operation of the semiconductor memory device 60 according to this embodiment will be described. First, the initial state of the semiconductor memory device 60 is the same as that of the semiconductor memory device 10 according to the first embodiment except for the following points. In other words, in semiconductor memory device 60, N-type transistors TN17 and TN19 are on in the initial state instead of N-type transistor TN3. P-type transistors TP5 and TP6 are off in the initial state.

  Next, the word line WL connected to the memory cell 100 is activated, and a certain memory cell 100 is selected. Further, almost simultaneously with the selection of the memory cell 100, the auxiliary circuit activation signal line EN is controlled to be activated. Also here, as an example, it is assumed that the memory cell 100 connected to the bit lines BIT0 and NBIT0 is selected.

  When the data stored in the memory cell 100 is “0”, a current flows from the bit line BIT0 to the memory cell 100, and discharging of the bit line BIT0 is started. Also, the N-type transistors TN116 and TN18 are turned on, and the discharge of the bit lines BIT0 and NBIT0 is started by the read auxiliary circuit 603.

  Similarly to the first embodiment, since the bit line BIT0 is discharged by the memory cell 100 and the read assist circuit 603 in the semiconductor memory device 60, the potential of the bit line BIT0 is changed from “H” level to “L” at high speed. “Transition to level.

  When the potential of the bit line BIT0 transits to the “L” level, the NAND circuit ND1 outputs an “H” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is turned on to discharge the global bit line RGBIT. As described above, data “0” is read from the semiconductor memory device 60.

  When the data stored in the memory cell 100 is “1”, the N-type transistor TN16 is turned on, and the discharge of the bit line BIT0 is started by the read auxiliary circuit 603.

  Further, when a current flows from the bit line NBIT0 to the selected memory cell 100, the discharge of the bit line NBIT0 is started. Further, the N-type transistor TN18 is turned on, whereby the discharge of the bit line NBIT0 is started by the read auxiliary circuit 603. When the potential of the bit line NBIT0 becomes “L” level due to these discharges, the N-type transistor TN17 is turned off, and the discharge of the bit line BIT0 by the read assist circuit 603 is stopped. At the same time, the P-type transistor TP5 is turned on, and current starts to flow from the power supply terminal to which the power supply voltage VDD is applied to the bit line BIT0 via the P-type transistor TP5. When a current flows from the power supply terminal to the bit line BIT0, the potential of the bit line BIT0 gradually rises to the power supply voltage VDD.

  In the semiconductor memory device 60 according to the present embodiment as well, similarly to the semiconductor memory device 40 according to the fourth embodiment, the discharge of the bit line NBIT0 is performed by the read auxiliary circuit 603 in addition to the selected memory cell 100. Compared with the semiconductor memory device 30 according to the third embodiment, the bit line NBIT0 changes to the “L” level more quickly. Therefore, since the N-type transistor TN17 is turned off more quickly, the period during which the bit line BIT0 is discharged is shortened, and the potential drop of the bit line BIT0 can be reduced.

  Since the potential of the bit line BIT0 is at “H” level, the NAND circuit ND1 continues to output an “L” level signal to the gate electrode of the N-type transistor TN1. By this output signal, the N-type transistor TN1 is maintained in the off state, and the potential of the global bit line RGBIT is maintained at the “H” level. As described above, data “1” is read from the semiconductor memory device 60.

  As described above, in the semiconductor memory device according to this embodiment, when “0” data is read from the memory cell, the bit line is discharged by the memory cell and the read auxiliary circuit. As a result, the bit line is discharged at a high speed, so that the reading of data from the memory cell can be speeded up. In addition, the semiconductor memory device according to the present embodiment includes two N-type transistors connected in series between the bit line and the ground terminal in the read auxiliary circuit for each of the bit lines BIT and NBIT. The potential drop of the bit line BIT when data “1” is read from the cell is reduced. Furthermore, the semiconductor memory device according to the present embodiment includes a P-type transistor that supplies the power supply voltage VDD in the read assist circuit, so that the potential of the bit line BIT drops to “L” level due to noise or the like. To prevent. Thereby, malfunction of the semiconductor memory device can be prevented.

  In the semiconductor memory device according to the present embodiment, the auxiliary circuit activation signal line EN is connected to the gate electrode of the N-type transistor TN18. However, the auxiliary circuit activation signal line EN may be connected to the gate electrode of the N-type transistor TN19. . In this case, the bit line NBIT0 is connected to the gate electrode of the N-type transistor TN18. The semiconductor memory device configured as described above can also achieve the same effects as the semiconductor memory device according to the present embodiment.

  FIG. 11 is a configuration diagram (FIG. 11A) and a layout diagram (FIG. 11B) of the read auxiliary circuit 603 included in the semiconductor memory device 60 according to the present embodiment. FIG. 11B shows an N well substrate 1000, a P well substrate 1001, a diffusion layer 1002, a polymetal 1003, a single layer metal 1004, and a via contact 1005 connecting the diffusion layer and the single layer metal.

  FIG. 12 is a layout diagram of the memory cell 100. Comparing the layout diagram of the read assist circuit 603 shown in FIG. 11B and the layout diagram of the memory cell 100 shown in FIG. 12, only the connection relationship between the first-layer metal 1004 and the diffusion layer 1002 is different. I understand. By forming the read auxiliary circuit 603 as shown in FIG. 11B, the read auxiliary circuit 603 and the memory cell 100 can be made the same size. Therefore, the read auxiliary circuit 603 is arranged in the memory cell region. Can be done easily. Further, the memory cell layout special rule can be applied to the read assist circuit 603 in the same manner as the memory cell 100, and the area of the memory cell region can be reduced.

  Further, by forming the read auxiliary circuit 603 as shown in FIG. 11B, the auxiliary circuit activation signal is used as a memory cell group selection signal with several bits of address, so that the auxiliary circuit activation signal is generated by the row decoder. Can be generated.

  FIG. 13 is a layout diagram illustrating an arrangement example of the read assist circuit 603 and the memory cell 100. A dotted line 1010 in FIG. 13 indicates the memory cell 100, and a broken line 1020 indicates the read auxiliary circuit 603. As shown in FIG. 13, it is possible to arrange two or more read assist circuits 603 for one memory cell group. By simultaneously operating these read assist circuits 603, reading from the memory cell 100 can be further speeded up.

  In all the embodiments, the transistor to which the auxiliary circuit activation signal line EN is connected is an N-type transistor, but may be a P-type transistor.

  In all the embodiments, in order to facilitate understanding of the invention, one semiconductor memory device is connected to the global bit line RGBIT. However, a semiconductor memory device is connected to the global bit line RGBIT. Many may be connected. A large number of such global bit lines RGBIT may be arranged.

  In all the embodiments, the semiconductor memory device is provided with two memory cell groups. However, the number of memory cell groups is not limited as long as it is one or more.

  Further, although the configuration in the case of the positive logic is shown for the semiconductor memory devices according to all the embodiments, the case of the negative logic can be dealt with by connecting the global bit line RGBIT to the bit line NBIT side.

  Since the semiconductor memory device of the present invention is a semiconductor memory device capable of reading data at high speed while suppressing an increase in area, it can be used for an SRAM or the like.

1 is a diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. The figure which shows the structure of the memory cell contained in the semiconductor memory device which concerns on all embodiment of this invention. The figure which shows the change of the electric potential of the bit line in the conventional SRAM and the semiconductor memory device according to the first embodiment of the present invention. The figure which shows the structure of the semiconductor memory device based on the 2nd Embodiment of this invention. The figure which shows the change of the electric potential of the bit line in the semiconductor memory device based on the 2nd Embodiment of this invention. The figure which shows the structure of the semiconductor memory device based on the 3rd Embodiment of this invention. The figure which shows the change of the electric potential of the bit line in the semiconductor memory device based on the 3rd Embodiment of this invention. The figure which shows the structure of the semiconductor memory device based on the 4th Embodiment of this invention. The figure which shows the structure of the semiconductor memory device based on the 5th Embodiment of this invention. The figure which shows the structure of the semiconductor memory device based on the 6th Embodiment of this invention. The figure and layout figure which show the structure of the read auxiliary circuit contained in the semiconductor memory device based on the 6th Embodiment of this invention Layout diagram of memory cells included in semiconductor memory device according to all embodiments of the present invention Layout diagram showing an arrangement example of a read auxiliary circuit and memory cells included in a semiconductor memory device according to a sixth embodiment of the present invention

Explanation of symbols

10, 20, 30, 40, 50, 60 Semiconductor memory device 100 Memory cell 101 Memory cell group 102 Read unit 103, 203, 303, 403, 503, 603 Read auxiliary circuit 1000 N well substrate 1001 P well substrate 1002 Diffusion layer 1003 Polymetal 1004 One layer metal 1005 Via contact BIT, BIT0, BIT1, NBIT, NBIT0, NBIT1 Bit line EN Auxiliary circuit activation signal line N1, N2 Storage node ND1 NAND circuits MP1, MP2, TP1 to TP6 P-type transistors MN1 to MN4, TN1 to TN19 N-type transistor RGBIT Global bit line WL Word line

Claims (13)

A plurality of memory cells;
A word line connected to the memory cell;
A first bit line and a second bit line connected to the memory cell;
Global bit lines,
A read assist circuit for controlling the potential of the first bit line to a predetermined potential based on a given control signal and a signal on the second bit line;
A semiconductor memory device comprising: a reading unit that controls the potential of the global bit line to a predetermined potential based on the potential of the first bit line.   The read auxiliary circuit grounds the first bit line when the control signal is in an active state and the potential of the second bit line is equal to or higher than a predetermined potential. Item 2. The semiconductor memory device according to Item 1. The readout auxiliary circuit includes
A first transistor to which the control signal is supplied to a gate electrode;
And a second transistor electrically connected to the second bit line,
2. The semiconductor memory device according to claim 1, wherein the first and second transistors are connected in series between the first bit line and ground. The readout auxiliary circuit includes
A first transistor to which the control signal is supplied to a gate electrode;
A P-type second transistor having a gate electrode electrically connected to the second bit line and a source voltage applied to the source electrode;
An N-type third transistor having a gate electrode electrically connected to the second bit line, a source electrode grounded, and a drain electrode connected to the drain electrode of the second transistor;
The semiconductor memory device according to claim 1, wherein the first transistor is connected to a drain electrode of the second transistor and the first bit line. The readout auxiliary circuit includes
A P-type first transistor having a gate electrode electrically connected to the second bit line and a source voltage applied to the source electrode;
A second transistor to which the control signal is supplied to the gate electrode;
An N-type third transistor whose gate electrode is electrically connected to the second bit line;
2. The semiconductor memory device according to claim 1, wherein the second and third transistors are connected in series between a drain of the first transistor and a ground. The readout auxiliary circuit includes
A third transistor to which the control signal is supplied to the gate electrode;
And a fourth transistor having a gate electrode electrically connected to the first bit line,
4. The semiconductor memory device according to claim 3, wherein the third and fourth transistors are connected in series between the second bit line and ground. The readout auxiliary circuit includes
A fourth transistor to which the control signal is supplied to the gate electrode;
A P-type fifth transistor having a gate electrode electrically connected to the first bit line and a source voltage applied to the source electrode;
An N-type sixth transistor having a gate electrode electrically connected to the first bit line, a source electrode grounded, and a drain electrode connected to the drain electrode of the fifth transistor;
The semiconductor memory device according to claim 4, wherein the fourth transistor is connected to a drain electrode of the fifth transistor and the second bit line. The readout auxiliary circuit includes
A P-type fourth transistor having a gate electrode electrically connected to the first bit line and a predetermined power supply voltage applied to the source electrode;
A fifth transistor to which the control signal is supplied to the gate electrode;
An N-type sixth transistor whose gate electrode is electrically connected to the second bit line;
6. The semiconductor memory device according to claim 5, wherein the fifth and sixth transistors are connected in series between a drain of the fourth transistor and a ground.   2. The semiconductor memory device according to claim 1, wherein the control signal is activated almost simultaneously with the activation of the word line.   2. The semiconductor memory device according to claim 1, wherein the control signal is activated before the word line is activated.   2. The semiconductor memory device according to claim 1, wherein a plurality of the read auxiliary circuits are connected to the first and second bit lines, and the plurality of read auxiliary circuits are simultaneously activated.   2. The semiconductor memory device according to claim 1, wherein two or more read auxiliary circuits are arranged for a plurality of memory cells connected to the same first and second bit lines. .   7. The layout of the plurality of transistors included in the read auxiliary circuit is the same as the layout of the plurality of transistors included in the memory cell except for a connection relation of metal wiring. 9. The semiconductor memory device according to any one of 8.

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