JP2007074421A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of improving an operation speed at a low resolution.
A first pixel column 1a including a plurality of pixels 11a, 11b,... Arranged in a fixed direction and generating signal charges by photoelectric conversion, and arranged in parallel with the first pixel column 1a, The first storage gate column 3a including a plurality of storage gates 31a, 31b,... For storing the signal charges generated by the pixel column 1a, and the first storage gate column 3a are stored in the respective storage gates at low resolution. And a first CCD register 5a that performs synthesis for every two of the signal charges and sequentially transfers the synthesized signal charges.
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device that sequentially transfers signal charges obtained by photoelectric conversion.

  A linear image sensor which is one of solid-state imaging devices includes a pixel row in which a plurality of pixels are arranged in a line. Signal charges generated by photoelectric conversion in each pixel are transferred to a CCD register including a plurality of transfer electrodes via a shift gate. Two transfer electrodes to which complementary transfer clocks are applied are assigned to one pixel (see, for example, Patent Document 1). A floating diffusion region for accumulating signal charges is provided at the output stage of the CCD register. When the resolution is lower than the normal (maximum) resolution, the operating frequency of the CCD register is increased and signal charges are synthesized in the floating diffusion region. Low resolution operation is realized by sampling the signal charges for a plurality of pixels accumulated in the floating diffusion region together.

Therefore, if the resolution is set to 1/2 and 1/4 of the normal resolution, the operating frequency of the CCD register is doubled and quadrupled, respectively, which is not suitable for high-speed driving and the sampling period is also shortened. Therefore, there is a limit to improving the operation speed at the time of low resolution. In addition, since the signal charges are synthesized in the floating diffusion region, when the signal charges from each pixel are transferred to the floating diffusion region, dark output components that are noise components are accumulated and the S / N ratio is deteriorated. Furthermore, since the number of transfer stages of the CCD register is large, the coupling capacitance between the transfer electrodes is large, so it is necessary to supply a high clock amplitude to the CCD register.
JP 2004-342746 A

  The present invention provides a solid-state imaging device capable of improving the operation speed at the time of low resolution.

  According to one aspect of the present invention, a first pixel column including a plurality of pixels arranged in a certain direction and generating signal charges by photoelectric conversion, and arranged in parallel with the first pixel column, the first pixel column is generated. The first accumulation gate row including a plurality of accumulation gates for accumulating the obtained signal charges and at least two of the signal charges accumulated in the respective accumulation gates of the first accumulation gate row at the time of low resolution There is provided a solid-state imaging device including a first CCD register that sequentially transfers the synthesized signal charges.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state imaging device which can improve the operation speed at the time of low resolution can be provided.

  Next, first and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings in the first and second embodiments, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in light of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

(First embodiment)
As shown in FIG. 1, the solid-state imaging device according to the first embodiment of the present invention is a first pixel including a plurality of pixels 11a, 11b,... That are arranged in a fixed direction and generate signal charges by photoelectric conversion. A first storage gate column 3a including a plurality of storage gates 31a, 31b,..., Which are arranged in parallel with the first pixel column 1a and store signal charges, and a first storage gate at a low resolution The first CCD register 5a for synthesizing at least two of the signal charges accumulated in the accumulation gates 31a, 31b,... Of the column 3a and sequentially transferring the synthesized signal charges. Here, the “constant direction” means, for example, the main scanning direction when a line sensor is used as the solid-state imaging element unit 10a shown in FIG. “At the time of low resolution” means, for example, the resolution of 1 / 2n (n: an integer of 1 or more) of the normal (maximum) resolution, that is, 1/2, 1/4, 1/8,. Operation at a resolution of. In the following first embodiment, a case will be described in which operations of normal resolution, 1/2 resolution, and 1/4 resolution are executed. In addition, each code | symbol described in each block (member) shown in FIG. 1 has shown the pulse (signal) name applied to each block.

  1 includes a first shift gate 2a, a first storage gate row 3a, and a first CCD register 5a disposed between the first pixel row 1a and the first storage gate row 3a. Are further provided with a first barrier gate 4a disposed between and a charge detector 50a disposed at an end of the first CCD register 5a. In response to the shift gate control pulse SH, the first shift gate 2a shifts the plurality of signal charges S1, S2,... Generated by the first pixel column 1a to the first accumulation gate column 3a. The timing of transferring the signal charge from the first pixel column 1a to the first accumulation gate column 3a is controlled by the shift gate control pulse SH. The charge detector 50a detects the signal charge transferred by the first CCD register 5a.

  The first and fifth accumulation gates 31a and 31e read out signal charges from the first pixel column 1a and transfer the signal charges to the first CCD register 5a in response to the first accumulation gate control pulse ST1. The second and sixth accumulation gates 31b and 31f read the signal charge from the first pixel column 1a in response to the second accumulation gate control pulse ST2, and transfer the signal charge to the first CCD register 5a. The third and seventh accumulation gates 31c and 31g read the signal charge from the first pixel column 1a in response to the third accumulation gate control pulse ST3, and transfer the signal charge to the first CCD register 5a. The fourth and eighth accumulation gates 31d and 31h read the signal charge from the first pixel column 1a according to the fourth accumulation gate control pulse supplied ST4, and transfer the signal charge to the first CCD register 5a. Therefore, any of the signal charges stored in the storage gates 31a, 31b,... Of the first storage gate array 3a is transferred to the first CCD register 5a by the first to fourth storage gate control pulses ST1 to ST4. Is selected.

  The first barrier gate 4a controls the timing at which signal charges are transferred from the first accumulation gate array 3a to the first CCD register 5a in accordance with the barrier gate control pulse BG, and from the first CCD register 5a to the first accumulation gate array 3a. The signal charge is controlled so as not to be transferred toward the.

  The first CCD register 5a includes a plurality of transfer electrodes 51a to 51c and a plurality of combined electrodes 56a, 56b,. A second transfer control clock P2 is supplied to the first and third transfer electrodes 51a and 51c. The first transfer control clock P1 is supplied to the second transfer electrode 51b.

  A first transfer control clock P1 is supplied to the first synthetic electrode 56a, the third synthetic electrode 56c,. The second transfer control clock P2 is supplied to the second composite electrode 56b, the fourth composite electrode 56d,. Note that the first and second transfer control clocks P1 and P2 have an opposite phase (complementary) relationship.

  As an example, when the first transfer control clock P1 is at a high (H) level and the second transfer control clock P2 is at a low (L) level, the region under the fourth composite electrode 56d is shifted to the region under the third composite electrode 56c. Signal charge is transferred. Further, the signal charge is transferred from the region under the second synthetic electrode 56b to the region under the first synthetic electrode 56a. The signal charge is transferred from the region under the third transfer electrode 51c to the region under the second transfer electrode 51b.

  On the other hand, when the first transfer control clock P1 is L level and the second transfer control clock P2 is H level, the signal charge is transferred from the region under the third composite electrode 56c to the region under the second composite electrode 56b. Is done. The signal charge is transferred from the region below the first synthetic electrode 56a to the region below the third transfer electrode 51c. Signal charges are transferred from the region under the second transfer electrode 51b to the region under the first transfer electrode 51a.

  As a result, the first CCD register 5a transfers the signal charge to the charge detection unit 50a in synchronization with the first and second transfer control clocks P1 and P2. The charge detection unit 50a includes a final stage gate 55a, a floating diffusion region 52, a reset gate 53, and a reset drain region 54. The final stage gate 55a injects signal charges into the floating diffusion region 52 in response to the final stage gate control pulse PA having the same phase as the first transfer control clock P1.

  In response to the reset pulse RS, the reset gate 53 transfers the signal charge remaining in the floating diffusion region 52 to the reset drain region 54 after reading (sampling) the signal charge from the floating diffusion region 52, Reset. The signal charges accumulated in the floating diffusion region 52 are sequentially sent to the memory 103, for example, as an output signal OS via the output amplifier 102 shown in FIG.

  The first to fourth accumulation gate control pulses ST1 to ST4, the shift gate control pulse SH, the barrier gate control pulse BG, the first transfer control clock P1, the second transfer control clock P2, the final stage gate control pulse PA, The reset pulse RS is supplied by, for example, the control unit 101 shown in FIG.

  Next, an outline of each operation of normal resolution, 1/2 resolution, and 1/4 resolution will be described. However, the plurality of pixels 11a, 11b,..., The plurality of storage gates 31a, 31b,... And the plurality of composite electrodes 56a, 56b,. The first to fourth pixels 11a to 11d, the first to fourth storage gates 31a to 31d, and the first and second composite electrodes 56a and 56b will be described as an example.

  In any of the normal resolution, 1/2 resolution, and 1/4 resolution, the first to fourth signal charges S1 to S4 generated by the first to fourth pixels 11a to 11d are connected to the first shift gate 2a. Through the first to fourth storage gates 31a to 31d and once held.

  At the normal resolution, the first to fourth signal charges S1 to S4 accumulated in the first to fourth accumulation gates 31a to 31d are sequentially transferred. That is, the first signal charge S1 stored in the region under the first storage gate 31a is transferred to the region under the first composite electrode 56a, and then the second signal charge stored in the region under the second storage gate 31b. S2 is transferred to the region below the first synthetic electrode 56a. Next, the third signal charge S3 stored in the region under the third storage gate 31c is transferred to the region under the second synthesis electrode 56b, and then the fourth signal charge stored in the region under the fourth storage gate 31d. S4 is transferred to the region below the second synthetic electrode 56b.

  On the other hand, at the half resolution, the first and second signal charges S1 and S2 accumulated in the region under the first and second accumulation gates 31a and 31b are simultaneously transferred to the region under the first synthesis electrode 56a and synthesized. Is done. Thereafter, the third and fourth signal charges S3 and S4 accumulated in the region under the third and fourth accumulation gates 31c and 31d are simultaneously transferred to the region under the second synthesis electrode 56b and synthesized. The combined signal charge is transferred toward the charge detector 50a.

  Further, at the 1/4 resolution, the third and fourth signal charges S3 and S4 stored in the region under the third and fourth storage gates 31c and 31d are simultaneously transferred to the region under the second composite electrode 56b. Synthesized. The signal charge synthesized by the second synthesis electrode 56b is transferred to a region below the first synthesis electrode 56a. Thereafter, the first and second signal charges S1 and S2 accumulated in the region under the first and second accumulation gates 31a and 31b are simultaneously transferred to the region under the first synthetic electrode 56a. As a result, the first to fourth signal charges S1 to S4 are all synthesized in the region below the first synthesis electrode 56a. The combined first to fourth signal charges S1 to S4 are transferred toward the charge detection unit 50a.

  In this way, at the time of low resolution, the first and second transfer control clocks are synthesized by synthesizing the signal charges in the regions below the plurality of synthesis electrodes 56a, 56b,. It is possible to read out signal charges at high speed without changing the clock frequencies of P1 and P2.

  As shown in FIG. 3A, for example, the plurality of pixels 11a, 11b,... In the first pixel column 1a include phosphorous (P), antimony ( Sb) or an n-type semiconductor region formed by doping an n-type impurity such as arsenic (As). As each of the pixels 11a, 11b,..., A photoelectric conversion element such as a pn junction diode (photodiode) can be used.

  A gate insulating film (not shown) such as a silicon oxide film is provided on the p-type semiconductor layer 202, and a first shift gate 2a, a plurality of storage gates 31a, 31b,. A barrier gate 4a, a plurality of transfer electrodes 51a to 51b, and a plurality of composite electrodes 56a, 56b,.

  The first shift gate 2a, the plurality of storage gates 31a, 31b, ..., the first barrier gate 4a, the plurality of transfer electrodes 51a to 51b, the plurality of composite electrodes 56a, 56b, ..., the final stage gate 55a, As a material of each reset gate 53, polysilicon, silicide, metal, or the like can be used.

  As each of the pixels 11a, 11b,..., A photoelectric conversion element such as a pn junction diode (photodiode) can be used. The first shift gate 2a, the plurality of storage gates 31a, 31b,..., The first barrier gate 4a, the plurality of transfer electrodes 51a to 51b, the plurality of composite electrodes 56a, 56b,. As the materials of the reset gate 53, polysilicon, silicide, metal, or the like can be used.

  The first signal charge S1 generated by photoelectric conversion in the pixel 11a is accumulated in a potential well formed in the p-type semiconductor layer 202 by the n-type semiconductor region of the pixel 11a itself. The signal charges S2, S3,... Generated in the other pixels 11b, 11c,.

  When the shift gate control pulse SH and the first accumulation gate control pulse ST1 are at the H level, as shown in FIG. 3B, the first signal charge S1 is transferred from the pixel 11a to the first accumulation gate 31a due to the electrostatic induction effect. Transferred to the area.

  Further, when the first accumulation gate control pulse ST1 is set to L level, the barrier gate control pulse BG is set to H level, and the first transfer control clock P1 is set to H level, as shown in FIG. S1 is transferred from the region under the first storage gate 31a to the region under the first composite electrode 56a.

  Further, as shown in FIG. 4A, the charge detection unit 50a includes a final gate 55a having a MOS gate structure, an output gate 57 having a MOS gate structure, and an n-type semiconductor region provided on the surface of the p-type semiconductor layer 202. A floating diffusion region 52, a reset gate 53 having a MOS gate structure, and a reset drain region 54 made of an n-type semiconductor region. 4A, illustration of a gate insulating film such as a silicon oxide film disposed on the p-type semiconductor layer 202 is omitted as in FIG. 3A.

  The final stage gate 55 a is disposed between the first transfer electrode 51 a and the output gate 57. As shown in FIGS. 4B to 4D, the final stage gate 55a adjusts the timing for injecting the signal charges sequentially transferred through the first CCD register 5a into the floating diffusion region 52. As shown in FIG. 4D, the output gate 57 injects the signal charge transferred to the region under the final stage gate 55a via the first transfer electrode 51a and the second transfer electrode 51b into the floating diffusion region 52. .

  The signal charge injected into the floating diffusion region 52 is transmitted to the output amplifier 102 shown in FIG. 2 as a potential change. The reset gate 53 is a gate electrode of a MOS transistor having the floating diffusion region 52 as a lease and the reset drain region 54 as a drain. By applying an H level reset pulse RS to the reset gate 53, the floating diffusion region 52 is set to a predetermined potential.

  Next, the operation at the normal resolution in the solid-state imaging device according to the first embodiment of the present invention will be described with reference to the time chart shown in FIG. However, the operation for one cycle of the shift gate control pulse SH will be described. The plurality of pixels 11a, 11b,..., The plurality of storage gates 31a, 31b,... And the plurality of composite electrodes 56a, 56b,. The pixels 11a to 11h, the first to eighth storage gates 31a to 31h, and the first to fourth synthesis electrodes 56a to 56d will be described.

  At time t1, the first transfer control clock P1 shown in FIG. 5 (g) is set to H level, and the second transfer control clock P2 shown in FIG. 5 (h) is set to L level. At time t2, the first to fourth accumulation gate control pulses ST1 to ST4 shown in FIGS. 5B to 5E are set to the H level.

  At time t3, when the shift gate control pulse SH shown in FIG. 5A rises, the first to eighth pixels 11a to 11h shown in FIG. ~ Eighth signal charges S1 to S8 are transferred. At time t4, the first accumulation gate control pulse ST1 transitions from the H level to the L level. At time t5, when the barrier gate control pulse BG shown in FIG. 5 (f) rises, the first signal charge S1 is transferred from the region under the first storage gate 31a to the region under the first composite electrode 56a.

  Further, the signal charge S5 is transferred from the region under the fifth storage gate 31e to the region under the third composite electrode 56c. During the period from time t6 to time t7, the first signal charge S1 and the fifth signal charge S5 are transferred to the charge detection unit 50a in synchronization with the first and second transfer control clocks P1 and P2.

  At time t7, the first transfer control clock P1 is set to H level, and the second transfer control clock P2 is set to L level. At time t8, the first to fourth accumulation gate control pulses ST1 to ST4 are set to the H level.

  At time t9, the second accumulation gate control pulse ST2 changes from the H level to the L level. When the barrier gate control pulse BG rises at time t10, the second signal charge S2 is transferred from the region below the second storage gate 31b to the region below the first composite electrode 56a.

  Further, the sixth signal charge S6 is transferred from the region under the sixth accumulation gate 31f to the region under the third composite electrode 56c. During the period from time t11 to t12, the second signal charge S2 and the sixth signal charge S6 are transferred to the charge detection unit 50a in synchronization with the first and second transfer control clocks P1 and P2.

  At time t12, the first transfer control clock P1 is set to L level, and the second transfer control clock P2 is set to H level. At time t13, the first to fourth accumulation gate control pulses ST1 to ST4 are set to the H level.

  At time t14, the third accumulation gate control pulse ST3 changes from the H level to the L level. When the barrier gate control pulse BG rises at time t15, the third signal charge S3 is transferred from the region below the third storage gate 31c to the region below the second composite electrode 56b.

  Further, the seventh signal charge S7 is transferred from the region under the seventh accumulation gate 31g to the region under the fourth composite electrode 56d. During the period from time t16 to t17, the third signal charge S3 and the seventh signal charge S7 are transferred to the charge detection unit 50a in synchronization with the first and second transfer control clocks P1 and P2.

  At time t17, the first transfer control clock P1 is set to L level, and the second transfer control clock P2 is set to H level. At time t18, the first to fourth accumulation gate control pulses ST1 to ST4 are set to the H level.

  At time t19, the fourth accumulation gate control pulse ST4 changes from the H level to the L level. When the barrier gate control pulse BG rises at time t20, the fourth signal charge S4 is transferred from the region below the fourth storage gate 31d to the region below the second composite electrode 56b.

  In addition, the eighth signal charge S8 is transferred from the region under the eighth storage gate 31h to the region under the fourth composite electrode 56d. In the period from time t21 to t22, the fourth signal charge S4 and the eighth signal charge S8 are transferred to the charge detection unit 50a in synchronization with the first and second transfer control clocks P1 and P2.

  Next, with reference to a time chart shown in FIG. 6, the operation at 1/2 resolution in the solid-state imaging device according to the first embodiment of the present invention will be described. However, redundant description of operations similar to those at normal resolution is omitted.

  At time t4, the first storage gate control pulse ST1 shown in FIG. 6B and the second storage gate control pulse ST2 shown in FIG. 6C transition from the H level to the L level. When the barrier gate control pulse BG shown in FIG. 6F rises at time t5, the first and second signal charges are transferred from the region below the first and second storage gates 31a and 31b to the region below the first composite electrode 56a. S1 and S2 are transferred. As a result, the first and second signal charges S1 and S2 are combined in the region under the first combined electrode 56a, and a combined charge (S1 + S2) is generated.

  Further, the fifth and sixth signal charges S5 and S6 are transferred from the region under the fifth and sixth storage gates 31e and 31f to the region under the third composite electrode 56c. Therefore, the fifth and sixth signal charges S5 and S6 are combined in the region below the third combined electrode 56c, and a combined charge (S5 + S6) is generated. In the period from time t6 to time t7, the combined charge (S1 + S2) and the combined charge (S5 + S6) are transferred to the charge detection unit 50a in synchronization with the first and second transfer control clocks P1 and P2.

  At time t9, the third storage gate control pulse ST3 shown in FIG. 6C and the fourth storage gate control pulse ST4 shown in FIG. 6D transition from the H level to the L level. When the barrier gate control pulse BG rises at time t10, the third and fourth signal charges S3 and S4 are transferred from the region below the third and fourth storage gates 31c and 31d to the region below the second composite electrode 56b. . As a result, the third and fourth signal charges S3 and S4 are combined in the region below the second combined electrode 56b, and a combined charge (S3 + S4) is generated.

  In addition, the seventh and eighth signal charges S7 and S8 are transferred from the region under the seventh and eighth storage gates 31g and 31h to the region under the fourth composite electrode 56d. Therefore, the seventh and eighth signal charges S7 and S8 are combined in the region below the fourth combined electrode 56d, and a combined charge (S7 + S8) is generated. In the period from time t11 to t12, the combined charge (S3 + S4) and the combined charge (S7 + S8) are transferred to the charge detection unit 50a in synchronization with the first and second transfer control clocks P1 and P2.

  Next, with reference to the time chart shown in FIG. 7, the operation at the 1/4 resolution in the solid-state imaging device according to the first embodiment of the present invention will be described. However, redundant description of operations similar to those at normal resolution is omitted.

  At time t4, the third and fourth accumulation gate control pulses ST3 and ST4 shown in FIGS. 7D and 7E transition from the H level to the L level. When the barrier gate control pulse BG shown in FIG. 7F rises at time t5, the third and fourth signal charges are transferred from the region below the third and fourth storage gates 31c and 31d to the region below the second composite electrode 56b. S3 and S4 are transferred. As a result, the third and fourth signal charges S3 and S4 are combined in the region below the second combined electrode 56b, and a combined charge (S3 + S4) is generated.

  In addition, the seventh and eighth signal charges S7 and S8 are transferred from the region under the seventh and eighth storage gates 31g and 31h to the region under the fourth composite electrode 56d. Therefore, the seventh and eighth signal charges S7 and S8 are combined in the region below the fourth combined electrode 56d, and a combined charge (S7 + S8) is generated.

  At time t6, the first transfer control clock P1 shown in FIG. 7 (g) changes from the L level to the H level, and the second transfer control clock P2 shown in FIG. 7 (h) changes from the H level to the L level. Therefore, the synthetic charge (S3 + S4) under the second synthetic electrode 56b is transferred to the region under the first synthetic electrode 56a. The synthetic charge (S7 + S8) under the fourth synthetic electrode 56d is transferred to the region under the third synthetic electrode 56c.

  At time t7, the third and fourth accumulation gate control pulses ST3 and ST4 transition from the H level to the L level. At time t7, the first and second accumulation gate control pulses ST2 are set to L level. When the barrier gate control pulse BG rises at time t8, the first and second signal charges S1 and S2 are transferred from the region below the first and second storage gates 31a and 31b to the region below the first composite electrode 56a. . As a result, the first and second signal charges S1 and S2 and the combined charge (S3 + S4) are combined in the region below the first combined electrode 56a, and a combined charge (S1 + S2 + S3 + S4) is generated.

  Further, the fifth and sixth signal charges S5 and S6 are transferred from the region under the fifth and sixth storage gates 31e and 31f to the region under the third composite electrode 56c. Therefore, the fifth and sixth signal charges S5 and S6 and the combined charge (S7 + S8) are combined in the region below the third combined electrode 56c, and a combined charge (S5 + S6 + S7 + S8) is generated. In the period from time t9 to t10, the combined charge (S1 + S2 + S3 + S4) and the combined charge (S5 + S6 + S7 + S8) are transferred to the charge detection unit 50a in synchronization with the first and second transfer control clocks P1 and P2.

  Next, in order to explain the effect of the solid-state imaging device according to the first embodiment, the detailed operation of the solid-state imaging device according to the first embodiment will be described in comparison with a comparative example. The solid-state imaging device according to the comparative example is assumed to have a configuration that does not include the first accumulation gate array 3a and the first barrier gate 4a shown in FIG.

  Since the operation at the normal resolution is almost the same as that in the comparative example, the detailed operation of the solid-state imaging device according to the first embodiment will be described with reference to the time chart shown in FIG. In the period from time t1 to time t2 in FIG. 8, the reset pulse RS shown in FIG. 8C is set to the H level. When the reset pulse RS is set to H level, the signal charge existing in the floating diffusion region 52 shown in FIG. 1 is transferred to the reset drain region 54. The period from time t2 to t3 corresponds to a signal reference period in which sampling is performed. In the signal reference period, the output signal OS is set to a constant potential, for example, about 5V. A period from time t3 to t4 corresponds to a signal period in which sampling is performed.

  The operation at the half resolution of the comparative example is shown in the time chart of FIG. A period from time t2 to t3 in FIG. 9 is a signal reference period. In order to synthesize the signal charge in the floating diffusion region, the signal charge is synthesized in the period of time t4 to t5 with respect to the signal charge accumulated in the floating diffusion region in the period of time t2 to t3 in FIG. To do. Since it is required to synthesize signal charges for two pixels within one cycle of the reset pulse RS shown in FIG. 9C, the first and second transfer control shown in FIGS. 9A and 9B. The clocks P1 and P2 are set to twice the frequency of the first and second transfer control clocks P1 and P2 shown in FIGS.

  On the other hand, FIG. 10 shows the operation of the solid-state imaging device according to the first embodiment of the present invention at 1/2 resolution. A period from time t2 to t3 in FIG. 10 is a signal reference period, and a period from time t3 to t4 is a signal period. The solid-state imaging device according to the first embodiment of the present invention synthesizes signal charges for two pixels at the plurality of combined electrodes 56a, 56b,... Shown in FIG. Therefore, it is not necessary to synthesize signal charges in the floating diffusion region 52. Accordingly, the first and second transfer control clocks P1 and P2 shown in FIGS. 10 (a) and 10 (b) are equal to the first and second transfer control clocks P1 and P2 shown in FIGS. 8 (a) and 8 (b). The frequency is good.

  Further, the operation at the 1/4 resolution of the comparative example is shown in the time chart of FIG. A period from time t2 to t3 in FIG. 11 is a signal reference period, and a period from time t6 to t7 is a signal period. Since it is required to synthesize signal charges for four pixels within one cycle of the reset pulse RS shown in FIG. 11C, the first and second transfer controls shown in FIGS. 11A and 11B. The clocks P1 and P2 are set to a frequency four times that of the first and second transfer control clocks P1 and P2 shown in FIGS. As a result, as shown in FIG. 11D, at the 1/4 resolution, the signal reference period and the signal period are very short. Therefore, it is difficult to perform sampling with high accuracy.

  On the other hand, the operation at the 1/4 resolution of the solid-state imaging device according to the first embodiment of the present invention is shown in the time chart of FIG. A period from time t2 to t3 in FIG. 12 is a signal reference period, and a period from time t3 to t4 is a signal period. The solid-state imaging device according to the first embodiment of the present invention synthesizes signal charges for four pixels at the plurality of combined electrodes 56a, 56b,... Shown in FIG. Therefore, it is not necessary to synthesize signal charges in the floating diffusion region 52. Accordingly, the first and second transfer control clocks P1 and P2 shown in FIGS. 12 (a) and (b) are equal to the first and second transfer control clocks P1 and P2 shown in FIGS. 8 (a) and (b). The frequency is good.

  As described above, according to the solid-state imaging device according to the first embodiment of the present invention, the signal charge is not the floating diffusion region 52 but the plurality of composite electrodes 56a, 56b,. By synthesizing in (2), a low-resolution operation can be realized without increasing the frequencies of the first and second transfer control clocks P1 and P2. Since the sampling period such as the signal reference period and the signal period can be secured for a long time, the sampling operation can be performed stably. Further, since the signal charges can be held by the plurality of storage gates 31a, 31b,..., The number of transfer stages of the first CCD register 5a can be reduced, and the signal charges can be transferred with a low clock amplitude. Further, the dark output component which is a noise component is not cumulatively added during transfer, and the S / N ratio is improved.

(Second Embodiment)
As shown in FIG. 13, the solid-state imaging device according to the second embodiment of the present invention includes a second pixel column 1b, a second shift gate 2b, a second accumulation gate column 3b, a second barrier gate 4b, and a second CCD register 5b. 1 further differs from FIG. 1 in that a drain region 60 and a switch gate 59 are further provided. Other configurations are the same as those of the solid-state imaging device according to the first embodiment.

  For example, the second pixel column 1b is disposed adjacent to the first pixel column 1a. The second accumulation gate row 3b is arranged in parallel with the second pixel row 1b. The second shift gate 2b is disposed between the second pixel column 1b and the second accumulation gate column 3b. The drain region 60 is branched from the end of the second CCD register 5b. The switch gate 59 is provided between the drain region 60 and the end of the second CCD register 5b. The charge detector 50b is arranged in a direction in which the ends of the first and second CCD registers 5a and 5b are gathered.

  Further, the second pixel column 1b includes a plurality of pixels 11b, 11d,... Arranged so as to be shifted from the pixels 11a, 11c,. The second accumulation gate row 3b includes a plurality of accumulation gates 32a, 32b,... For accumulating signal charges generated by the second pixel row 1b. The second shift gate 2b shifts the signal charge generated by the second pixel column 1b to the second accumulation gate column 3b in response to the shift gate control pulse SH. The second CCD register 5b combines at least two of the signal charges stored in the respective storage gates of the second storage gate row 3b at the time of low resolution, and sequentially transfers the combined signal charges. The charge detector 50b selectively detects the signal charges transferred via the first and second CCD registers 5a and 5b. The drain region 60 absorbs signal charges generated in each pixel of the second pixel column 1b. The switch gate 59 injects signal charges generated in the respective pixels of the second pixel column 1b into the drain region 60 at the time of low resolution.

  The charge detection unit 50b includes a first final stage gate 55a, a second final stage gate 55b, a floating diffusion region 52, a reset gate 53, and a reset drain region 54. A first final stage gate control pulse PA having the same phase as the first transfer control clock P1 is supplied to the first final stage gate 55a. A second final stage gate control pulse PB having the same phase as the second transfer control clock P2 is supplied to the second final stage gate 55b. In the normal resolution, the first and second final stage gates 55 a and 55 b inject signal charges into the floating diffusion region 52 alternately.

  The second CCD register 5b includes a plurality of transfer electrodes 57a to 57d and a plurality of combined electrodes 58a, 58b,. The number of the plurality of transfer electrodes 57a to 57d of the second CCD register 5b is one more than the number of the transfer electrodes 51a to 51d of the first CCD register 5a. By increasing one transfer electrode, the first transfer control clock P1 is supplied to the first transfer electrode 57a of the second CCD register 5b, and the second transfer control clock P2 is supplied to the first transfer electrode 51a of the first CCD register 5a. Is supplied.

  The solid-state imaging device unit 10b illustrated in FIG. 13 realizes operations at a resolution of 1/2, 1/4, and 1/8 of the normal resolution as the low resolution operation. When the resolution is low, the switch gate 59 is opened, and all the signal charges S2, S4,... Generated in the second pixel column 1b are absorbed by the drain region 60. As a result, the half resolution operation is executed only by opening the switch gate 59.

  Further, by performing the 1/2 and 1/4 resolution operations described in the first embodiment in a state where the switch gate 59 is opened, the solid-state imaging device unit 10b shown in FIG. An operation with 8 resolutions is realized.

  Fig.14 (a) is typical sectional drawing between CC of FIG. Also in FIG. 14A, illustration of a gate insulating film such as a silicon oxide film disposed on the p-type semiconductor layer 202 is omitted. A switch gate 59 is disposed between the first transfer electrode 57 a of the second CCD register 5 b and the drain region 60. An H level voltage is applied to the switch gate 59 at the time of low resolution. As a result, as shown in FIGS. 14B and 14C, when an H level voltage is applied to the switch gate 59, the signal existing in the region under the first transfer electrode 57a of the second CCD register 5b. The charge is absorbed by the drain region 60 through the region under the switch gate 59.

  Next, the operation at the normal resolution in the solid-state imaging device according to the second embodiment of the present invention will be described with reference to the time chart shown in FIG. However, the operation for one cycle of the shift gate control pulse SH will be described, and redundant description of the same operation as that of the solid-state imaging device according to the first embodiment will be omitted.

  When the shift gate control pulse SH shown in FIG. 15A rises at time t3, each storage gate 31a of the first storage gate row 3a from the first pixel 11a, the third pixel 11c,. The first signal charge S1, the third signal charge S3,... Are transferred to the lower region 31b,. Similarly, the second signal charge S2, the fourth signal charge S4, the region below the second storage gate row 3b from the second pixel 11b, the fourth pixel 11d,. ... are transferred.

  When the barrier gate control pulse BG shown in FIG. 15 (f) rises at time t5, the region from the first storage gate 31a in the first storage gate row 3a to the region under the first composite electrode 56a in the first CCD register 5a. The first signal charge S1 is transferred. The ninth signal charge S9 is transferred from the region under the fifth storage gate 31e of the first storage gate row 3a to the region under the third composite electrode 56c of the first CCD register 5a.

  Further, the second signal charge S2 is transferred from the region under the first storage gate 32a of the second storage gate row 3b to the region under the first composite electrode 58a of the second CCD register 5b. The tenth signal charge S10 is transferred from the region under the fifth storage gate 31e of the second storage gate row 3b to the region under the third composite electrode 56c of the first CCD register 5a.

  In the period from time t6 to time t7, the first signal charge S1, the second signal charge S2, the ninth signal charge S9, and the tenth signal charge S10 are synchronized with the first and second transfer control clocks P1 and P2. The charge is transferred to the charge detector 50b.

  Similarly, in the period from time t11 to time t12, the third signal charge S3, the fourth signal charge S4, the eleventh signal charge S11, and the twelfth signal charge S12 are supplied to the first and second transfer control clocks P1 and P2. Is transferred to the charge detector 50b in synchronization with

  In the period from time t16 to t17, the fifth signal charge S5, the sixth signal charge S6, the thirteenth signal charge S13, and the fourteenth signal charge S14 are synchronized with the first and second transfer control clocks P1 and P2. The charge is transferred to the charge detector 50b.

  In the period from time t21 to t22, the seventh signal charge S7, the eighth signal charge S8, the fifteenth signal charge S15, and the sixteenth signal charge S16 are synchronized with the first and second transfer control clocks P1 and P2. The charge is transferred to the charge detector 50b.

  Next, with reference to a time chart shown in FIG. 16, an operation at half resolution in the solid-state imaging device according to the second embodiment of the present invention will be described. However, overlapping description of operations similar to those of the solid-state imaging device according to the first embodiment is omitted. At half resolution, an H level voltage is applied to the switch gate 59.

  At time t3, the first accumulation gate control pulse ST1 changes from the H level to the L level. When the barrier gate control pulse BG shown in FIG. 16 (f) rises at time t4, the region from the first storage gate 31a in the first storage gate row 3a to the region under the first composite electrode 56a in the first CCD register 5a. The first signal charge S1 is transferred. The ninth signal charge S9 is transferred from the region under the fifth storage gate 31e of the first storage gate row 3a to the region under the third composite electrode 56c of the first CCD register 5a.

  Further, the second signal charge S2 is transferred from the region under the first storage gate 32a of the second storage gate row 3b to the region under the first composite electrode 58a of the second CCD register 5b. The tenth signal charge S10 is transferred from the region under the fifth storage gate 32e of the second storage gate row 3b to the region under the third composite electrode 58c of the second CCD register 5b.

  In the period from time t5 to t6, the first signal charge S1, the second signal charge S2, the ninth signal charge S9, and the tenth signal charge S10 are synchronized with the first and second transfer control clocks P1 and P2. The data is transferred toward the charge detection unit 50b. However, since the second signal charge S2 and the tenth signal charge S10 are absorbed by the drain region 60 that is branched from the end of the second CCD register 5b on the charge detection unit 50b side, the charge detection unit 50b Not reach. Therefore, the first signal charge S1 and the ninth signal charge S9 are transferred to the charge detection unit 50b.

  Similarly, in the period from time t10 to t11, the third signal charge S3 and the eleventh signal charge S11 are transferred to the charge detection unit 50b in synchronization with the first and second transfer control clocks P1 and P2. During the period from time t16 to t17, the fifth signal charge S5 and the thirteenth signal charge S13 are transferred to the charge detection unit 50b in synchronization with the first and second transfer control clocks P1 and P2. In the period from time t21 to t22, the seventh signal charge S7 and the fifteenth signal charge S15 are transferred to the charge detection unit 50b in synchronization with the first and second transfer control clocks P1 and P2.

  Next, with reference to a time chart shown in FIG. 17, an operation at ¼ resolution in the solid-state imaging device according to the second embodiment of the present invention will be described. However, overlapping description of operations similar to those of the solid-state imaging device according to the first embodiment is omitted. At 1/4 resolution, an H level voltage is applied to the switch gate 59.

  At time t4, the first accumulation gate control pulse ST1 shown in FIG. 17B and the second accumulation gate control pulse ST2 shown in FIG. 17C transition from the H level to the L level. When the barrier gate control pulse BG shown in FIG. 17 (f) rises at time t5, the first composite electrode of the first CCD register 5a starts from the region under the first and second storage gates 31a and 31b of the first storage gate row 3a. The first and third signal charges S1 and S3 are transferred to the region below 56a. As a result, a combined charge (S1 + S3) is generated. In addition, the ninth and eleventh signal charges S9 and S11 are transferred from the region under the fifth and sixth storage gates 31e and 31f of the first storage gate row 3a to the region under the third composite electrode 56c of the first CCD register 5a. , A combined charge (S9 + S11) is generated.

  Further, the second and fourth signal charges S2 and S4 are transferred from the region under the first and second storage gates 32a and 32b of the second storage gate row 3b to the region under the first composite electrode 58a of the second CCD register 5b. , A combined charge (S2 + S4) is generated. The tenth and twelfth signal charges S10 and S12 are transferred from the region under the fifth and sixth storage gates 32e and 32f of the second storage gate row 3b to the region under the third composite electrode 58c of the second CCD register 5b and combined. Charge (S10 + S12) is generated.

  In the period from time t6 to t7, the combined charges (S1 + S3), (S9 + S11), (S2 + S4), and (S10 + S12) are directed to the charge detection unit 50b in synchronization with the first and second transfer control clocks P1 and P2. Forwarded. However, since the combined charges (S2 + S4) and (S10 + S12) are absorbed by the drain region 60, they do not reach the charge detection unit 50b. Therefore, the combined charges (S1 + S3) and (S9 + S11) are transferred to the charge detection unit 50b.

  Similarly, in the period from time t11 to t12, the combined charges (S5 + S7) and (S13 + S15) are transferred to the charge detection unit 50b in synchronization with the first and second transfer control clocks P1 and P2.

  Next, an operation at 1/8 resolution in the solid-state imaging device according to the second embodiment of the present invention will be described with reference to a time chart shown in FIG. However, overlapping description of operations similar to those of the solid-state imaging device according to the first embodiment is omitted. At 1/8 resolution, an H level voltage is applied to the switch gate 59.

  At time t4, the third and fourth accumulation gate control pulses ST3 and ST4 shown in FIGS. 18D and 18E transition from the H level to the L level. When the barrier gate control pulse BG shown in FIG. 18 (f) rises at time t5, the second composite electrode of the first CCD register 5a starts from the region under the third and fourth storage gates 31c and 31d of the first storage gate row 3a. The fifth and seventh signal charges S5 and S7 are transferred to the region below 56b. As a result, a synthetic charge (S5 + S7) is generated. The thirteenth and fifteenth signal charges S13 and S15 are transferred from the regions under the seventh and eighth storage gates 31g and 31h of the first storage gate row 3a to the region under the fourth composite electrode 56d of the first CCD register 5a. , A synthetic charge (S13 + S15) is generated. Signal charges are similarly transferred in the second storage gate row 3b and the second CCD register 5b, but are absorbed in the drain region 60 in the signal charge transfer process by the second CCD register 5b. The operations of the column 3b and the second CCD register 5b are omitted.

  At time t6, the combined charge (S5 + S7) under the second composite electrode 56b of the first CCD register 5a is transferred to the region under the first composite electrode 56a. The synthesized charge (S13 + S15) under the fourth synthetic electrode 56d of the first CCD register 5a is transferred to the region under the third synthetic electrode 56c.

  At time t7, the third and fourth accumulation gate control pulses ST3 and ST4 transition from the L level to the H level. When the barrier gate control pulse BG rises at time t8, the first storage gate row 3a first region from the first and second storage gates 31a and 31b to the region below the first composite electrode 56a of the first CCD register 5a. The third signal charges S1 and S3 are transferred. As a result, the first and third signal charges S1 and S3 and the combined charge (S5 + S7) are combined in the region below the first combined electrode 56a, and a combined charge (S1 + S3 + S5 + S7) is generated.

  In addition, the ninth and eleventh signal charges S9 and S11 are transferred from the region under the fifth and sixth storage gates 31e and 31f of the first storage gate row 3a to the region under the third composite electrode 56c. Therefore, the ninth and eleventh signal charges S9 and S11 and the combined charge (S13 + S15) are combined in the region below the third combined electrode 56c, and a combined charge (S9 + S11 + S13 + S15) is generated. In the period from time t9 to t10, the combined charges (S1 + S3 + S5 + S7) and (S9 + S11 + S13 + S15) are transferred to the charge detection unit 50b in synchronization with the first and second transfer control clocks P1 and P2.

  Next, detailed operation of the solid-state imaging device according to the second embodiment will be described with reference to the time chart shown in FIG. In the period from time t1 to time t2 in FIG. 8, the reset pulse RS shown in FIG. 8C is set to the H level. When the reset pulse RS is set to H level, the signal charge existing in the floating diffusion region 52 shown in FIG. 1 is transferred to the reset drain region 54. The period from time t2 to t3 corresponds to a signal reference period in which sampling is performed. In the signal reference period, the output signal OS is set to a constant potential, for example, 5V. A period from time t3 to t4 corresponds to a signal period in which sampling is performed.

  Next, the time chart shown in FIG. 19 shows the operation at normal resolution, the time chart shown in FIG. 20 shows the operation at 1/2 resolution, and the time chart shown in FIG. 21 shows the operation at 1/4 resolution. The time chart shown in FIG. 22 shows the operation at 1/8 resolution. In any of FIGS. 19 to 22, the period from time t2 to t3 is the signal reference period, and the period from time t3 to t4 is the signal period. Similarly to the first embodiment, in FIGS. 19 to 22, the first and second transfer control clocks P1 and P2 can use the same frequency.

  Thus, according to the solid-state imaging device according to the second embodiment of the present invention, an operation at 1/8 resolution can be realized in addition to 1/2 resolution and 1/4 resolution. Each pixel of the first pixel column 1a and each pixel of the second pixel column 1b are arranged so as to be shifted from each other by half a pixel, so that the resolution between the pixels cannot be obtained at the normal resolution. Since the pixels can be complemented with pixels in other pixel columns, the resolution can be obtained uniformly.

(Other embodiments)
As described above, the present invention has been described according to the first and second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the above description of the embodiment, an example in which one composite electrode is assigned to two storage gates has been described. However, a configuration in which one composite electrode is assigned to three or more storage gates may be employed.

  In the second embodiment, the second pixel column 1b including a plurality of pixels 11b, 11d,... Arranged with a ½ pitch shift from each pixel 11a, 11b,. An example comprising That is, in the second embodiment, the configuration includes two pixel columns, but the configuration may include three or more pixel columns. For example, a configuration including four pixel columns in which each pixel is shifted by ¼ pitch may be used.

  When the solid-state imaging device according to the first embodiment is used as a color linear image sensor, for example, three solid-state imaging device units 10a each having R, G, and B color filters mounted thereon are arranged in parallel. Is done. Since the output signal of each color is output from each solid-state image sensor unit 10a, a color linear image sensor can be obtained. The color filter only needs to be placed on at least the first pixel row 1a of each solid-state image sensor unit 10a. Similarly, the solid-state imaging device according to the second embodiment may be a color linear image sensor.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

1 is a schematic top view of a solid-state imaging element unit of a solid-state imaging device according to a first embodiment of the present invention. 1 is a block diagram illustrating an example of the overall configuration of a solid-state imaging device according to a first embodiment of the present invention. 3A is a schematic cross-sectional view taken along the line AA in FIG. 1, and FIG. 3B is a potential diagram (part 1) of the cross-sectional view of FIG. ) Is a potential diagram (part 2) of the cross-sectional view of FIG. 4A is a schematic cross-sectional view between BB in FIG. 1, FIG. 4B is a potential diagram (part 1) of the cross-sectional view in FIG. 4A, and FIG. ) Is a potential diagram (part 2) of the sectional view of FIG. 4 (a), FIG. 4 (c) is a potential diagram (part 3) of the sectional view of FIG. 4 (a), and FIG. FIG. 5 is a potential diagram (part 4) of the cross-sectional view of FIG. 5 is a time chart illustrating an operation example at normal resolution in the solid-state imaging device according to the first embodiment of the present invention. 3 is a time chart showing an operation example at 1/2 resolution in the solid-state imaging device according to the first embodiment of the present invention. 3 is a time chart illustrating an operation example at a 1/4 resolution in the solid-state imaging device according to the first embodiment of the present invention. 3 is a time chart illustrating a detailed operation example at a normal resolution in the solid-state imaging device according to the first embodiment of the present invention. It is a time chart which shows the operation example at the time of 1/2 resolution in the comparative example of 1st Embodiment of this invention. 3 is a time chart illustrating a detailed operation example at 1/2 resolution in the solid-state imaging device according to the first embodiment of the present invention. It is a time chart which shows the operation example at the time of 1/4 resolution in the comparative example of 1st Embodiment of this invention. 3 is a time chart illustrating a detailed operation example at a ¼ resolution in the solid-state imaging device according to the first embodiment of the present invention. It is the upper surface schematic diagram of the solid-state image sensor part of the solid-state imaging device concerning 2nd Embodiment of this invention. 14A is a schematic cross-sectional view taken along the line C-C in FIG. 13, and FIG. 14B is a potential diagram (part 1) of the cross-sectional view in FIG. ) Is a potential diagram (part 2) of the cross-sectional view of FIG. It is a time chart which shows the operation example at the time of the normal resolution in the solid-state imaging device concerning 2nd Embodiment of this invention. It is a time chart which shows the operation example at the time of 1/2 resolution in the solid-state imaging device concerning 2nd Embodiment of this invention. It is a time chart which shows the operation example at the time of 1/4 resolution in the solid-state imaging device concerning 2nd Embodiment of this invention. It is a time chart which shows the operation example at the time of 1/8 resolution in the solid-state imaging device concerning 2nd Embodiment of this invention. It is a time chart which shows the detailed operation example at the time of the normal resolution in the solid-state imaging device concerning 2nd Embodiment of this invention. It is a time chart which shows the detailed operation example at the time of 1/2 resolution in the solid-state imaging device concerning 2nd Embodiment of this invention. It is a time chart which shows the detailed operation example at the time of 1/4 resolution in the solid-state imaging device concerning 2nd Embodiment of this invention. It is a time chart which shows the detailed operation example at the time of 1/8 resolution in the solid-state imaging device concerning 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... 1st pixel row | line | column 1b ... 2nd pixel row | line | column 2a ... 1st shift gate 2b ... 2nd shift gate 3a ... 1st storage gate row | line | column 3b ... 2nd storage gate row | line | column 4a ... 1st barrier gate 4b ... 2nd barrier gate 5a ... 1st CCD register 5b ... 2nd CCD register 50a, 50b ... Charge detection part 59 ... Switch gate 60 ... Drain region

Claims (5)

A first pixel array including a plurality of pixels arranged in a fixed direction and generating signal charges by photoelectric conversion;
A first storage gate array including a plurality of storage gates arranged in parallel with the first pixel array and storing the signal charges generated by the first pixel array;
A first CCD register for synthesizing at least two of the signal charges accumulated in the respective accumulation gates of the first accumulation gate row at a low resolution and sequentially transferring the synthesized signal charges; A solid-state imaging device. A first shift gate that is disposed between the first pixel column and the first storage gate column and shifts the signal charge generated by the first pixel column to the first storage gate column;
The first barrier gate disposed between the first accumulation gate row and the first CCD register and controlling a signal charge holding period in the first accumulation gate row, further comprising: Solid-state imaging device. A second pixel row including a plurality of pixels arranged in the fixed direction and arranged to be shifted from each pixel of the first pixel row by ½ pitch;
A second storage gate array including a plurality of storage gates arranged in parallel with the second pixel array and storing signal charges generated by the second pixel array;
A second CCD register for performing synthesis for at least two of the signal charges accumulated in the respective accumulation gates of the second accumulation gate row at the time of the low resolution and sequentially transferring the synthesized signal charges;
A charge detection unit that is arranged in a direction in which ends of the first and second CCD registers are gathered to selectively detect the signal charges transferred by the first and second CCD registers;
A drain region that is branched from an end of the second CCD register on the charge detection unit side and absorbs the signal charge generated in each pixel of the second pixel column;
Provided between the drain region and the end of the second CCD register on the charge detection unit side, and transfers the signal charge generated in each pixel of the second pixel column to the drain region at the time of the low resolution. The solid-state imaging device according to claim 1, further comprising: The first CCD register is
Combining the signal charges stored in two adjacent storage gates of the first storage gate row at half resolution as the low resolution,
In the 1/4 resolution as the low resolution, the signal charges accumulated in two adjacent storage gates among the four adjacent storage gates of the first storage gate row are combined to generate a combined charge. 3. The solid-state imaging device according to claim 1, wherein the combined signal is combined with the signal charge stored in the remaining two storage gates after the combined charge is transferred by one stage. The first CCD register is
In the 1/4 resolution as the low resolution, the signal charges accumulated in two adjacent accumulation gates of the first accumulation gate row are combined,
When the resolution is 1/8 resolution, the signal charges accumulated in two adjacent storage gates among the four adjacent storage gates of the first storage gate row are combined to generate a combined charge. 4. The solid-state imaging device according to claim 3, wherein, after the combined charge is transferred by one stage, the signal charge and the combined charge accumulated in the remaining two accumulation gates are combined.

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