JP2007093722A - Drive device - Google Patents

Abstract

In a gate driver for driving a display panel, the function can be set and changed from the outside without increasing the number of input terminals.
A drive circuit of a liquid crystal display panel 10 has a two-chip configuration of a source driver module 20 and a gate driver module 30. When shifting from the standby state to the normal drive state, a standby cancellation period passes. During this standby cancellation period, the logic unit 24 of the source driver module 20 outputs the function setting data externally input and stored in the built-in register to the gate output. The gate driver circuit 32 outputs the signal as an off signal to the gate driver circuit 32. The gate driver circuit 32 regards the input gate off signal GRES as a function setting signal, and stores the fetched data in a built-in register. Based on the function setting data set in the gate driver circuit 32, various functions for driving in the gate driver circuit 32 are set.
[Selection] Figure 1

Description

  The present invention relates to a driving device for driving a display panel, and more particularly to a gate driver that applies a scanning signal to each scanning line of the display panel.

  In an active matrix liquid crystal display device, a plurality of scanning lines and signal lines are arranged orthogonally on a liquid crystal display panel, and display pixels are formed in the vicinity of each intersection. Each display pixel has a liquid crystal capacitance in which liquid crystal is filled between a pixel electrode connected to a signal line and a scanning line via a TFT (Thin Film Transistor) and a common electrode.

  In such a liquid crystal display device, when a scanning signal (gate pulse) is sequentially applied to each scanning line by a gate driver (scanning driver) to be in a selected state (high potential state), the TFT of the corresponding display pixel is turned on. Become. Then, the display signal voltage applied to each signal line by the source driver (signal driver) is applied to the pixel electrode via the TFT, whereby the display signal voltage and the common voltage VCOM applied to the common electrode are A desired voltage is displayed on the liquid crystal display panel by applying and charging the differential voltage to the corresponding liquid crystal capacitor and controlling the alignment state of the liquid crystal molecules.

By the way, some conventional source drivers are provided with a serial communication function so that various functions can be set and changed. That is, an input terminal for serial communication is provided in the source driver, and command data for setting / changing various functions of the source driver from the controller that performs display control of the display panel to the input terminal as a serial signal. Input is performed, and control according to the input command data is performed. Functions controlled by command data include, for example, brightness voltage and contrast adjustment, clock signal polarity setting, backlight control, standby setting, left / right inversion setting, gradation voltage amplifier drive capability selection, and partial drive For example, there is a selection of a partial block (see, for example, Patent Document 1).
JP 2004-205634 A

  However, conventionally, the gate driver is not provided with such a serial communication function, and each function of the gate driver is fixed to a preset value. For this reason, it is necessary to prepare a gate driver set to an appropriate function according to the application, and there is a problem that the versatility is poor.

  In addition, the driver having the serial communication function as described above has a problem that the number of input terminals of the driver increases because a dedicated input terminal for serial communication is provided.

  In view of the above circumstances, an object of the present invention is to enable setting and changing of functions from the outside without increasing the number of input terminals in a driver for driving a display panel, particularly a gate driver.

  According to a first aspect of the present invention for solving the above problem, each display pixel of a display panel comprising a plurality of display pixels arranged in a matrix in the vicinity of the intersections of the plurality of scanning lines and the plurality of signal lines. In the driving device for applying a display control signal to the display device, a means for applying the display control signal to the display pixels according to a plurality of predetermined control signals, a normal drive state, and a standby state in which the application of the scanning signal is stopped At least one of the plurality of control signals used as a function setting signal in a standby release period for switching from the standby state to the normal driving state. Setting means for setting the state of the function.

  According to a second aspect of the present invention, in the drive device according to the first aspect, one vertical scanning period immediately after the release of the standby state is defined as the standby cancellation period.

  According to a third aspect of the present invention, in the driving device according to the first aspect, the driving device includes means for applying a scanning signal to each scanning line of the display panel.

  According to a fourth aspect of the present invention, in the driving apparatus according to the first aspect, the function setting signal includes at least a scanning clock signal, and the setting means includes the scanning clock signal in the function setting signal. It has a function of receiving any signal other than the above as a serial signal synchronized with the scanning clock signal.

  According to a fifth aspect of the present invention, in the driving apparatus according to the fourth aspect, the setting unit includes a storage unit that stores a value received as the serial signal.

  According to a sixth aspect of the present invention, there is provided a driving device that displays desired image information on a display panel including a plurality of display pixels arranged in a matrix in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines. Scanning-side drive means having means for applying a scanning signal to each scanning line based on the scanning-side control signal, and applying a display signal voltage based on display data to each signal line based on a plurality of signal-side control signals Signal-side driving means, and the scanning-side driving means switches between a normal driving state and a standby state in which application of the scanning signal is stopped according to a predetermined standby state switching instruction signal, and the standby In the standby release period for switching from the state to the normal driving state, some of the plurality of scanning side control signals are used as function setting signals. And a setting unit that sets a state of at least one function of the scanning side driving unit. The signal side driving unit includes a plurality of control signals, the scanning side driving unit, and the signal side. A function setting signal for setting a function in the driving unit is supplied, and the scanning side control signal for controlling the scanning side driving device and the standby state switching instruction signal are output to the scanning side driving unit based on the control signal. Control signal control means for outputting, to the scanning side driving device, a signal that becomes a part of the function setting signals of the plurality of scanning side control signals based on the function setting signal during the standby release period; It is characterized by having.

  According to a seventh aspect of the present invention, in the driving device according to the sixth aspect, the control signal control means in the signal side driving means includes a function setting signal storage means for storing a value of the function setting signal, and the standby release. Means for outputting a signal to be the function setting signal in the plurality of scanning side control signals to the scanning side driving means based on a value stored in the function setting signal storage means during the period It is characterized by that.

  According to an eighth aspect of the present invention, in the drive device according to the seventh aspect, the function setting signal includes at least a scanning clock signal, and any one of the function setting signals other than the scanning clock signal. It has means for outputting a signal as a serial signal synchronized with the scanning clock signal.

  According to a ninth aspect of the present invention, in the drive device according to the sixth aspect, in the scanning side driving means, one vertical scanning period immediately after the standby state is canceled is set as the standby cancellation period.

  According to a tenth aspect of the present invention, in the driving device according to the sixth aspect, in the scanning side driving unit, the function setting signal includes at least a scanning clock signal, and the setting unit includes the function setting signal. And a function of receiving any signal other than the scanning clock signal as a serial signal synchronized with the scanning clock signal.

  According to an eleventh aspect of the present invention, in the driving apparatus according to the tenth aspect, the setting unit includes a storage unit that stores a value received as the serial signal.

  According to the present invention, in the scanning side drive circuit, a part of the control signal input during the standby release period is used as a function setting signal, and the function value in the scanning side drive circuit is based on the signal. Is set / changed. Therefore, the function can be set and changed from the outside without providing a function setting input terminal separately, and versatility is improved.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[Liquid Crystal Display]
FIG. 1 is a configuration diagram of a liquid crystal display device 1 according to the present embodiment. As shown in the figure, the liquid crystal display device 1 includes a liquid crystal display panel 10, a source driver module 20 (signal side driving means) and a gate driver module 30 (scanning side) that form a two-chip configuration that is a drive circuit for the liquid crystal display panel 10. Drive means).

  The liquid crystal display panel 10 is provided with a plurality of scanning lines Lg connected to the gate driver circuit 32 in the row direction and a plurality of signal lines Ls in the column direction so as to be orthogonal to the scanning lines Lg. Is arranged. Display pixels are two-dimensionally arranged in the vicinity of each intersection of the scanning line Lg and the signal line Ls.

  FIG. 2 shows an equivalent circuit of the display pixel. According to the figure, the display pixel is disposed at a position facing the pixel electrode, the TFT (thin film transistor) 11 which is an active element, the pixel electrode 12 connected to the scanning line Lg and the signal line Ls via the TFT 11. , A common electrode 13 to which a common voltage VCOM is applied, a pixel capacitor (liquid crystal capacitor) 14 in which liquid crystal is filled between the pixel electrode 12 and the common electrode 13, and a pixel capacitor 14 are provided in parallel. 14 includes an auxiliary capacitor 15 that holds a display signal voltage applied to 14, and a common line Lc that is connected to the auxiliary capacitor 15 and to which a common voltage VCOM is applied.

  When a scanning signal (gate pulse) is sequentially applied to each scanning line Lg by the gate driver module 30 to be in a selected state (high potential state), the TFT 11 of each corresponding display pixel is turned on. Then, the display signal voltage applied (supplied) from the source driver circuit 22 to each signal line Ls is applied to each pixel electrode 12 through the TFT 11, whereby the display signal voltage and the common voltage VCOM applied to the common electrode. The pixel capacitor 14 is charged with the difference voltage between and the liquid crystal molecules in each display pixel is controlled in accordance with the difference voltage. As a result, a desired image is displayed on the liquid crystal display panel 10.

  In FIG. 1, the source driver module 20 includes a source driver circuit 22 (signal side drive circuit), a logic unit 24 (control circuit), and an analog circuit 26. The gate driver module 30 includes a gate driver circuit 32 (scanning side drive circuit) and an analog circuit 34. Here, the analog circuit 26 and the analog circuit 34 are circuits that generate a plurality of voltages used for the operation of the source driver circuit 22 and the gate driver circuit 32. For example, the analog circuit 26 corresponds to the number of bits of display data. The analog circuit 34 includes a charge pump circuit, for example, and generates a voltage necessary for generating a scanning signal by the gate driver circuit 32. Details will be described later.

  The signal line Ls of the liquid crystal display panel 10 is connected to the source driver circuit 22. Based on the source driver control signal input from the logic unit 24, the source driver circuit 22 selects, for example, a gradation voltage corresponding to display data from the gradation voltages input from the analog circuit 26, and displays the display signal. A voltage is applied to each signal line Ls.

  In the logic unit 24, display data of each color of R (red), G (green), and B (blue) extracted from the video signal from the outside of the source driver module 20, the horizontal synchronization signal, the vertical synchronization signal, and the composite synchronization are displayed. A synchronization signal including signals and various control signals are input, and function setting data (function setting signal) is input as a serial signal.

  The function setting data includes data for setting functions in the gate driver module 30 in addition to the setting data of various functions for the source driver described above. For example, the function setting data includes the output of the charge pump circuit included in the analog circuit 34. This includes setting the voltage, setting the frequency of the driving pulse CP, and the like.

  The logic unit 24 generates a source driver control signal (signal side control signal) based on the synchronization signal and each control signal and outputs it to the source driver circuit 22 and also generates a gate driver control signal (scanning side control signal). Output to the gate driver circuit 32 of the gate driver module 30, and the source driver circuit 22 selects a gradation voltage corresponding to the display data based on the source driver control signal, and applies it to each display pixel of the liquid crystal display panel 10 at a predetermined timing. A display signal voltage is applied, and an image based on the display data is displayed on the liquid crystal display panel 10. Further, the polarity inversion signal FRP is generated based on the input synchronization signal and output to the analog circuit 26. Further, a charge pump drive pulse CP for driving a charge pump circuit (not shown) included in the analog circuit 34 is generated and output to the analog circuit 34.

  Here, the gate driver control signal includes a standby signal STBYB, a gate output off signal GRES, a gate start signal GRST, and a gate clock signal GPCK. The standby signal STBYB is a signal (standby state switching instruction signal) that controls switching of the normal driving state / standby state of the liquid crystal display device 1. The gate output off signal GRES is a signal for controlling the scanning signal to the “L” level (no gate pulse). The gate start signal GRST is a pulse signal that defines one vertical scanning period. The gate clock signal GPCK is a clock signal for operating the gate driver circuit 32.

  The analog circuit 26 generates a voltage necessary for each part of the source driver module 20. For example, the reference voltage input from the analog circuit 34 is divided by resistors to generate a drive power supply voltage for the source driver circuit 22. In addition, a gradation voltage corresponding to the number of gradations of the liquid crystal display panel 10 is generated and output to the source driver circuit 22.

  Further, the analog circuit 26 generates a VCOM reference signal for generating a common voltage VCOM such as a rectangular wave whose polarity is inverted based on the polarity inversion signal FRP input from the logic unit 24. The VOCM reference signal generated by the analog circuit 26 is output to a drive amplifier (not shown). The drive amplifier generates a common voltage VCOM to be applied to the common line Lc and the common electrode 13 of the liquid crystal display panel 10 based on the input VCOM reference signal.

  A scanning line Lg of the liquid crystal display panel 10 is connected to the gate driver circuit 32. The gate driver circuit 32 sequentially applies the scanning signal to each scanning line Lg according to the gate driver control signal input from the logic unit 24 to make the selected state.

  The analog circuit 34 includes a charge pump circuit and a regulator circuit, and generates a necessary voltage in each part of the gate driver module 30. For example, the drive power supply voltage of the gate driver circuit 32 is generated. A reference voltage for driving the source driver circuit 22 is generated and output to the analog circuit 26.

  By the way, in the liquid crystal display device, when the device on which the liquid crystal display device is mounted enters a standby state, the liquid crystal display panel is set to a non-display state and only the necessary minimum part is operated to reduce power consumption. Some have a function to set the standby state. It is assumed that the liquid crystal display device 1 in this embodiment has a function of setting such a standby state. In this case, in the standby state, the output of the source driver circuit 22 is set to the high impedance state, and the vertical scanning (output of the gate pulse) by the gate driver circuit 32 is stopped. The vertical scanning of the gate driver circuit 32 is controlled by a standby signal.

  Further, when shifting from the standby state to the normal driving state, the standby state cannot be immediately shifted to the normal driving state, but a standby cancellation period including at least one vertical scanning period, for example, two vertical scanning periods has passed. Later, migrate. This is because it takes a certain amount of time for the voltages generated by the analog circuits 26 and 34 to reach a predetermined value. Therefore, in the present embodiment, a predetermined period of the standby cancellation period, for example, one vertical scanning period immediately after cancellation of the standby state is set as a function setting period for setting function setting data for driving in the gate driver circuit 32.

This will be specifically described.
FIG. 3 is a diagram illustrating the main configuration of the source driver module 20 and the gate driver module 30 according to the setting of the function setting data in the gate driver circuit 32. According to the figure, as a component related to function setting in the gate driver circuit 32, the logic unit 24 has a register 25 (function setting signal storage means), and the gate driver circuit 32 has a register 33 (function setting value storage means). Have

  The register 25 stores function setting data input from the outside of the source driver module 20.

  The logic unit 24 outputs a plurality of control signals including a gate output off signal GRES, a standby signal STBYB, a gate start signal GRST, and a gate clock signal GPCK to the gate driver circuit 32 as gate driver control signals. In the function setting period, the function setting data relating to the function setting of the gate driver module 30 stored in the register 25 is output as the gate output off signal GRES.

  A plurality of gate driver control signals including a gate output off signal GRES, a standby signal STBYB, a gate start signal GRST, and a gate clock signal GPCK output from the logic unit 24 are input to the gate driver circuit 32. In the normal driving state, the gate driver circuit 32 applies a scanning signal (gate pulse) to each scanning line Lg of the liquid crystal display panel 10 in accordance with these input signals. In the function setting period, the input gate output off signal GRES is used as a setting signal, and data input as a serial signal by this signal is stored in the register 33 as function setting data (bit0, 1,..., N). Remember.

  FIG. 4 is a diagram showing signal waveforms between the logic unit 24 and the gate driver circuit 32. In the figure, in order from the top, the standby signal STBYB, the gate start signal (scanning start signal) GRST, and the gate clock signal (scanning). The respective signal waveforms of the clock signal) GPCK and the gate output off signal (scan output off signal) GRES are shown.

  According to the figure, first, as an initial state, it is assumed that the standby signal STBYB is at "L" level and is set to the standby state. The gate start signal GRST, the gate clock signal GPCK, and the gate output off signal GRES are all at the “L” level.

  At time t1, the standby signal STBYB changes from the “L” level to the “H” level, the standby state is released, and the standby release period is entered. In the standby release period, one vertical scanning period, which is a period from time t2 when the first pulse of the gate start signal GRST falls to time t3 when the next pulse falls, is set as a function setting period.

  That is, in the function setting period, the logic unit 24 reads the function setting data stored in the register 25, and as the gate output off signal GRES, for example, one bit at a time starting from the least significant bit in synchronization with the gate clock signal. A serial signal is output to the driver circuit 32. On the other hand, the gate driver circuit 32 regards the gate output off signal GRES input from the logic unit 24 as a function setting signal during this function setting period, and uses the gate output off signal GRES as a serial signal synchronized with the gate clock signal GPCK. Received, fetched, and stored in the register 33 as bit data bits 0, 1,..., N in the order of fetching.

  After that, when the standby cancellation period ends, the normal driving period starts, the output of the scanning signal (gate pulse) is started, and the vertical scanning is started.

  Thus, in the function setting period during the standby release period, the function setting data stored in the register 25 from the logic unit 24 of the source driver module 20 is sent to the gate driver circuit 32 of the gate driver module 30 as the gate output off signal GRES. Is output and stored in the register 33. Various functions for driving the liquid crystal display panel 10 in the gate driver circuit 32 are set based on the function setting data stored in the register 33.

  As an example of function setting based on the function setting data set in the gate driver circuit 32, a case where the present invention is applied to a charge pump circuit included in the analog circuit 34 will be described.

  FIG. 5 is a diagram illustrating a circuit configuration of the charge pump type power supply circuit 35 included in the analog circuit 34. According to the figure, the charge pump type power supply circuit 35 is a power supply circuit that boosts the input voltage VCC by a predetermined factor and outputs the output voltage VDD, and includes a regulator 351, a charge pump circuit 352, resistors R1-3, The switches SW1 and SW2 and the error amplifier 353 are provided.

  The regulator 351 is configured by, for example, a p-MOSFET or the like, and controls and outputs the value of the voltage Vc according to the input voltage VCC and the control signal input from the error amplifier 353. Specifically, when the control signal is a positive voltage, the value of the voltage Vc is decreased with respect to the input voltage VCC in accordance with the voltage value of the control signal, and when the control signal is a negative voltage, the control signal is output. The voltage Vc is increased with respect to the input voltage VCC according to the voltage value (absolute value) of the signal and output. Thus, when the input voltage VDD increases, the control signal becomes a positive voltage, and when the input voltage VIN decreases, the control signal becomes a negative voltage, and the value of the voltage Vc controlled according to the control signal is a constant value. It is controlled in the direction approaching.

  The charge pump circuit 352 has at least one capacitor and switch, and alternately opens and closes these switches according to the charge pump drive pulse CP input from the logic unit 24, and adds the voltage charged in the capacitor. The voltage Vc input from the regulator 351 is boosted by a predetermined factor and output.

  The output voltage VDD of the charge pump circuit 352 is divided by the resistors R1 to R3 connected in series, and is input to the positive terminal (+) of the error amplifier 353 as the comparison voltage Va via the switches SW1 and SW2.

  The switch SW1 is connected between the connection point of the resistors R1 and R2 and the positive terminal (+) of the error amplifier 353. The switch SW2 is connected between the connection point of the resistors R2 and R3 and the positive terminal (+) of the error amplifier 353. One of the switches SW1 and SW2 is turned on and the other is turned off in accordance with a predetermined switching signal.

  Here, assuming that the resistance values of the resistors R1 to R3 are all equal to “R”, the comparison voltage Va input to the positive terminal (+) of the error amplifier 353 is as follows. That is, when the switch SW1 is on and the switch SW2 is off, the comparison voltage Va is Va = VDD × 2/3. When the switch SW1 is off and the switch SW2 is on, the comparison voltage Va is Va = VDD × 1/3.

  A comparison voltage Va obtained by dividing the output voltage VDD by the resistors R1 to R3 is input to the positive terminal (+) of the error amplifier 353, and a predetermined comparison voltage Vb is input to the negative terminal (−). Then, the error amplifier 353 outputs a voltage difference ΔV between the comparison voltage Va input to the positive terminal (+) and the reference voltage Vb input to the negative terminal (−) to the regulator 351 as a control signal.

  In the charge pump type power supply circuit 35 configured as described above, of the bit data stored in the register 33, for example, bit data bits 0 and 1 are used for function setting.

  Specifically, the output voltage VDD is selected according to the value of the bit data bit0. FIG. 6A shows an example of output voltage selection based on the value of bit0. According to FIG. 5A, if the value of the bit data bit0 is “0”, the output voltage VDD is set to a predetermined voltage VDD0. If the value of the bit data bit0 is “1”, the output voltage VDD is set to a predetermined voltage VDD1.

  Specifically, the setting of the output voltage VDD is realized by switching the switches SW1 and SW2 on / off. That is, if the bit data bit1 is “0”, the switch SW1 is turned off and the switch SW2 is turned on. Then, the comparison voltage Va input to the positive terminal (+) of the error amplifier 353 is Va = VDD × 2/3. If the bit data bit is “1”, the switch SW1 is turned on and the switch SW2 is turned off. Then, the comparison voltage Va input to the positive terminal (+) of the error amplifier 353 is Va = VDD × 1/3. In this way, by switching the switches SW1 and SW2 to make the comparison voltage Va different, two different types of output voltages VDD are set.

  Also, the frequency of the charge pump drive pulse CP is selected according to the value of the bit data bit1 among the function setting data stored in the register 33. FIG. 6B shows an example of selection of the frequency of the charge pump drive pulse CP according to the value of the bit data bit1. According to FIG. 5B, if the value of the bit data bit1 is “0”, the frequency of the charge pump drive pulse CP is set to a predetermined normal frequency. Further, if the value of the bit data bit1 is “1”, the frequency of the charge pump drive pulse CP is ½ of the normal frequency.

[Action / Effect]
As described above, according to the present embodiment, the predetermined period in the standby release period during the transition of the liquid crystal display device 1 from the standby state to the normal activation state is the function setting period, and the gate driver circuit 32 is driven during this function setting period. Function setting data is set. That is, in the function setting period, the logic unit 24 outputs the function setting data for setting the function of the gate driver circuit 32 stored in the internal register 25 to the gate driver circuit 32 as the gate output off signal GRES. The gate driver circuit 32 regards the input gate output off signal GRES as a setting signal, fetches it in synchronization with the gate clock signal GPCK, and stores it in the internal register 33 as function setting data. Therefore, it is possible to set the function from the outside without newly providing an input terminal for setting the function in the gate driver circuit 32, and the versatility is improved.

The block diagram of the liquid crystal display device in this embodiment. Equivalent circuit of display pixel. The principal part block diagram of a source driver module and a gate driver module. The signal waveform diagram between a logic part and a gate driver circuit. The circuit block diagram of a charge pump power supply circuit. Function setting example of charge pump type power supply circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Liquid crystal display panel Ls Signal line Lg Scan line 20 Source driver module 22 Source driver circuit 24 Logic part 25 Register 26 Analog circuit 30 Gate driver module 32 Gate driver circuit 33 Register 34 Analog circuit 35 Charge pump type power supply circuit

Claims (11)

In a driving device for applying a display control signal to each display pixel of a display panel including a plurality of display pixels arranged in a matrix in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines,
Means for applying the display control signal to each display pixel according to a plurality of predetermined control signals;
Means for switching between a normal driving state and a standby state in which application of the scanning signal is stopped;
In a standby release period for switching from the standby state to the normal driving state, a state of at least one function of the driving device is set using a part of the plurality of control signals as a function setting signal. Setting means;
A drive device comprising:   2. The driving device according to claim 1, wherein one standby scanning period immediately after the standby state is canceled is set as the standby cancellation period.   2. The driving device according to claim 1, further comprising means for applying a scanning signal to each scanning line of the display panel.   The plurality of function setting signals include at least a clock signal, and the setting means receives any signal other than the clock signal in the function setting signal as a serial signal synchronized with the clock signal. The drive device according to claim 1, further comprising:   5. The driving apparatus according to claim 4, wherein the setting unit includes a storage unit that stores a value received as the serial signal. In a drive device that displays desired image information on a display panel including a plurality of display pixels arranged in a matrix in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines,
Scanning side drive means having means for applying a scanning signal to each scanning line based on a plurality of scanning side control signals, and a display signal voltage based on display data on each signal line based on a plurality of signal side control signals Signal side driving means for applying,
The scanning-side driving means is configured to switch between a normal driving state and a standby state in which application of the scanning signal is stopped in accordance with a predetermined standby state switching instruction signal, and standby release for switching from the standby state to the normal driving state. A setting unit that sets a state of at least one function of the scanning side driving unit using a part of the plurality of scanning side control signals as a function setting signal during the period;
The signal side driving means is supplied with a plurality of control signals and a function setting signal for setting functions in the scanning side driving means and the signal side driving means, and controls the scanning side driving device based on the control signals. The scanning side control signal and the standby state switching instruction signal to be output to the scanning side driving means, and during the standby release period, based on the function setting signal, a part of the plurality of scanning side control signals And a control signal control means for outputting a signal to be the function setting signal to the scanning side driving device.   The control signal control means in the signal side drive means includes a function setting signal storage means for storing the value of the function setting signal, and the function setting signal in the plurality of scanning side control signals during the standby release period. The driving device according to claim 6, further comprising: a unit that outputs a signal to be output to the scanning side driving unit based on a value stored in the function setting signal storage unit.   The function setting signal has at least a scanning clock signal, and has means for outputting any signal other than the scanning clock signal in the function setting signal as a serial signal synchronized with the scanning clock signal. The drive device according to claim 7.   7. The driving apparatus according to claim 6, wherein in the scanning side driving means, one vertical scanning period immediately after the standby state is canceled is set as the standby cancellation period.   In the scanning side driving means, the function setting signal includes at least a scanning clock signal, and the setting means outputs any signal other than the scanning clock signal in the function setting signal to the scanning clock. The drive device according to claim 6, further comprising a function of receiving as a serial signal synchronized with the signal.   11. The driving apparatus according to claim 10, wherein the setting unit includes a storage unit that stores a value received as the serial signal.

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