JP2007026284A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor capable of preventing reduction of processing performance of the whole system using a plurality of buses. <P>SOLUTION: A traffic monitoring unit 3 monitors a traffic state of each the bus, and changes over a transfer bus for data. When a traffic amount of a bus 1A is less than a value of a bus 1B when an initiator M_A1 accesses a target T_A1, the initiator M_A1 and the bus 1A are connected, the target T_A1 and the bus 1A are connected, and the initiator M_A1 is made to access the target T_A1 via the bus 1A. When the traffic amount of the bus 1A exceeds a threshold value and when a traffic amount of the bus 1B is not more than the threshold value, the initiator M_A1 and the bus 1B are connected, the target T_A1 and the bus 1B are connected, and the initiator M_A1 is made to access the target T_A1 via the bus 1B. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing device, and more particularly to a data processing device that performs data processing using a plurality of buses.

  In recent years, data processing apparatuses represented by image processing systems such as digital cameras have been required to achieve both high functionality and high-speed processing, and more and more demands have been made to realize apparatus costs at a lower cost. Yes. At present, the majority of cases where such requirements are solved by system LSI (Large Scale Integration).

  Conventionally, regarding a system LSI architecture for an image processing apparatus represented by a digital camera or the like, a plurality of initiators (image processing engine, CPU (Central Processing Unit), etc.) and targets (frame memory, etc.) accessed by these initiators In general, a plurality of initiators are connected to a data bus and share the bus usage right to exchange data with the target. In such a case, the priorities of bus use permission of a plurality of initiators are generally set in advance.

  FIG. 5 shows a conventional bus architecture structure. In this example, for one bus 101, three initiators M_A101, M_A102, M_A103 and one target T_A101 are provided.

  As described above, in a configuration in which a plurality of initiators M_A101, M_A102, M_A103, and a target T_A101 are connected to one bus 101, bus requests may be generated simultaneously from a plurality of initiators. Therefore, the arbiter 102 performs bus arbitration according to a preset priority order.

  That is, the initiator M_A 101, initiator M_A 102, and initiator M_A 103 send bus requests R_A 101, R_A 102, and R_A 103 to the arbiter 102 when using the bus 101.

  When bus requests are sent from a plurality of initiators, the arbiter 102 returns bus grants G_A101, G_A102, and G_A103 to the initiator with the highest priority according to a preset priority.

  When the initiators M_A101, M_A102, and M_A103 receive the bus grants G_A101, G_A102, and G_A103 from the arbiter 102, they can access the target T_A101 via the bus 101.

  6 to 8 show the configuration of the bus 101 in the architecture shown in FIG. 5, and FIG. 6 shows an address select unit directed to the target T_A101.

  In FIG. 6, A101_A (m), A102_A (m), and A103_A (m) are m-bit address lines output from the initiator M_A101, initiator M_A102, and initiator M_A103, respectively. G_A101, G_A102, and G_A103 are bus grants output from the arbiter 102. Each of the bus grants G_A101, G_A102, and G_A103 is permitted to use the buses of the respective initiators M_A101, M_A102, and M_A103 at the H level, and indicates the bus use prohibition at the L level.

  The address lines A101_A (m), A102_A (m), A103_A (m) and the bus grants G_A101, G_A102, G_A103 are ANDed by AND circuits 121a, 121b, 121c, respectively, and the AND circuits 121a, 121b, 121c are obtained. By taking the logical sum of the outputs by the OR circuit 122, the address line S_A (m) of the initiator permitted to use the bus is output to the target T_A101.

  FIG. 7 shows a data selection unit directed to the target T_A101. A101_WD (n), A102_WD (n), and A103_WD (n) are n-bit data lines output from the initiator M_A101, initiator M_A102, and initiator M_A103, respectively. The AND of the data lines A101_WD (n), A102_WD (n), A103_WD (n) and the bus grants G_A101, G_A102, G_A103 are taken by AND circuits 131a, 131b, 131c, respectively, and the outputs of the AND circuits 131a, 131b, 131c Is output by the OR circuit 132, and the data line S_WD (n) of the initiator permitted to use the bus is output to the target T_A101.

  FIG. 8 shows a memory control signal selector for the target T_A101. A101_XWR, A102_XWR, and A103_XWR are memory read / write control signal lines for the target T_A101 output from the initiator M_A101, initiator M_A102, and initiator M_A103, respectively. The signal level is H level for reading to the target T_A 101 and L for writing.

  NAND of the control signal lines A101_XWR, A102_XWR, A103_XWR and the bus grants G_A101, G_A102, G_A103 are obtained by the NAND circuits 141a, 141b, 141c, respectively, and the logical product of the outputs of the NAND circuits 141a, 141b, 141c is obtained. By taking the AND circuit 142, the memory read / write control signal line S_XWR of the target T_A101 is output.

  The operation of the above-described conventional bus architecture will be described with reference to FIG. FIG. 9 shows an operation of the architecture including the multiple initiators M_A101, M_A102, and M_A103 shown in FIG. Here, it is assumed that the initiator bus use priority is the highest for the initiator M_A101, the initiator M_A102 next, and the initiator M_A103 having the lowest priority.

  FIGS. 9A, 9F, and 9K show bus requests R_A101, R_A102, and R_A103 sent from the initiator M_A101, initiator M_A102, and initiator M_A103 to the arbiter 102, and indicate the request state at the H level. .

  FIGS. 9B, 9G, and 9L show bus grants G_A101, G_A102, and G_A103 returned from the arbiter 102 to the initiator M_A101, the initiator M_A102, and the initiator M_A103, and the bus use permission state at the H level. Indicates.

  FIG. 9C, FIG. 9H, and FIG. 9M show the addresses of the targets that the initiator M_A101, initiator M_A102, and initiator M_A103 access.

  FIG. 9D, FIG. 9I, and FIG. 9N show data that the initiator M_A 101, initiator M_A 102, and initiator M_A 103 access to the target.

  FIGS. 9E, 9J, and 9O show read / write control signals for targets accessed by the initiator M_A101, the initiator M_A102, and the initiator M_A103, and write at the L level and write at the H level. Lead.

  FIGS. 9 (P), 9 (Q), and 9 (R) show the selected address, data, and target read / write.

  For example, at time t1, as shown in FIGS. 9A, 9F, and 9K, the bus requests R_A101, R_A102, and R_A103 are simultaneously output from the initiator M_A101, the initiator M_A102, and the initiator M_A103. To do. When bus requests are generated at the same time, the arbiter 102 sends a bus grant to the initiator with the highest priority. In this case, since the priority of the initiator M_A101 is the highest, as shown in FIG. 9B, the arbiter 102 first sends the bus grant G_A101 to the initiator M_A101.

  The initiator M_A 101 that has received the bus grant G_A 101 accesses the target T_A 101 via the bus 101. At this time, as shown in FIGS. 9C, 9D, and 9E, the initiator M_A101 has the address line A101_A (m) as the address A101 and the data line A101_WD (n) as the data D101. The read / write control signal is write (L level). Based on this, as shown in FIGS. 9 (P), 9 (Q), and 9 (R), the use-permitted address line S_A (m) becomes the address A101, and the use-permitted data line S_WD becomes the data D101. And the target is set to light.

  Thus, while the bus 101 is being used by the initiator M_A 101, the access to the target T_A 101 by the initiator M_A 102 or the initiator M_A 103 is in a wait state.

  When the access of the initiator M_A 101 to the target T_A 101 is completed at time t2, as shown in FIG. 9G, the arbiter 102 sends the bus grant G_A 102 to the initiator M_A 102 having the next highest priority.

  The initiator M_A 102 that has received the bus grant G_A 102 accesses the target T_A 101 via the bus 101. At this time, as shown in FIGS. 9H, 9I, and 9J, the initiator M_A102 has the address line A102_A (m) as the address A102 and the data line A102_WD (n) as the data D102. The read / write control signal repeats reading and writing (repetition of L level and H level). Based on this, as shown in FIGS. 9 (P), 9 (Q), and 9 (R), the use-permitted address line S_A (m) becomes the address A102, and the use-permitted data line S_WD becomes the data D102. Thus, the target is set to repeat reading and writing.

  Thus, while the bus 101 is used by the initiator M_A102, the write access to the target T_A101 of the initiator M_A103 is in a wait state.

  When the access of the initiator M_A102 to the target T_A101 is completed at time t3, as shown in FIG. 9L, the arbiter 102 sends the bus grant G_A103 to the next highest priority initiator M_A103.

  The initiator M_A 103 that has received the bus grant G_A 103 accesses the target T_A 101 via the bus 101. At this time, as shown in FIGS. 9 (M), 9 (N), and 9 (O), the initiator M_A103 has the address line A103_A (m) as the address A103 and the data line A103_WD (n) as the data D103. Thus, the read / write control signal is read (H level). Based on this, as shown in FIGS. 9 (P), 9 (Q), and 9 (R), the use-permitted address line S_A (m) becomes the address A103, and the use-permitted data line S_WD becomes the data D103. And the target is set to lead.

  As an example to which this configuration is applied, for example, an entire sequence of a digital camera system will be described.

  The above-described access of the initiator M_A101 to the target T_A101 is data processing for transferring image data from an imaging module (not shown) for one frame to the target T_A101. The above-described access of the initiator M_A102 is a period in which image data for one frame in the target T_A101 is read in an arbitrary processing unit, this data is image-processed in the initiator M_A102, and written back to the target T_A101. The processing contents in the initiator M_A 102 are omitted. The above-described access of the initiator M_A 103 is a period in which data after image processing in the target T_A 101 is transferred to an external storage device (not shown) or the like.

  A series of system sequence from shooting to recording is completed by passing through the above-described period.

  The above conventional system is an architecture that is particularly suitable for high integration by a system LSI and realizes high cost performance. However, in the future, as more systems become more sophisticated, when more initiators and targets associated therewith are required, the real-time performance of the processing apparatus using the conventional method is remarkably high. There is concern about the decline.

  In order to solve such problems, for example, as shown in Patent Document 1, a system architecture using a plurality of buses is considered.

  FIG. 10 shows a configuration in which the above-described conventional system is made into two buses. In this example, two independent buses 201A and 201B are provided.

  An initiator M_A201, M_A202, M_A203 and a target T_A201 are provided for the bus 201A. The arbiter 202A arbitrates the bus 201A according to a preset priority order.

  An initiator M_B201, M_B202, M_B203, and a target T_B201 are provided for the bus 201B. The arbiter 202B arbitrates the bus 201B according to a preset priority order.

  In this way, with the independent bus configuration, the initiators M_A201, M_A202, and M_A203 connected to the bus 201A and the initiators M_B201, M_B202, and M_B203 connected to the bus 201B can be executed in parallel, and processing performance is improved. Improvement can be achieved.

  However, in general, the processing time required or inevitably possible for each initiator is unique to the initiator. Furthermore, the processing performance of the entire system is the total processing time of each initiator group connected to the bus. Therefore, in a system using multiple buses, the number of initiators connected to each bus can be adjusted as appropriate by taking into account the shared target, processing contents, and priority, thereby maintaining the processing performance required for the entire system. Must.

  However, with the increase in the number of buses, the number of initiators, and the number of targets, such architectural design becomes more difficult.

In order to solve such design problems, further proposals have been made. As a typical example, Patent Document 2 realizes a bus system that has a plurality of buses and prepares a plurality of access paths between a master device and a target device, thereby reducing an access loss time due to bus arbitration. Japanese Patent Application Laid-Open No. 2004-228561 searches for a system bus in which an arbiter is not used when a certain initiator tries to access a target, and realizes access between the initiator and the target via an unused bus.
JP 2004-213142 A JP-A-7-210501

  Even in an architecture configuration using a plurality of buses typified by Patent Document 2, there are many cases where any bus is in use when the use state of the bus is examined. In such a case, in such a system, as soon as an unused bus is found, the initiator and target are connected using the bus.

  However, when judging from the amount of data traffic on the bus, it is often not always the optimum bus selection. That is, in an architecture composed of a plurality of buses, it is ideal to use a bus with as little traffic as possible so that traffic is not concentrated on one bus. However, in the method of Patent Document 2, an unused bus is found and an initiator and a target are connected, and a bus in which an unused period is generated is not always a bus with a small amount of traffic.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a data processing apparatus capable of preventing a decrease in processing performance of the entire system using a plurality of buses.

  In order to solve the above-described problem, a data processing apparatus according to claim 1 is a bus that monitors the frequency of access by a plurality of initiators for each of a plurality of buses to which a plurality of initiators and a target are connected. One bus that mediates data transfer between a certain initiator and a target that transfers data between the initiators from a plurality of buses according to the monitoring result of the traffic monitoring unit and the bus traffic monitoring unit And a bus setting means for selecting and setting, and a connection means for connecting an initiator and a target for transferring data to the set bus.

  According to a second aspect of the present invention, the bus traffic monitoring means includes means for integrating the valid period of the bus permission right signal for the initiator, and means for comparing the integration result with a predetermined threshold value.

  According to a third aspect of the present invention, the bus traffic monitoring means includes means for measuring an interrupt event output from the initiator, and means for comparing the measured value with a predetermined threshold value.

  According to the present invention, a plurality of initiators and targets are connected to a plurality of buses, the bus traffic state is monitored, and the data transfer bus between the initiator and the target is switched according to the traffic monitoring result. ing. That is, a bus with less traffic is selected from a plurality of buses. This prevents traffic from concentrating on one bus in an architecture composed of a plurality of buses. Furthermore, a connection means such as a selector is provided between the initiator and target and the bus, and the bus is switched by switching the connection means while monitoring the traffic volume, so that the traffic volume can be reflected reliably and the architecture design. Is not complicated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<First Embodiment>
FIG. 1 shows a first embodiment of the present invention. In this example, eight initiators M_A1 to M_A4 and M_B1 to M_B4 and two targets T_A1 and T_B1 are provided. Two buses 1A and 1B are provided.

  The selector SEL1 is a selector for selectively connecting the initiator M_A1 and the bus 1A or 1B. The selector SEL1 is switched by a select signal S1. When the select signal S1 is at L level, the initiator M_A1 and the bus 1A are connected, and when the select signal S1 is at H level, the initiator M_A1 and the bus 1B are connected.

  The selector SEL2 is a selector for selectively connecting the initiator M_B2 and the bus 1B or 1A. The selector SEL2 is switched by a select signal S2. When the select signal S2 is at L level, the initiator M_B2 is connected to the bus 1B, and when the select signal S2 is at H level, the initiator M_B2 and the bus 1A are connected.

  The selector SEL3 is a selector for selectively connecting the target T_A1 and the bus 1A or 1B. The selector SEL3 is switched by a select signal S1. When the select signal S1 is at L level, the target T_A1 and the bus 1A are connected. When the select signal S1 is at H level, the target T_A1 and the bus 1B are connected.

  The selector SEL4 is a selector for selectively connecting the target T_B1 and the bus 1B or 1A. The selector SEL4 is switched by a select signal S2. When the select signal S2 is at L level, the target T_B1 and the bus 1B are connected, and when the select signal S2 is at H level, the target T_B1 and the bus 1A are connected.

  R_A1, R_A2, R_A3, and R_A4 output from the initiator M_A1, initiator M_A2, initiator M_A3, and initiator M_A4, respectively, are bus requests input to an arbiter (not shown). The signal level is H and a bus request.

  G_A1, G_A2, G_A3, and G_A4 respectively input to the initiator M_A1, initiator M_A2, initiator M_A3, and initiator M_A4 are bus grants for the bus 1A output from an arbiter (not shown). The signal level is H, and the bus use is permitted.

  R_B1, R_B2, R_B3, and R_B4 output from the initiator M_B1, initiator M_B2, initiator M_B3, and initiator M_B4 are requests to the bus 1B that are input to an arbiter (not shown). The signal level is H and a bus request.

  G_B1, G_B2, G_B3, and G_B4 respectively input to the initiator M_B1, the initiator M_B2, the initiator M_B3, and the initiator M_B4 are grants for the bus 1B output from an arbiter (not shown). The signal level is H, and the bus use is permitted.

  When a bus request is sent from a plurality of initiators, an arbiter (not shown) returns a bus grant to the initiator with the highest priority according to a preset priority. Since the arbitration of the bus by the arbiter is the same as the conventional one, the description thereof is omitted.

  The traffic monitoring unit 3 monitors the bus grant status of the initiator on the bus 1A and the bus 1B to monitor the traffic state of the bus. Then, a select signal S1 and a select signal S2 are generated according to the result of the traffic state, the select signal S1 is sent to the selector SEL1 and the selector SEL3, and the select signal S2 is sent to the selector SEL2 and the selector SEL4.

  Thus, in the first embodiment of the present invention, two buses 1A and 1B are provided. Initiators M_A1, M_A2, M_A3, and M_A4 are provided for the bus 1A. The initiator M_A1 can be connected to the bus 1A or the bus 1B by the selector SEL1.

  Initiators M_B1, M_B2, M_B3, and M_B4 are provided for the bus 1B. The initiator M_B2 can be connected to the bus 1B or the bus 1A by the selector SEL2.

  The target T_A1 can be connected to the bus 1A or the bus 1B by the selector SEL3. The target T_B1 can be connected to the bus 1B or the bus 1A by the selector SEL4.

  With such a configuration, it is possible to dynamically change the path of more efficient bus access by appropriately monitoring the bus traffic status of the bus 1A and the bus 1B.

  First, an operation when the initiator M_A1 accesses the target T_A1 will be described.

  The traffic monitoring unit 3 monitors the bus usage status of initiators other than the initiator M_A1, and monitors the traffic status of the bus 1A and the bus 1B. Specifically, the bus grant on the bus 1A other than the bus grant G_A1 is monitored for a period when the bus grant on the bus 1B is at the H level, and the bus grant on the bus 1B is monitored for the period of the H level. It is determined which of the buses 1B is congested, and the level of the select signal S1 is determined accordingly.

  When the traffic amount of the bus 1A is lower than the value of the bus 1B, the select signal S1 from the traffic monitoring unit 3 becomes L level (S1 = L).

  When the select signal S1 is at the L level, the selector SEL1 connects the initiator M_A1 and the bus 1A. When the select signal S1 is at the L level, the selector SEL3 connects the target T_A1 and the bus 1A. Therefore, the initiator M_A1 accesses the target T_A1 via the bus 1A as indicated by paths W1, W2, W8, and W15.

  On the other hand, when the traffic amount of the bus 1A exceeds the threshold value and the traffic amount of the bus 1B is equal to or less than the threshold value, the select signal S1 from the traffic monitoring unit 3 becomes H level (S1 = H).

  When the select signal S1 becomes H level, the selector SEL1 connects the initiator M_A1 and the bus 1B. Further, the target T_A1 and the bus 1B are connected by the selector SEL3. Therefore, the initiator M_A1 accesses the target T_A1 via the bus 1B as indicated by paths W1, W3, W7, and W15.

  Next, an operation when the initiator M_B2 accesses the target T_B1 will be described.

  The traffic monitoring unit 3 monitors the bus usage status of initiators other than the initiator M_B2, and monitors the traffic status of the bus 1A and the bus 1B. Specifically, the bus grant on the bus 1B other than the bus grant G_B2 is monitored for a period in which the bus grant on the bus 1A is at an H level, and the bus grant on the bus 1A is monitored for an H level. The level of the select signal S2 is determined by determining whether it is congested.

  When the traffic amount of the bus 1B is lower than the traffic amount of the bus 1A, the select signal S2 becomes L level (S2 = L). When the select signal S2 is at L level, the selector SEL2 connects the initiator M_B2 and the bus 1B. Further, when the select signal S2 is at the L level, the target T_B1 and the bus 1B are connected by the selector SEL4. Therefore, the initiator M_B2 accesses the target T_B1 via the bus 1B as indicated by paths W17, W12, W9, and W16.

  On the other hand, when the traffic amount of the bus 1B exceeds the threshold value and the traffic amount of the bus 1A is equal to or less than the threshold value, the select signal S2 becomes H level (S2 = H). When the select signal S2 is at H level, the selector SEL2 connects the initiator M_B2 and the bus 1A. Further, the target T_B1 and the bus 1A are connected by the selector SEL4. Therefore, the initiator M_B2 accesses the target T_B1 via the bus 1A as indicated by paths W17, W11, W10, and W16.

  As described above, in the first embodiment of the present invention, the bus traffic status of the bus 1A and the bus 1B is appropriately monitored in a circuit configuration in which a desired initiator can access the target via a plurality of buses. Thus, a more efficient bus access route can be dynamically changed.

  Next, the configuration of the traffic monitoring unit 3 will be described. FIG. 2 shows a specific example of the traffic monitoring unit 3. In this example, the generation circuit of the select signal S1 will be described, but the generation circuit of the select signal S2 can be configured in the same manner.

  In FIG. 2, the rising edge signals of the bus grants G_A 2, G_A 3, G_A 4 from the initiators M_A 2, M_A 3, M_A 4 are sent to the OR circuit 11. The output signal of the OR circuit 11 is supplied to the enable terminal of the counter 12.

  In this way, the logical sum of the rising edge signals of the bus grants G_A2, G_A3, and G_A4 is supplied to the enable terminal of the counter 12, and when any of the bus grants G_A2, G_A3, and G_A4 becomes the H level, the counter 12 is in the count enable state. become. From the count value of the counter 12, a value obtained by integrating the bus grant of the bus 1A during the valid period, that is, a value corresponding to the event count value of the bus 1A is obtained.

  A value corresponding to the number of events of the bus 1 </ b> A from the counter 12 is compared with a preset threshold A from the threshold setting circuit 14 by the comparator 13. If the number of event occurrences obtained by the counter 12 exceeds the threshold A, it is determined that the traffic on the bus 1A is significantly increased or increased, and the output level of the comparator 13 becomes H level. The output of the comparator 13 is sent to the comparator 31.

  The rising edge signals of the bus grants G_B1, G_B2, G_B3, and G_B4 from the initiators M_B1, M_B2, M_B3, and M_B4 are sent to the OR circuit 21. The output signal of the OR circuit 21 is supplied to the enable terminal of the counter 22.

  In this manner, the logical sum of the rising edge signals of the bus grants G_B1, G_B2, G_B3, and G_B4 is supplied to the enable terminal of the counter 22, and when any of the bus grants G_B1, G_B2, G_B3, and G_B4 becomes H level, the counter 22 Enters the count enable state. From the count value of the counter 22, a value obtained by integrating the bus grant of the bus 1A during the valid period, that is, a value corresponding to the number of events of the bus 1B is obtained.

  A value corresponding to the number of events of the bus 1B from the counter 22 is compared with a preset threshold B from the threshold setting circuit 24 by the comparator 23. If the number of event occurrences determined by the counter 22 exceeds the threshold value B, it is determined that the traffic on the bus 1B is significantly increased or increased, and the output level of the comparator 23 becomes H level. The output of the comparator 13 is sent to the comparator 31.

  The comparator 31 performs an operation from the outputs of the comparator 13 and the comparator 23 based on the following condition (1) to generate the select signal S1.

Condition (1): The output signal of the comparator 13 is H level, and the output signal of the comparator 23 is L level.

  When the condition (1) is satisfied, the output signal of the comparator 13 is at the H level, so the number of event occurrences on the bus 1A exceeds the threshold value A, and it can be determined that the traffic on the bus 1A is significantly increased or increased. . Further, since the output signal of the comparator 23 is at the L level, it can be determined that the number of event occurrences on the bus 1B is smaller than the threshold value B and the traffic on the bus 1B is small.

  Therefore, when the condition (1) is satisfied, the select signal S1 becomes H level (S1 = H), the initiator M_A1 accesses the target T_A1 via the bus 1B, and waits for the bus 1A. Is avoided.

  In other cases, the select signal S1 is at the L level (S1 = L), and the initiator M_A1 accesses the target T_A1 via the bus 1A.

  The timer 32 is a reset signal generation timer for the counters 12 and 22. When a preset time (a period longer than a period in which a plurality of initiators perform bus access) elapses, a reset signal is output from the timer 32, and this reset signal is supplied to the reset terminals of the counters 12 and 22. 12 and 22 are reset. As a result, the select signal S1 is returned to the default state.

  FIG. 3 shows the operation of the first embodiment of the present invention. FIG. 3A shows the count value C_A1 of the counter 12 corresponding to the traffic volume of the bus 1A and the change C_B1 of the count value of the counter 22 corresponding to the traffic volume of the bus 1B. The counters 12 and 22 hold the value when the full count is reached and do not overflow.

  FIG. 3B shows a counter reset pulse output from the timer 32. FIG. 3C shows the select signal S 1 generated from the traffic monitoring unit 3.

  At time t00 to t01, the count value C_A1 is equal to or lower than the threshold level A and the count value C_B1 is equal to or lower than the threshold level B as shown in FIG. Therefore, as shown in FIG. 3C, the select signal S1 becomes L level, and the initiator M_A1 accesses the target T_A1 via the bus 1A.

  From time t01 to t02, the count value C_A1 exceeds the threshold level A and the count value C_B1 does not reach the threshold level B as shown in FIG. For this reason, the above-mentioned condition (1) is satisfied, and the select signal S1 becomes L level as shown in FIG. When the select signal S1 is at the L level, the initiator M_A1 accesses the target T_A1 via the bus 1B.

  Similarly, at times t10 to t11, the count value C_A1 exceeds the threshold level A, and the count value C_B1 does not reach the threshold level B. Therefore, the above condition (1) is satisfied, and the select signal S1 becomes L level as shown in FIG. 3C, and the initiator M_A1 accesses the target T_A1 via the bus 1B.

  At times t11 to t12, since the count value C_A1 and the count value C_B1 exceed the threshold A and the threshold B, respectively, the condition (1) is not satisfied, and the initiator M_A1 accesses the target T_A1 via the bus 1A.

  In such a case, as another idea, differentials (X and Y slopes in FIG. 3) of the count values C_A1 and C_B1 of the counter 12 or the counter 22 are separately acquired, and a bus corresponding to a counter with a small differential value is selected. You may do it.

  In this example, the traffic monitoring unit 3 for monitoring the traffic volume of the bus 1A and the bus 1B is configured by hardware as shown in FIG. 2, but such a function may be executed by software by the CPU. good. When the traffic amount is monitored by the CPU, the rising edge signals of the bus grants G_A2, G_A3, and G_A4 and the rising edge signals of the bus grants G_B1, G_B2, G_B3, and G_B4 may be handled as interrupt signals to the CPU. .

  In this embodiment, two buses are used, but the same effect can be expected with more buses. In this embodiment, the number of initiators is four connected to one bus, but the same effect can be expected with a configuration with more than this.

<Second Embodiment>
FIG. 4 shows a second embodiment of the present invention. In this embodiment, the traffic monitoring unit 3 weights the number of grants generated from each initiator, and calculates the bus traffic amount reflecting the processing content (processing time) of each initiator. That is, in this embodiment, the number of event occurrences from the initiator is preferentially reflected in the bus traffic amount in consideration of the processing time per bus request. Other parts are the same as those in the first embodiment described above, and a description thereof will be omitted.

  FIG. 4 shows the configuration of the traffic monitoring unit 3 according to the second embodiment of the present invention. In FIG. 4, the rising edge signals of the bus grants G_A2, G_A3, and G_A4 from the initiators M_A2, M_A3, and M_A4 are supplied to the enable terminals of the counters 51a, 51b, and 51c, respectively.

  The count values of the counters 51a, 51b, 51c are sent to the multipliers 52a, 52b, 52c, respectively. Weighting factors Coeff_A2, Coeff_A3, and Coeff_A4 corresponding to the processing time per bus request are set in the multipliers 52a, 52b, and 52c, respectively. Multipliers 52a, 52b, and 52c multiply the count values of the counters 51a, 51b, and 51c by weight coefficients Coeff_A2, Coeff_A3, and Coeff_A4, respectively. The multiplication results of the multipliers 52a, 52b, and 52c are added by the adder 53.

  The added value of the adder 53 is compared with a preset threshold A from the threshold setting circuit 55 by the comparator 54. If the addition value of the adder 53 exceeds the threshold A, it is determined that the traffic on the bus 1A is significantly increased or increased, and the H level is output to the comparator 71.

  The rising edge signals of the bus grants G_B1, G_B2, G_B3, and G_B4 from the initiators M_B1, M_B2, M_B3, and M_B4 are supplied to the enable terminals of the counters 61a, 61b, 61c, and 61d, respectively. As a result, the counters 61a, 61b, 61c, 61d are enabled, and the counters 61a, 61b, 61c, 61d are up-counted.

  The count values of the counters 61a, 61b, 61c, and 61d are sent to multipliers 62a, 62b, 62c, and 62d, respectively. Weighting factors Coeff_B1, Coeff_B2, Coeff_B3, and Coeff_B4 corresponding to the processing time per bus request are set in the multipliers 62a, 62b, 62c, and 62d, respectively. Multipliers 62a, 62b, 62c, and 62d multiply the count values of the counters 61a, 61b, 61c, and 61d by weight coefficients Coeff_B1, Coeff_B2, Coeff_B3, and Coeff_B4, and the multiplication results of the multipliers 62a, 62b, 62c, and 62d are obtained. It is added by the adder 63.

  The added value of the adder 63 is compared with a preset threshold B from the threshold setting circuit 65 by a comparator 64. If the addition value of the adder 63 exceeds the threshold value B, it is determined that the traffic on the bus 1B is significantly increased or increased, and the H level is output to the comparator 71.

  The comparator 71 performs an operation from the outputs of the comparator 54 and the comparator 64 based on the following condition (1a) to generate the select signal S1.

Condition (1a): The output signal of the comparator 54 is H level and the output signal of the comparator 64 is L level.

  When the condition (1a) is satisfied, the select signal S1 becomes H level (S1 = H), the initiator accesses the target via the bus 1B, and the waiting time of the bus 1A is avoided.

  In other cases, the select signal SEL1 is at the L level (S1 = L), and the target is accessed via the bus 1A.

  The timer 72 is a reset signal generation timer for the counters 51a to 51c and the counters 61a to 61d. When a preset time (a period longer than a period in which a plurality of initiators perform bus access) elapses, a reset signal is output from the timer 72.

  As described above, in the second embodiment of the present invention, the number of grants generated from each initiator is weighted, and the bus traffic amount reflecting the processing content of each initiator is calculated. For this reason, the amount of bus traffic can be reflected more accurately.

  The present invention is not limited to the above-described embodiments, and various modifications and applications can be made without departing from the gist of the present invention.

  The present invention can be widely used in an architecture in which a plurality of initiators and targets are connected via a bus.

It is a block diagram which shows the structure of 1st Embodiment of this invention. It is a block diagram used for description of the traffic monitoring unit in 1st Embodiment of this invention. It is a timing diagram used for description of 1st Embodiment of this invention. It is a block diagram used for description of 2nd Embodiment of this invention. It is a block diagram which shows the structure of an example of the conventional bus architecture. It is a block diagram used for description of the conventional bus architecture. It is a block diagram used for description of the conventional bus architecture. It is a block diagram used for description of the conventional bus architecture. It is a timing diagram used for description of the conventional bus architecture. It is a block diagram which shows the structure of the other example of the conventional bus architecture.

Explanation of symbols

1A, 1B: Bus
3: Traffic monitoring unit,
M_A1 to M_A4, M_B1 to M_B4: initiator,
SEL1 to SEL4: selector,
T_A1, T_B1: Target

Claims (3)

Bus traffic monitoring means for monitoring the frequency of access by the plurality of initiators for each of a plurality of buses to which a plurality of initiators and targets are connected;
In accordance with the monitoring result by the bus traffic monitoring means, select one bus that mediates data transfer between a certain initiator and a target that transfers data between the initiators from a plurality of buses. A bus setting means to set;
A data processing apparatus comprising: a connection unit that connects the initiator that transfers data to the set bus and the target.   2. The data processing according to claim 1, wherein the bus traffic monitoring means includes means for integrating a valid period of a bus permission right signal for the initiator, and means for comparing the integration result with a predetermined threshold value. apparatus. 2. The data processing apparatus according to claim 1, wherein the bus traffic monitoring means includes means for measuring an interrupt event output from the initiator, and means for comparing the measured value with a predetermined threshold value.

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