JP2007027402A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a package size can be miniaturized in a structure formed by stacking semiconductor chips each having electrodes on its surface and backside. <P>SOLUTION: In this semiconductor device 1, a die pad 2 and a die pad 12 are stuck to each other with an insulation adhesive. An SBD chip 3 is fixed on the die pad 2, and an MOSFET chip 14 is fixed on the die pad 12. Electrodes of the SBD chip 3 or the MOSFET chip 14 are electrically connected to leads 7, 9 and 10 via metallic fine wires 18, 19 and 21. This structure enables a package 5 to pull out leads 6-10 from desired directions, and the degree of freedom in the design of the lead can be increased. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a miniaturized semiconductor device in which a plurality of semiconductor chips are stacked and fixed in one package.

  In a conventional semiconductor device, a semiconductor chip having electrodes on the front and back sides, for example, an N-channel MOSFET (Metal Oxide Field Effect Transistor) chip and an SBD (Schottky Barrier Diode) chip are stacked and fixed in one package. There is a structure. (For example, refer to Patent Document 1).

  5A and 5B show the semiconductor device disclosed in Patent Document 1. FIG. FIG. 5A is a plan view of the semiconductor device. FIG. 5B is a cross-sectional view taken along the line II in FIG. 5A and viewed in the direction of the arrow.

  As shown in FIG. 5A, in the semiconductor device 71, a laminated structure is constituted by the first lead frames 72 and 73, the second lead frame 74, and the third lead frame 75 made of nickel or solder plated copper. ing. A dotted line 76 indicates the outer periphery of the package. Leads extending from the first to third lead frames 72 to 75 are led out from the package.

  As shown in FIG. 5B, the source electrode 78 on the surface electrode side of the MOSFET chip 77 is fixed to the first lead frame 72 by solder balls 79. On the other hand, the gate electrode 80 on the surface electrode side of the MOSFET chip 77 is fixed to the first lead frame 73 by a solder ball 81.

  On the back surface 74a side of the second lead frame 74, the drain electrode 82 on the back surface electrode side of the MOSFET chip 77 is fixed by a conductive adhesive (not shown). On the other hand, on the surface 74 b side of the second lead frame 74, the anode electrode 84 on the surface electrode side of the SBD chip 83 is fixed by a solder ball 85. With this structure, the drain electrode 82 of the MOSFET chip 77 and the anode electrode 84 of the SBD chip 83 are electrically connected via the second lead frame 74.

  A cathode electrode 86 on the back electrode side of the SBD chip 83 is fixed to the third lead frame 75 with a conductive adhesive (not shown). The semiconductor device 71 is resin-molded as indicated by a dotted line 76.

  Next, a conventional semiconductor device has a structure in which, for example, a semiconductor chip incorporating an N-channel MOSFET and SBD is mounted in a lead frame package (see, for example, Patent Document 2).

  6A and 6B show a semiconductor device disclosed in Patent Document 2. FIG. FIG. 6A is a plan view of the semiconductor device. FIG. 6B is a cross-sectional view in the direction of the line JJ in FIG.

  As shown in FIG. 6A, in the semiconductor device 91, the drain electrode 101 (see FIG. 6B) on the back electrode side of the semiconductor chip 92 incorporating the MOSFET and the SBD is fixed on the die pad 93. . A source electrode 94 on the surface electrode side of the semiconductor chip 92 is fixed to the lead 96 by a metal strap 95. Further, the gate electrode 97 on the surface electrode side of the semiconductor chip 92 is electrically connected to the lead 99 by the bonding wire 98. A region indicated by a dotted line is the anode region 100 of the SBD, and the source electrode 94 of the MOSFET is used as the anode electrode.

As shown in FIG. 6B, one end of the metal strap 95 is fixed to the source electrode 94 so as to completely cover the anode region 100 of the SBD, and the other end of the metal strap 95 is fixed to the lead 96. The drain electrode 101 of the MOSFET is used as the cathode electrode of the SBD.
JP-A-2004-342880 (pages 10-13 and 4-6) JP 2004-103664 A (page 4-5, Fig. 1-3)

  As described above, the conventional semiconductor device disclosed in Patent Document 1 has a package structure in which the first to third lead frames 72 to 75 are used and the MOSFET chip 77 and the SBD chip 83 are stacked. The electrodes of the MOSFET chip 77 and the SBD chip 83 are selectively bonded to the first to third lead frames 72 to 75 to form a wireless structure (a structure using no bonding wire). The leads extending from the first to third lead frames 72 to 75 are led out from the package. With this structure, each of the lead frames 72 to 75 needs to have a fixed area with the electrodes of the MOSFET chip 77 and the SBD chip 83, and the frame width is widened. Therefore, in order to prevent the first to third lead frames 72 to 75 from being short-circuited, the shapes of the first to third lead frames 72 to 75 are limited. As a result, the layout of leads derived from the package is limited, and there is a problem that it is difficult to cope with a design change of the wiring pattern on the mounting substrate.

  In addition, the conventional semiconductor device disclosed in Patent Document 2 has a package structure in one semiconductor chip 92 including, for example, a MOSFET and an SBD. Therefore, although it is one semiconductor chip 92, the chip size increases according to the electrical characteristics used, and the package size (mounting area) also increases. As a result, there is a problem that the package size (mounting area) cannot be reduced and the degree of freedom in designing is difficult to obtain even when the MOSFET chip and the SBD chip are each fixed on the mounting substrate.

  The present invention has been made in view of the above circumstances, and the semiconductor device of the present invention has a first main surface and a second main surface opposite to the first main surface, and the first main surface. A first semiconductor chip having a first electrode formed on a surface and a second electrode formed on the second main surface; a first main surface; and a second main surface facing the first main surface A second semiconductor chip having a main surface, wherein a first electrode is formed on the first main surface, and a second electrode and a third electrode are formed on the second main surface; And a second main surface opposite to the first main surface, and the first electrode of the first semiconductor chip is fixed to the first main surface via a conductive adhesive. The first die pad, the first lead led out from the first die pad in the horizontal direction, and the second electrode of the first semiconductor chip and the thin metal wire electrically A second lead disposed around the first die pad; a first main surface; and a second main surface opposite to the first main surface, the first main surface including: The first electrode of the second semiconductor chip is fixed via a conductive adhesive, and the second main surface of the first die pad is attached to the second main surface via an insulating adhesive. The second die pad fixed in this way, the third lead led out in the horizontal direction from the second die pad, and the second electrode of the second semiconductor chip and electrically connected through the fine metal wire, A fourth lead disposed around the second die pad is electrically connected to a third electrode of the second semiconductor chip via a thin metal wire, and a second lead disposed around the second die pad. And 5 leads. Therefore, in the present invention, two die pads are bonded together with an insulating adhesive, and a semiconductor chip is fixed on each die pad, thereby reducing the package size. In addition, the use of fine metal wires increases the degree of freedom in the layout of leads derived from the package, and can realize a laminated structure that can easily cope with various wiring patterns.

  In the semiconductor device of the present invention, the conductive adhesive that fixes the first electrode of the first semiconductor chip and the first main surface of the first die pad and the first of the second semiconductor chip. The conductive adhesive that adheres the electrode and the first main surface of the second die pad is an anisotropic conductive film. Therefore, in the present invention, the first semiconductor chip and the second semiconductor chip have a structure that is not easily short-circuited, and the package size is reduced while maintaining reliability.

  The semiconductor device of the present invention has a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is formed on the first main surface, and the first A first semiconductor chip in which a second electrode and a third electrode are formed on two main surfaces; a first main surface; and a second main surface facing the first main surface; A second semiconductor chip in which a first electrode is formed on a first main surface, and a second electrode and a third electrode are formed on the second main surface; the first main surface and the first A first die pad to which a first electrode of the first semiconductor chip is fixed to the first main surface via a conductive adhesive; and A first lead led out from the first die pad in a horizontal direction, and electrically connected to a second electrode of the first semiconductor chip via a fine metal wire; And a third lead disposed around the first die pad and electrically connected to the third electrode of the first semiconductor chip via a thin metal wire. And a first main surface and a second main surface opposite to the first main surface, and the first electrode of the second semiconductor chip is a conductive adhesive on the first main surface. And a second die pad in which the second main surface of the first die pad is fixed to the second main surface via an insulating adhesive, and a horizontal direction from the second die pad. A fourth lead led out to the second semiconductor chip, a fifth lead electrically connected to the second electrode of the second semiconductor chip via a fine metal wire, and disposed around the second die pad; The second die chip is electrically connected to the third electrode of the second semiconductor chip through a fine metal wire. And having a sixth leads arranged around. Therefore, in the present invention, for example, even when a plurality of MOSFET chips are stacked, the package size is reduced, and the degree of freedom in the layout of leads derived from the package is increased.

  In the present invention, two die pads are bonded together with an insulating adhesive, and a semiconductor chip is fixed on each die pad and stored in a package. With this structure, the package size is reduced in a stacked structure of semiconductor chips having electrodes on the front and back surfaces.

  In the present invention, the electrode of the semiconductor chip and the lead led out from the package are electrically connected by a thin metal wire. With this structure, the degree of freedom in the layout of leads is increased, and a laminated structure that can easily cope with a design change of the wiring pattern can be realized.

  In the present invention, a die pad bonded between semiconductor chips is disposed. An anisotropic conductive film is used as a conductive adhesive for fixing the semiconductor chip and the die pad. With this structure, the conductive adhesive does not flow when the semiconductor chip is fixed, and a short circuit between the electrodes of the semiconductor chip can be prevented. Then, the reliability of the semiconductor device is maintained, and the package size is reduced.

  In the present invention, a die pad bonded between semiconductor chips is disposed. With this structure, the die pad is also used as a heat dissipation plate, and heat dissipation is improved.

  The semiconductor device according to the first embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1A is a plan view for explaining the semiconductor device of this embodiment mode. FIG. 1B is a cross-sectional view taken along line AA of the semiconductor device illustrated in FIG. FIG. 1C is a cross-sectional view taken along line BB of the semiconductor device illustrated in FIG. FIG. 2A is a plan view for explaining the semiconductor device in this embodiment. FIG. 2B is a cross-sectional view taken along line CC of the semiconductor device illustrated in FIG. FIG. 2C is a cross-sectional view taken along line DD of the semiconductor device illustrated in FIG.

  As shown in FIG. 1A, in the semiconductor device 1 of the present embodiment, the SBD chip 3 is fixed to the surface side of the die pad 2 via the conductive paste 16 (see FIG. 1B). The SBD chip 3 has an anode electrode 4 formed on the surface side thereof. Dotted lines indicate the outer shape of the package. Leads 6 to 10 are led out from the package 5 and used as external terminals.

  As shown in FIG. 1B, the back side of the die pad 12 is bonded to the back side of the die pad 2 with an insulating adhesive 11. The die pad 12 has the same shape as the die pad 2, and the die pad 2 and the die pad 12 are insulated by an insulating adhesive 11. An N-channel MOSFET chip 14 is fixed to the surface side of the die pad 12 via a conductive adhesive, for example, a conductive paste 13 such as solder paste or Ag paste, or a solder wire. The lead 6 is formed continuously with the die pad 12. The die pad 12 is fixed to the drain electrode 15 of the MOSFET chip 14, and the lead 6 is used as a drain terminal.

  On the other hand, the cathode electrode 17 of the SBD chip 3 is fixed to the surface side of the die pad 2 via a conductive adhesive 16, for example, a conductive paste 16 such as solder paste or Ag paste, or a solder wire. The lead 7 is disposed in the vicinity of the die pad 2 and is electrically connected to the anode electrode 4 of the SBD chip 3 through the fine metal wire 18, and the lead 7 is used as an anode terminal.

  As shown in FIG. 1C, the lead 8 is formed continuously with the die pad 2. As described above, the lead 8 is used as a cathode terminal. The lead 9 is disposed in the vicinity of the die pad 12 and is electrically connected to the source electrode 20 of the MOSFET chip 14 through the fine metal wire 19, and the lead 9 is used as a source terminal.

  As shown in FIG. 1A, the lead 10 is electrically connected to a gate electrode (not shown) of the MOSFET chip 14 through a fine metal wire 21, and the lead 10 is used as a gate terminal.

  With this structure, leads 6 to 10 connected to individual electrodes of the SBD chip 3 and the MOSFET chip 14 are led out from the package 5. That is, it is possible to apply different potentials to the individual electrodes of the SBD chip 3 and the MOSFET chip 14, and it is possible to cope with any circuit design. The die pads 2 and 12 and the leads 6 to 10 are formed by molding a copper (Cu) lead frame (hereinafter referred to as a Cu frame).

  Further, the die pads 2 and 12 are bonded together by the insulating adhesive 11, and the leads 7, 9 and 10 are substantially located on the same plane as the die pads 2 and 12. With this structure, as shown in FIG. 1B, for example, the separation distance L1 between the anode electrode 4 and the lead 7 of the SBD chip 3 is reduced. Although the minimum distance L2 between the end of the SBD chip 3 and the fine metal wire 18 is necessary, the fine metal wire 18 is connected to the lead 7 close to the die pad 2. As a result, the package size (mounting area) can be reduced. Furthermore, since the separation distance L1 is reduced, the separation distance L3 from the surface of the SBD chip 3 to the top of the thin metal wire 18 can be reduced while reducing the package size. Although the thickness of the package 5 (Y-axis direction on the paper surface) is adjusted by the position of the top of the thin metal wire 18, the thickness of the package 5 can be reduced by this structure.

  The leads 7, 9, and 10 are connected to the electrodes of the SBD chip 3 and the MOSFET chip 14 through metal thin wires 18, 19, and 21, respectively. By using the thin metal wires 18, 19, and 21, the degree of freedom of layout of the leads 7, 9, and 10 is increased, and the leads 6 to 10 can be led out from arbitrary locations with respect to the package 5. Specifically, as shown in FIG. 1A, not only when leads 6 to 10 are led out from the X axis direction to the package 5, but also from the Y axis direction according to the purpose of use. The leads 6 to 10 can be led out. It is possible to easily cope with an arbitrary design change according to a wiring pattern on a mounting substrate (not shown) on which the semiconductor device 1 is mounted.

  The die pad 2 is fixed to the cathode electrode 17 of the SBD chip 3 via a conductive paste 16 or a solder wire. On the other hand, the die pad 12 is fixed to the drain electrode 15 of the MOSFET chip 14 via the conductive paste 13 and the solder wire. With this structure, heat generated during operation of the SBD chip 3 and the MOSFET chip 14 is radiated through the die pads 2 and 12. That is, the die pads 2 and 12 can improve heat dissipation, and can prevent the SBD chip 3 and the MOSFET chip 14 from changing their characteristics due to heat generated by themselves or heat generated from each other.

  As described above, the case where the SBD chip 3 and the MOSFET chip 14 are fixed to the die pads 2 and 12 via the conductive pastes 16 and 13 has been described. However, the present invention is not limited to this case. As the conductive adhesive, for example, an anisotropic conductive film (ACF (Anisotropic Conductive Film)) may be used.

  Here, in the anisotropic conductive film, conductive particles are dispersed in an insulating adhesive based on a thermosetting resin. Then, by heating and pressurizing when bonding the SBD chip 3 and the MOSFET chip 14 on the anisotropic conductive film, the conductive particles below the fixing region come into contact with each other, and electrical conduction is obtained. As a result, conductivity between the electrodes of the SBD chip 3 and the MOSFET chip 14 and the die pads 2 and 12 is obtained. That is, by using an anisotropic conductive film as the bonding means on the upper surfaces of the die pads 2 and 12, the conductive adhesive does not flow when bonding the SBD chip 3 and the MOSFET chip 14. And the short circuit between the electrodes of the SBD chip 3 and the MOSFET chip 14 can be prevented. In particular, the anisotropic conductive film can prevent a short circuit due to the flow of the conductive adhesive when the package size is reduced, and is an effective bonding means in the laminated structure.

  Finally, the package 5 is formed of a resin package, a metal package, or the like.

  Next, in the semiconductor device 22 shown in FIG. 2A, as in the semiconductor device 1 shown in FIG. 1A, for example, an SBD chip and an N-channel MOSFET chip are fixed so that a die pad is sandwiched between them. Yes. When comparing the semiconductor device 22 and the semiconductor device 1 (see FIG. 1A), the semiconductor device 22 has a structure that does not use a thin metal wire. Therefore, the structure for fixing the SBD chip and the MOSFET chip is referred to the description of FIGS. 1A to 1C described above, and the description is omitted here. 2A to 2C, the same reference numerals are used for the same components as those shown in FIGS. 1A to 1C.

  As shown in FIG. 2A, in the semiconductor device 22, the SBD chip 3 is fixed on the die pad 2. Leads 6 to 10 are led out from the package 5 indicated by a dotted line and used as external terminals. As described above with reference to FIG. 1A, the lead 8 is formed continuously with the die pad 2, and the lead 6 is formed continuously with the die pad 12. On the other hand, the leads 7, 9, and 10 are formed from conductive plates 23 to 25 that are independent of the die pads 2 and 12. One end side of each of the conductive plates 23 to 25 is fixed to an electrode of the SBD chip 3 or the MOSFET chip 14 through a conductive adhesive, for example, an anisotropic conductive film. The conductive plates 23 to 25 are made of a conductive material such as a Cu frame.

  As shown in FIG. 2B, one end side of the conductive plate 23 is fixed to the anode electrode 4 of the SBD chip 3 via the anisotropic conductive film 26. The conductive plate 23 is led out substantially horizontally from the surface of the SBD chip 3, and the lead 7 which is the other end side of the conductive plate 23 is substantially located on the same plane as the die pad 2.

  As shown in FIG. 2C, one end side of the conductive plate 25 is fixed via the gate electrode 27 and the anisotropic conductive film 28 of the MOSFET chip 14. The conductive plate 25 is led out substantially horizontally from the surface of the MOSFET chip 14, and the lead 10 which is the other end side of the conductive plate 25 is substantially located on the same plane as the die pad 12.

  Although not shown, one end side of the conductive plate 24 is fixed to the source electrode 20 of the MOSFET chip 14 via an anisotropic conductive film. The conductive plate 24 is led out substantially horizontally from the surface of the MOSFET chip 14, and the lead 9 which is the other end side of the conductive plate 24 is substantially located on the same plane as the die pad 12.

  As described above, in this embodiment, an anisotropic conductive film is used as a fixing material between the electrode of the SBD chip 3 or the MOSFET chip 14 and the conductive plates 23 to 25. With this structure, the conductive adhesive does not flow out due to heat or the like at the time of fixing as compared with the case where a conductive adhesive such as a solder paste is used. And the short circuit between electrodes by the flow-out of a conductive adhesive agent can be prevented.

  Further, heat generated during the operation of the SBD chip 3 or the MOSFET chip 14 is dissipated through the die pads 2 and 12 and the conductive plates 23 to 25. With this structure, heat dissipation in the semiconductor device 22 is improved, and it is possible to prevent the SBD chip 3 and the MOSFET chip 14 from changing their characteristics due to their own generated heat and each other's generated heat.

  Moreover, since the die pads 2 and 12 are bonded together with an insulating adhesive, they are substantially located on the same plane. The leads 6 to 10 are located on the same plane as the die pads 2 and 12 in the vicinity of the die pads 2 and 12. However, the leads 6 to 10 may be located slightly above and below the plane of the die pads 2 and 12.

  Further, not only when the leads 6 to 10 are led out from the X-axis direction with respect to the package 5, but also according to the purpose of use, the leads 6 to 10 can be led out from the Y-axis direction with respect to the package 5. It is possible to easily cope with an arbitrary design change according to a wiring pattern on a mounting substrate (not shown) on which the semiconductor device 22 is mounted.

  In the present embodiment, the case where the die pads 2 and 12 and the conductive plates 23 to 25 are formed from a Cu frame has been described. However, the present invention is not limited to this case. For example, a lead frame mainly made of Fe—Ni may be used instead of the Cu frame, or another metal material may be used. In the present embodiment, the structure in which the two semiconductor chips of the SBD chip 3 and the MOSFET chip 14 are stacked has been described. However, the present invention is not limited to this case. For example, three or more semiconductor chips may be stacked. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a semiconductor device according to a second embodiment of the present invention will be described in detail with reference to FIGS. FIG. 3A is a plan view for explaining the semiconductor device in this embodiment. FIG. 3B is a cross-sectional view taken along the line EE of the semiconductor device illustrated in FIG. FIG. 3C is a cross-sectional view taken along line FF of the semiconductor device illustrated in FIG. FIG. 4A is a plan view for explaining the semiconductor device in this embodiment. FIG. 4B is a cross-sectional view taken along line GG of the semiconductor device illustrated in FIG. FIG. 4C is a cross-sectional view taken along line HH of the semiconductor device illustrated in FIG.

  As shown in FIG. 3A, in the semiconductor device 31 of the present embodiment, an N-channel MOSFET chip 33 is fixed to the surface side of the die pad 32 via a conductive paste 48 (see FIG. 3B). is doing. The MOSFET chip 33 has a source electrode 34 and a gate electrode 35 formed on the surface side thereof. Dotted lines indicate the outer shape of the package. Leads 37 to 42 are led out from the package 36 and used as external terminals.

  As shown in FIG. 3B, the back side of the die pad 44 is bonded to the back side of the die pad 32 by an insulating adhesive 43. The die pad 44 has the same shape as the die pad 32, and the die pad 32 and the die pad 44 are insulated by an insulating adhesive 43. On the surface side of the die pad 44, an N-channel MOSFET chip 46 is fixed via a conductive adhesive 45, for example, a conductive paste 45 such as solder paste or Ag paste, or a solder wire. The lead 37 is formed continuously with the die pad 44. The die pad 44 is fixed to the drain electrode 47 of the MOSFET chip 46, and the lead 37 is used as a drain terminal.

  On the other hand, the drain electrode 49 of the MOSFET chip 33 is fixed to the surface side of the die pad 32 through a conductive adhesive 48, for example, a conductive paste 48 such as solder paste or Ag paste, or a solder wire. The lead 38 is disposed in the vicinity of the die pad 32 and is electrically connected to the source electrode 34 of the MOSFET chip 33 through the fine metal wire 50, and the lead 38 is used as a source terminal.

  As shown in FIG. 3C, the lead 39 is formed continuously with the die pad 32, and the lead 39 is used as a drain terminal. The lead 40 is disposed in the vicinity of the die pad 44 and is electrically connected to the source electrode 52 of the MOSFET chip 46 through the fine metal wire 51, and the lead 40 is used as a source terminal.

  As shown in FIG. 3A, the lead 41 is electrically connected to the gate electrode 35 of the MOSFET chip 33 through the fine metal wire 53, and the lead 41 is used as a gate terminal. The lead 42 is electrically connected to a gate electrode (not shown) of the MOSFET chip 46 through a fine metal wire 54, and the lead 42 is used as a gate terminal.

  With this structure, leads 37 to 42 connected to the individual electrodes of the MOSFET chips 33 and 46 are led out from the package 36. In other words, different potentials can be applied to the individual electrodes of the MOSFET chips 33 and 46, and any circuit design can be accommodated. The die pads 32 and 44 and the leads 37 to 42 are formed by molding a copper (Cu) lead frame (hereinafter referred to as a Cu frame).

  The die pads 32 and 44 are bonded together by the insulating adhesive 43, and the leads 38 and 40 to 42 are substantially located on the same plane as the die pads 32 and 44. With this structure, as shown in FIG. 3B, for example, the distance L4 between the source electrode 34 of the MOSFET chip 33 and the lead 38 is reduced. Although the minimum distance L5 between the end of the MOSFET chip 33 and the fine metal wire 50 is necessary, the fine metal wire 50 is connected on the lead 38 close to the die pad 32. As a result, the package size (mounting area) can be reduced. Furthermore, since the separation distance L4 is reduced, it is possible to reduce the separation distance L6 from the surface of the MOSFET chip 33 to the top of the thin metal wire 50 while reducing the package size. The thickness of the package 36 (in the Y-axis direction on the paper surface) is adjusted by the position of the top of the thin metal wire 50, but with this structure, the thickness of the package 36 can be reduced.

  Further, the leads 38 and 40 to 42 are connected to the electrodes of the MOSFET chips 33 and 46 through the thin metal wires 50, 51, 53 and 54, respectively. By using the thin metal wires 50, 51, 53, 54, the degree of freedom of layout of the leads 38, 40-42 is increased, and the leads 38, 40-42 can be led out from arbitrary locations with respect to the package 36. Become. Specifically, as shown in FIG. 3A, not only when leads 37 to 42 are led out from the X-axis direction with respect to the package 36, but also with respect to the package 36 from the Y-axis direction depending on the purpose of use. The leads 37 to 42 can be led out. It is possible to easily cope with any design change according to the wiring pattern on the mounting substrate (not shown) on which the semiconductor device 31 is mounted.

  The die pad 32 is fixed to the drain electrode 49 of the MOSFET chip 33 via the conductive paste 48 and the solder wire. On the other hand, the die pad 44 is fixed to the drain electrode 47 of the MOSFET chip 46 via the conductive paste 45 and the solder wire. With this structure, heat generated during the operation of the MOSFET chips 33 and 46 is dissipated through the die pads 32 and 44. That is, the die pads 32 and 44 can improve heat dissipation, and can prevent the MOSFET chips 33 and 46 from changing their characteristics due to their own heat generation or mutual heat generation.

  As described above, the case where the MOSFET chips 33 and 46 are fixed to the die pads 32 and 44 via the conductive pastes 48 and 45 has been described. However, the present invention is not limited to this case. For example, an anisotropic conductive film may be used as the conductive adhesive. As described above, by using the anisotropic conductive film, conductivity between the drain electrodes 49 and 47 of the MOSFET chips 33 and 46 and the die pads 32 and 44 can be obtained, and conductive bonding is performed when the MOSFET chips 33 and 46 are bonded. The agent does not flow out. And it can prevent that the drain electrodes 49 and 47 of MOSFET chip | tip 333 and 46 short-circuit.

  Finally, the package 36 is formed of a resin package, a metal package, or the like.

  Next, in the semiconductor device 55 shown in FIG. 4A, as in the semiconductor device 31 shown in FIG. 3A, for example, two N-channel MOSFET chips are fixed so as to sandwich the die pad. When comparing the semiconductor device 55 and the semiconductor device 31 (see FIG. 3A), the semiconductor device 55 has a structure that does not use a thin metal wire. Therefore, the structure for fixing the MOSFET chip is referred to the description of FIGS. 3A to 3C described above, and the description is omitted here. 4A to 4C, the same reference numerals are used for the same components as those shown in FIGS. 3A to 3C.

  As shown in FIG. 4A, in the semiconductor device 55, the MOSFET chip 33 is fixed on the die pad 32. Leads 37 to 42 are led out from a package 36 indicated by a dotted line, and are used as external terminals. As described above with reference to FIG. 3A, the lead 39 is formed continuously with the die pad 32, and the lead 37 is formed continuously with the die pad 44. On the other hand, the leads 38 and 40 to 42 are formed of conductive plates 56 to 59 that are independent of the die pads 32 and 44. One end sides of the conductive plates 56 to 59 are fixed to the electrodes of the MOSFET chips 33 and 46 via a conductive adhesive, for example, an anisotropic conductive film. The conductive plates 56 to 59 are made of a conductive material such as a Cu frame.

  As shown in FIG. 4B, one end side of the conductive plate 56 is fixed to the source electrode 34 of the MOSFET chip 33 via the anisotropic conductive film 60. The conductive plate 56 is led out substantially horizontally from the surface of the MOSFET chip 33, and the lead 38 which is the other end side of the conductive plate 56 is substantially located on the same plane as the die pad 32. One end side of the conductive plate 57 is fixed to the source electrode 52 of the MOSFET chip 46 via the anisotropic conductive film 61. The conductive plate 57 is led out from the surface of the MOSFET chip 46 in a substantially horizontal direction, and the lead 40 which is the other end side of the conductive plate 57 is substantially located on the same plane as the die pad 44.

  As shown in FIG. 4C, one end side of the conductive plate 59 is fixed via the gate electrode 62 of the MOSFET chip 46 and the anisotropic conductive film 63. The conductive plate 59 is led out substantially horizontally from the surface of the MOSFET chip 46, and the lead 42 which is the other end side of the conductive plate 59 is substantially located on the same plane as the die pad 44.

  As shown in FIG. 4A, one end side of the conductive plate 58 is fixed to the gate electrode 35 of the MOSFET chip 33 via an anisotropic conductive film (not shown). The conductive plate 58 is led out substantially horizontally from the surface of the MOSFET chip 33, and the lead 41 which is the other end side of the conductive plate 58 is substantially located on the same plane as the die pad 32.

  As described above, in this embodiment, an anisotropic conductive film is used as a fixing material between the electrodes of the MOSFET chips 33 and 46 and the conductive plates 56 to 59. With this structure, the conductive adhesive does not flow out due to heat or the like at the time of fixing as compared with the case where a conductive adhesive such as a solder paste is used. And the short circuit between electrodes by the flow-out of a conductive adhesive agent can be prevented.

  Further, heat generated during the operation of the MOSFET chips 33 and 46 is dissipated through the die pads 32 and 44 and the conductive plates 56 to 59. With this structure, heat dissipation in the semiconductor device 55 is improved, and the MOSFET chips 33 and 46 can be prevented from changing their characteristics due to heat generated by themselves or heat generated from each other.

  Moreover, since the die pads 32 and 44 are bonded together with an insulating adhesive, they are substantially located on the same plane. The leads 37 to 42 are located on the same plane as the die pads 32 and 44 in the vicinity of the die pads 32 and 44. However, the leads 37 to 42 may be positioned slightly above and below the plane of the die pads 32 and 44.

  Further, not only when the leads 37 to 42 are led out from the X axis direction with respect to the package 36, but also according to the purpose of use, the leads 37 to 42 can be led out from the Y axis direction with respect to the package 36. It is possible to easily cope with an arbitrary design change according to a wiring pattern on a mounting substrate (not shown) on which the semiconductor device 55 is mounted.

  In this embodiment, the case where the die pads 32 and 44 and the conductive plates 56 to 59 are formed from a Cu frame has been described. However, the present invention is not limited to this case. For example, a lead frame mainly made of Fe—Ni may be used instead of the Cu frame, or another metal material may be used. In the present embodiment, a structure in which two semiconductor chips, MOSFET chips 33 and 46, are stacked is described. However, the present invention is not limited to this case. For example, three or more semiconductor chips may be stacked. In addition, various modifications can be made without departing from the scope of the present invention.

It is (A) top view for demonstrating the semiconductor device in embodiment of this invention, (B) It is sectional drawing along the AA line shown to (A), (C) It shows to (A) It is sectional drawing along the BB line. It is (A) top view for demonstrating the semiconductor device in embodiment of this invention, (B) It is sectional drawing along CC line shown to (A), (C) It shows to (A) It is sectional drawing along the DD line. It is (A) top view for demonstrating the semiconductor device in embodiment of this invention, (B) It is sectional drawing along the EE line shown to (A), (C) It shows to (A) It is sectional drawing along the FF line. It is (A) top view for demonstrating the semiconductor device in embodiment of this invention, (B) It is sectional drawing along the GG line | wire shown to (A), (C) It shows to (A) It is sectional drawing along the HH line. It is (A) top view for demonstrating the conventional semiconductor device, (B) It is sectional drawing along the II line | wire shown to (A). It is (A) top view for demonstrating the conventional semiconductor device, and is sectional drawing along the JJ line | wire shown to (B) (A).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Die pad 3 SBD chip 11 Insulating adhesive 12 Die pad 13, 16 Anisotropic conductive film 14 MOSFET chip

Claims (8)

A first main surface and a second main surface opposite to the first main surface, wherein the first electrode is formed on the first main surface, and the second electrode is formed on the second main surface. A first semiconductor chip formed with:
A first main surface and a second main surface opposite to the first main surface, wherein the first electrode is formed on the first main surface, and the second electrode is formed on the second main surface. And a second semiconductor chip on which a third electrode is formed,
A first main surface and a second main surface opposite to the first main surface, and the first electrode of the first semiconductor chip is interposed on the first main surface with a conductive adhesive. A first die pad fixed by
A first lead led out horizontally from the first die pad;
A second lead electrically connected to the second electrode of the first semiconductor chip via a fine metal wire and disposed around the first die pad;
A first main surface and a second main surface opposite to the first main surface, and the first electrode of the second semiconductor chip is interposed on the first main surface with a conductive adhesive. And a second die pad in which the second main surface of the first die pad is fixed to the second main surface via an insulating adhesive;
A third lead led out horizontally from the second die pad;
A fourth lead electrically connected to the second electrode of the second semiconductor chip through a fine metal wire and disposed around the second die pad;
A semiconductor device comprising: a fifth lead electrically connected to a third electrode of the second semiconductor chip through a fine metal wire and disposed around the second die pad. A conductive adhesive that fixes the first electrode of the first semiconductor chip and the first main surface of the first die pad, and the first electrode of the second semiconductor chip and the second die pad; The semiconductor device according to claim 1, wherein the conductive adhesive fixed to the first main surface is an anisotropic conductive film. A first main surface and a second main surface opposite to the first main surface, wherein the first electrode is formed on the first main surface, and the second electrode is formed on the second main surface. A first semiconductor chip formed with:
A first main surface and a second main surface opposite to the first main surface, wherein the first electrode is formed on the first main surface, and the second electrode is formed on the second main surface. And a second semiconductor chip on which a third electrode is formed,
A first main surface and a second main surface opposite to the first main surface, and the first electrode of the first semiconductor chip is interposed on the first main surface with a conductive adhesive. A first die pad fixed by
A first lead led out horizontally from the first die pad;
A first conductive plate having one end fixed to the second electrode of the first semiconductor chip via a conductive adhesive and the other end disposed around the first die pad as a second lead;
A first main surface and a second main surface opposite to the first main surface, and the first electrode of the second semiconductor chip is interposed on the first main surface with a conductive adhesive. And a second die pad in which the second main surface of the first die pad is fixed to the second main surface via an insulating adhesive;
A third lead led out horizontally from the second die pad;
A second conductive plate having one end side fixed to the second electrode of the second semiconductor chip via a conductive adhesive and the other end side disposed as a fourth lead around the second die pad;
One end side is fixed to the third electrode of the second semiconductor chip via a conductive adhesive, and the other end side has a third conductive plate disposed around the second die pad as a fifth lead. A semiconductor device. A conductive adhesive that fixes at least the first electrode of the first semiconductor chip and the first main surface of the first die pad; the first electrode of the second semiconductor chip; and the second die pad. A conductive adhesive fixed to the first main surface, a conductive adhesive fixed to the second electrode of the first semiconductor chip and the first conductive plate, and a second adhesive of the second semiconductor chip. Either a conductive adhesive that fixes the second electrode and the second conductive plate or a conductive adhesive that fixes the third electrode of the second semiconductor chip and the third conductive plate, The semiconductor device according to claim 3, wherein the semiconductor device is an anisotropic conductive film. A first main surface and a second main surface opposite to the first main surface, wherein the first electrode is formed on the first main surface, and the second electrode is formed on the second main surface. And a first semiconductor chip on which a third electrode is formed,
A first main surface and a second main surface opposite to the first main surface, wherein the first electrode is formed on the first main surface, and the second electrode is formed on the second main surface. And a second semiconductor chip on which a third electrode is formed,
A first main surface and a second main surface opposite to the first main surface, and the first electrode of the first semiconductor chip is interposed on the first main surface with a conductive adhesive. A first die pad fixed by
A first lead led out horizontally from the first die pad;
A second lead electrically connected to the second electrode of the first semiconductor chip via a fine metal wire and disposed around the first die pad;
A third lead electrically connected to the third electrode of the first semiconductor chip via a fine metal wire and disposed around the first die pad;
A first main surface and a second main surface opposite to the first main surface, and the first electrode of the second semiconductor chip is interposed on the first main surface with a conductive adhesive. And a second die pad in which the second main surface of the first die pad is fixed to the second main surface via an insulating adhesive;
A fourth lead led out horizontally from the second die pad;
A fifth lead electrically connected to the second electrode of the second semiconductor chip via a fine metal wire and disposed around the second die pad;
A semiconductor device comprising: a sixth lead electrically connected to a third electrode of the second semiconductor chip through a fine metal wire and disposed around the second die pad. A conductive adhesive that fixes the first electrode of the first semiconductor chip and the first main surface of the first die pad, and the first electrode of the second semiconductor chip and the second die pad; 6. The semiconductor device according to claim 5, wherein the conductive adhesive fixed to the first main surface is an anisotropic conductive film. A first main surface and a second main surface opposite to the first main surface, wherein the first electrode is formed on the first main surface, and the second electrode is formed on the second main surface. And a first semiconductor chip on which a third electrode is formed,
A first main surface and a second main surface opposite to the first main surface, wherein the first electrode is formed on the first main surface, and the second electrode is formed on the second main surface. And a second semiconductor chip on which a third electrode is formed,
A first main surface and a second main surface opposite to the first main surface, and the first electrode of the first semiconductor chip is interposed on the first main surface with a conductive adhesive. A first die pad fixed by
A first lead led out horizontally from the first die pad;
A first conductive plate having one end fixed to the second electrode of the first semiconductor chip via a conductive adhesive and the other end disposed around the first die pad as a second lead;
A second conductive plate having one end side fixed to the third electrode of the first semiconductor chip via a conductive adhesive and the other end side disposed around the first die pad as a third lead;
A first main surface and a second main surface opposite to the first main surface, and the first electrode of the second semiconductor chip is interposed on the first main surface with a conductive adhesive. And a second die pad in which the second main surface of the first die pad is fixed to the second main surface via an insulating adhesive;
A fourth lead led out horizontally from the second die pad;
A third conductive plate, one end of which is fixed to the second electrode of the second semiconductor chip via a conductive adhesive, and the other end is disposed around the second die pad as a fifth lead;
One end side is fixed to the third electrode of the second semiconductor chip via a conductive adhesive, and the other end side has a fourth conductive plate disposed around the second die pad as a sixth lead. A semiconductor device. A conductive adhesive that fixes at least the first electrode of the first semiconductor chip and the first main surface of the first die pad; the first electrode of the second semiconductor chip; and the second die pad. A conductive adhesive fixed to the first main surface, a conductive adhesive fixed to the second electrode of the first semiconductor chip and the first conductive plate, and a first adhesive of the first semiconductor chip. 3 and the second conductive plate, a conductive adhesive that fixes the second electrode of the second semiconductor chip and the third conductive plate, or the second adhesive plate. 8. The semiconductor device according to claim 7, wherein any one of the conductive adhesives fixing the third electrode of the semiconductor chip and the fourth conductive plate is an anisotropic conductive film.

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