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JP2007027576A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007027576A
JP2007027576A JP2005210380A JP2005210380A JP2007027576A JP 2007027576 A JP2007027576 A JP 2007027576A JP 2005210380 A JP2005210380 A JP 2005210380A JP 2005210380 A JP2005210380 A JP 2005210380A JP 2007027576 A JP2007027576 A JP 2007027576A
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Prior art keywords
semiconductor device
alignment
mounting substrate
connection terminal
bump
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JP2005210380A
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Japanese (ja)
Inventor
Shingo Higuchi
晋吾 樋口
Osamu Miyata
修 宮田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2005210380A priority Critical patent/JP2007027576A/en
Publication of JP2007027576A publication Critical patent/JP2007027576A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Abstract

<P>PROBLEM TO BE SOLVED: To securely connect connection-terminals on a semiconductor device to lands on the mounting board in the semionductor device surface mounted on the mounting board. <P>SOLUTION: The connection-terminals 2 formed in a ball shape with the use of a metal material and electrically connected to the lands 5 on the mounting board 4, and a bump 3 for an alignment formed in a ball shape having a diameter larger than that of the connection terminal 2 and pressed to the pads 6 for an alignment on the mounting board 4, are provided on the surface 1a of the semiconductor device 1 facing to the mounting board 4. The bump 3 for the alignment comprises an inside component part 31 formed by the same metal material as the connection-terminal 2 in the ball shape having an approximately the same diameter as that of the connection-terminal 2, and an outside component part 32 formed with the use of the solder material having a melting point lower than that of the inside structure 31. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、実装基板に表面実装される半導体装置に関する。   The present invention relates to a semiconductor device that is surface-mounted on a mounting substrate.

従来から、表面実装型パッケージの代表的なものとして、たとえば、ＢＧＡ（Ball Grid Array）が知られている。
このＢＧＡが採用された半導体装置では、実装基板に対向配置される一方面上に、複数のボール状の接続端子が格子状に配置されている。一方、実装基板上には、複数のランド（電極）が接続端子の配列に対応する格子状に配置されている。そして、半導体装置の一方面を実装基板に対向させて、各接続端子が実装基板上のランドと対向するように位置合わせした後、半導体装置を実装基板に近接させ、各接続端子をランドに接続することによって、半導体装置の実装基板に対する表面実装が達成される。
特開平１０−２５６３０８号公報 Conventionally, for example, BGA (Ball Grid Array) is known as a typical surface mount package.
In a semiconductor device adopting this BGA, a plurality of ball-like connection terminals are arranged in a grid pattern on one surface opposed to the mounting substrate. On the other hand, on the mounting substrate, a plurality of lands (electrodes) are arranged in a lattice shape corresponding to the arrangement of connection terminals. Then, one side of the semiconductor device is made to face the mounting board, and after positioning so that each connection terminal faces the land on the mounting board, the semiconductor device is brought close to the mounting board, and each connection terminal is connected to the land. By doing so, surface mounting on the mounting substrate of the semiconductor device is achieved.
JP-A-10-256308

ところが、各接続端子と実装基板上のランドとが精度よく位置合わせされないと、すべての接続端子がランドに接続されず、半導体装置と実装基板との間の導通不良などの実装不良を生じるおそれがある。
そこで、この発明の目的は、接続端子を実装基板上のランドに対して確実に接続させることができる半導体装置を提供することである。 However, if the connection terminals and the lands on the mounting board are not accurately aligned, all the connection terminals are not connected to the lands, and there is a risk of causing a mounting failure such as a continuity failure between the semiconductor device and the mounting board. is there.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of reliably connecting a connection terminal to a land on a mounting board.

上記の目的を達成するための請求項１記載の発明は、実装基板に表面実装される半導体装置であって、前記実装基板との対向面上に、金属材料を用いてボール状に形成され、前記実装基板上のランドと電気接続される接続端子と、前記対向面上に、前記接続端子よりも大きな径を有するボール状に形成され、前記実装基板上のアライメント用パッドに当接されるアライメント用バンプとを含み、前記アライメント用バンプは、前記接続端子と同じ金属材料を用いて、前記接続端子とほぼ同じ径を有するボール状に形成された内側構成部と、前記内側構成部を形成する金属材料よりも低い融点を有するはんだ材料を用いて形成され、前記内側構成部の表面を被覆する外側構成部とを備えていることを特徴とする、半導体装置である。   The invention according to claim 1 for achieving the above object is a semiconductor device that is surface-mounted on a mounting substrate, and is formed in a ball shape using a metal material on a surface facing the mounting substrate. A connection terminal that is electrically connected to a land on the mounting substrate, and an alignment that is formed in a ball shape having a larger diameter than the connection terminal on the facing surface and abuts against an alignment pad on the mounting substrate The alignment bump includes an inner component formed in a ball shape having substantially the same diameter as the connection terminal, and the inner component using the same metal material as the connection terminal. A semiconductor device, comprising: a solder material having a melting point lower than that of a metal material; and an outer component that covers a surface of the inner component.

この構成によれば、アライメント用バンプは、接続端子よりも大きな径を有する。したがって、半導体装置の接続端子およびアライメント用バンプが形成されている面を実装基板に対向させて、アライメント用バンプが実装基板上のアライメント用パッドと対向するように、その半導体装置と実装基板とを位置合わせした後、半導体装置を実装基板に近接させると、アライメント用バンプがアライメント用パッドに当接し、半導体装置がアライメント用バンプによって実装基板上に支持された状態となる。このとき、各接続端子は、実装基板上のランドから離間している。   According to this configuration, the alignment bump has a larger diameter than the connection terminal. Therefore, the semiconductor device and the mounting substrate are mounted so that the connection terminal of the semiconductor device and the surface on which the alignment bump is formed are opposed to the mounting substrate, and the alignment bump is opposed to the alignment pad on the mounting substrate. After the alignment, when the semiconductor device is brought close to the mounting substrate, the alignment bump comes into contact with the alignment pad, and the semiconductor device is supported on the mounting substrate by the alignment bump. At this time, each connection terminal is separated from the land on the mounting substrate.

アライメント用バンプは、接続端子と同じ金属材料からなる内側構成部と、この内側構成部を被覆し、内側構成部の材料よりも低い融点を有するはんだ材料からなる外側構成部とを備える。したがって、半導体装置がアライメント用バンプによって実装基板上に支持された状態でリフローが行われると、接続端子が溶融し始めるよりも先に、アライメント用バンプの外側構成部が溶融する。外側構成部が溶融すると、その溶融したはんだ材料の表面張力によって、実装基板上の半導体装置が、実装基板を垂直に見下ろす平面視において、アライメント用バンプの中心とアライメント用パッドの中心とが一致する位置にアライメントされる。そして、外側構成部の溶融に伴って、半導体装置がアライメントされつつ実装基板に近接していき、外側構成部が完全に溶融すると、内側構成部が実装基板上のアライメント用パッドに当接するとともに、接続端子が実装基板上のランドに当接する。そのため、半導体装置と実装基板との位置合わせが精度よく行われず、アライメント用バンプがアライメント用パッドに当接された時点で、平面視において各接続端子の位置がランドの位置に対してずれていても、外側構成部の溶融過程でアライメントが行われ、接続端子をランドに対して確実に接続させることができる。その結果、半導体装置の実装基板に対する良好な表面実装を達成することができる。   The alignment bump includes an inner component made of the same metal material as the connection terminal, and an outer component made of a solder material that covers the inner component and has a lower melting point than the material of the inner component. Therefore, when the reflow is performed in a state where the semiconductor device is supported on the mounting substrate by the alignment bumps, the outer constituent portions of the alignment bumps are melted before the connection terminals start to melt. When the outer constituent portion melts, the center of the alignment bump and the center of the alignment pad coincide with each other in a plan view in which the semiconductor device on the mounting substrate vertically looks down on the mounting substrate due to the surface tension of the molten solder material. Aligned to position. Then, as the outer component is melted, the semiconductor device is brought closer to the mounting substrate while being aligned, and when the outer component is completely melted, the inner component contacts the alignment pad on the mounting substrate, The connection terminal contacts the land on the mounting board. For this reason, the alignment of the semiconductor device and the mounting substrate is not performed accurately, and the position of each connection terminal is shifted from the position of the land in plan view when the alignment bump contacts the alignment pad. In addition, alignment is performed in the melting process of the outer constituent portion, and the connection terminal can be reliably connected to the land. As a result, good surface mounting on the mounting substrate of the semiconductor device can be achieved.

また、アライメント用バンプの内側構成部は、接続端子と同じ金属材料を用いられて、ほぼ同じ径を有するボール状に形成されているので、接続端子と同一工程で作成することができる。
また、請求項２記載の発明は、前記対向面は、矩形状に形成されており、前記アライメント用バンプは、前記対向面の四隅に配置されていることを特徴とする、請求項１記載の半導体装置である。 Further, since the inner component part of the alignment bump is formed in a ball shape having the same diameter by using the same metal material as that of the connection terminal, it can be formed in the same process as the connection terminal.
The invention according to claim 2 is characterized in that the facing surface is formed in a rectangular shape, and the alignment bumps are arranged at four corners of the facing surface. It is a semiconductor device.

この構成によれば、アライメント用バンプが半導体装置の実装基板に対する対向面の四隅に配置されているので、その４つのアライメント用バンプの外側構成部が溶融したときに、半導体装置の対向面の各隅において、半導体装置の実装基板に対する位置をアライメントすることができる。そのため、接続端子をより精度よくランドに対向させることができる。その結果、接続端子をランドに対してより確実に接続させることができ、半導体装置の実装基板に対する一層良好な表面実装を達成することができる。   According to this configuration, since the alignment bumps are arranged at the four corners of the facing surface of the semiconductor device with respect to the mounting substrate, each of the facing surfaces of the semiconductor device is melted when the outer constituent parts of the four alignment bumps are melted. At the corner, the position of the semiconductor device with respect to the mounting substrate can be aligned. Therefore, the connection terminal can be opposed to the land with higher accuracy. As a result, the connection terminal can be more reliably connected to the land, and better surface mounting on the mounting substrate of the semiconductor device can be achieved.

また、半導体装置の対向面の四隅にアライメント用バンプが配置されているので、温度変化に伴って、半導体装置と実装基板との間に熱膨張差が生じても、その熱膨張差による応力を各アライメント用バンプで吸収することができる。そのため、４つのアライメント用バンプよりも内方に配置された接続端子に加わる応力を軽減することができる。   In addition, since the alignment bumps are arranged at the four corners of the opposing surface of the semiconductor device, even if a thermal expansion difference occurs between the semiconductor device and the mounting substrate due to a temperature change, the stress due to the thermal expansion difference is applied. It can be absorbed by each alignment bump. Therefore, it is possible to reduce the stress applied to the connection terminals arranged inward than the four alignment bumps.

以下では、この発明の実施の形態を、添付図面を参照して詳細に説明する。
図１は、この発明の一実施形態にかかる半導体装置１の構成を図解的に示す側面図である。また、図２は、図１に示す半導体装置１の図解的な平面図（実装基板４との対向面１ａの構成を示す図）である。
この半導体装置１は、ＢＧＡ（Ball Grid Array）が採用された半導体装置であって、矩形板状に形成されている。半導体装置１の内部には、半導体チップ（図示せず）が内蔵されており、実装基板４と対向する半導体装置１の一方面１ａには、複数の接続端子２と、複数のアライメント用バンプ３とが形成されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a side view schematically showing the configuration of a semiconductor device 1 according to an embodiment of the present invention. 2 is a schematic plan view of the semiconductor device 1 shown in FIG. 1 (a diagram showing a configuration of the facing surface 1a facing the mounting substrate 4).
The semiconductor device 1 is a semiconductor device employing a BGA (Ball Grid Array), and is formed in a rectangular plate shape. A semiconductor chip (not shown) is built in the semiconductor device 1, and a plurality of connection terminals 2 and a plurality of alignment bumps 3 are provided on one surface 1 a of the semiconductor device 1 facing the mounting substrate 4. And are formed.

複数の接続端子２は、半導体装置１の一方面１ａの中央部に、格子状（この実施形態では、３行×３列の行列状）に配列されている。各接続端子２は、ボール状に形成されている。また、各接続端子２は、半導体装置１に内蔵された半導体チップと電気的に接続されている。
複数のアライメント用バンプ３は、半導体装置１の一方面１ａの四隅に配置されている。各アライメント用バンプ３は、接続端子２よりも大きな径を有するボール状に形成されている。より具体的には、各アライメント用バンプ３は、接続端子２と同じ材料を用いて、接続端子２とほぼ同じ径を有するボール状に形成された内側構成部３１と、内側構成部３１を形成する金属材料よりも低い融点を有するはんだ材料を用いて形成され、内側構成部３１の表面を被覆する外側構成部３２とを備えている。 The plurality of connection terminals 2 are arranged in a lattice shape (in this embodiment, a matrix of 3 rows × 3 columns) at the center of the one surface 1a of the semiconductor device 1. Each connection terminal 2 is formed in a ball shape. Each connection terminal 2 is electrically connected to a semiconductor chip built in the semiconductor device 1.
The plurality of alignment bumps 3 are arranged at the four corners of the one surface 1 a of the semiconductor device 1. Each alignment bump 3 is formed in a ball shape having a diameter larger than that of the connection terminal 2. More specifically, each alignment bump 3 uses the same material as the connection terminal 2 to form an inner component 31 and an inner component 31 formed in a ball shape having substantially the same diameter as the connection terminal 2. And an outer constituent part 32 that covers the surface of the inner constituent part 31 and is formed using a solder material having a melting point lower than that of the metal material.

接続端子２およびアライメント用バンプ３の内側構成部３１の材料としては、高融点はんだ材料（たとえば、Ｓｎ−Ａｇ−Ｃｕ系のはんだ）が用いられる。一方、アライメント用バンプ３の外側構成部３２の材料としては、接続端子２およびアライメント用バンプ３の内側構成部３１の材料よりも低い融点を有する低融点はんだ材料（たとえば、Ｓｎ−Ｚｎ系のはんだ）が用いられる。   A high melting point solder material (for example, Sn—Ag—Cu based solder) is used as the material of the inner terminal portion 31 of the connection terminal 2 and the alignment bump 3. On the other hand, the material of the outer component 32 of the alignment bump 3 is a low melting point solder material having a lower melting point than the material of the connection terminal 2 and the inner component 31 of the alignment bump 3 (for example, Sn—Zn solder). ) Is used.

半導体装置１は、接続端子２およびアライメント用バンプ３の配置された一方面１ａを対向させて実装基板４（プリント配線基板）に表面実装される。実装基板４には、複数の薄板状のランド５と、複数の薄板状のアライメント用パッド６とが設けられている。
複数のランド５は、半導体装置１の接続端子２の配列に対応する格子状に配置されている。半導体装置１と実装基板４とを位置合わせして、半導体装置１の各接続端子２と実装基板４上の各ランド５とを対向させることができ、各接続端子２が各ランド５と接続されることにより、半導体装置１内の半導体チップと実装基板４上の配線との電気的な接続が達成される。 The semiconductor device 1 is surface-mounted on a mounting substrate 4 (printed wiring substrate) with the one surface 1a on which the connection terminals 2 and the alignment bumps 3 are disposed facing each other. The mounting substrate 4 is provided with a plurality of thin plate-like lands 5 and a plurality of thin plate-like alignment pads 6.
The plurality of lands 5 are arranged in a lattice shape corresponding to the arrangement of the connection terminals 2 of the semiconductor device 1. The semiconductor device 1 and the mounting substrate 4 can be aligned so that each connection terminal 2 of the semiconductor device 1 and each land 5 on the mounting substrate 4 can face each other, and each connection terminal 2 is connected to each land 5. Thus, electrical connection between the semiconductor chip in the semiconductor device 1 and the wiring on the mounting substrate 4 is achieved.

複数のアライメント用パッド６は、半導体装置１の各接続端子２が実装基板４上の各ランド５と対向した状態で、半導体装置１の各アライメント用バンプ３と対向する位置に配置されている。
図３は、半導体装置１と実装基板４との接続の過程を図解的に示す側面図（ａ）〜（ｄ）である。 The plurality of alignment pads 6 are disposed at positions facing the alignment bumps 3 of the semiconductor device 1 in a state where the connection terminals 2 of the semiconductor device 1 face the lands 5 on the mounting substrate 4.
FIG. 3 is a side view (a) to (d) schematically showing the process of connection between the semiconductor device 1 and the mounting substrate 4.

半導体装置１の実装基板４への実装に際しては、まず、半導体装置１の一方面１ａを実装基板４に対向させて、アライメント用バンプ３が実装基板４上のアライメント用パッド６と対向するように、その半導体装置１と実装基板４とを位置合わせする。その後、半導体装置１を実装基板４に近接させる（図３（ａ）参照）。アライメント用バンプ３は、接続端子２よりも大きな径を有するので、半導体装置１を実装基板４に近接させると、アライメント用バンプ３がアライメント用パッド６に当接し、半導体装置１がアライメント用バンプ３によって実装基板４上に支持された状態となる。このとき、各接続端子２は、実装基板４上のランド５から離間している。   When mounting the semiconductor device 1 on the mounting substrate 4, first, the one surface 1 a of the semiconductor device 1 is opposed to the mounting substrate 4, and the alignment bumps 3 are opposed to the alignment pads 6 on the mounting substrate 4. The semiconductor device 1 and the mounting substrate 4 are aligned. Thereafter, the semiconductor device 1 is brought close to the mounting substrate 4 (see FIG. 3A). Since the alignment bump 3 has a diameter larger than that of the connection terminal 2, when the semiconductor device 1 is brought close to the mounting substrate 4, the alignment bump 3 comes into contact with the alignment pad 6, and the semiconductor device 1 is aligned with the alignment bump 3. As a result, it is supported on the mounting substrate 4. At this time, each connection terminal 2 is separated from the land 5 on the mounting substrate 4.

次に、半導体装置１がアライメント用バンプ３によって実装基板４上に支持された状態でリフローが行われる。アライメント用バンプ３の外側構成部３２は、接続端子２の材料よりも低い融点を有する低融点はんだ材料からなるので、接続端子２が溶融し始めるよりも先に、アライメント用バンプ３の外側構成部３２が溶融する（図３（ｂ）参照）。
外側構成部３２が溶融すると、溶融したはんだ材料がアライメント用パッド６上に拡がり、その表面張力によって、実装基板４上の半導体装置１が、実装基板４を垂直に見下ろす平面視において、アライメント用バンプ３の中心とアライメント用パッド６の中心とが一致する位置にアライメントされる（図３の（ｃ）参照）。そして、外側構成部３２の溶融に伴って、半導体装置１がアライメントされつつ実装基板４に近接し、外側構成部３２が完全に溶融すると、内側構成部３１が実装基板４上のアライメント用パッド６に当接するとともに、接続端子２が実装基板４上のランド５に当接し、半導体装置１が実装基板４に対して平行な姿勢で支えられる。 Next, reflow is performed in a state where the semiconductor device 1 is supported on the mounting substrate 4 by the alignment bumps 3. Since the outer component 32 of the alignment bump 3 is made of a low melting point solder material having a lower melting point than the material of the connection terminal 2, the outer component of the alignment bump 3 before the connection terminal 2 starts to melt. 32 melts (see FIG. 3B).
When the outer component 32 is melted, the melted solder material spreads on the alignment pad 6, and the surface tension causes the semiconductor device 1 on the mounting substrate 4 to have an alignment bump in a plan view in which the mounting substrate 4 is looked down vertically. 3 and the center of the alignment pad 6 are aligned (see FIG. 3C). As the outer component 32 is melted, the semiconductor device 1 approaches the mounting substrate 4 while being aligned, and when the outer component 32 is completely melted, the inner component 31 is aligned with the alignment pad 6 on the mounting substrate 4. In addition, the connection terminal 2 contacts the land 5 on the mounting substrate 4, and the semiconductor device 1 is supported in a posture parallel to the mounting substrate 4.

その後、リフローがさらに進み、半導体装置１の周囲の温度が接続端子２および内側構成部３１の材料である高融点はんだ材料の融点以上になると、接続端子２と内側構成部３１とが溶融しはじめる。接続端子２と内側構成部３１とは、同じ材料で形成されているので、同様に溶融する。これにより、半導体装置１が実装基板４に対して、平行な姿勢を保ったまま、接続端子２と内側構成部３１とが接合され、リフローが達成される（図３（ｄ）参照）。   Thereafter, the reflow further proceeds, and when the temperature around the semiconductor device 1 becomes equal to or higher than the melting point of the high melting point solder material that is the material of the connection terminal 2 and the inner component 31, the connection terminal 2 and the inner component 31 begin to melt. . Since the connection terminal 2 and the inner side component 31 are formed of the same material, they are similarly melted. Thereby, the connection terminal 2 and the inner component part 31 are joined while the semiconductor device 1 is maintained in a parallel posture with respect to the mounting substrate 4, and reflow is achieved (see FIG. 3D).

以上のように、リフローにおいて、アライメント用バンプ３の外側構成部３２が溶融することにより、実装基板４に対する半導体装置１の位置がアライメントされる。そのため、アライメント用バンプ３がアライメント用パッド６に当接された時点で、平面視において各接続端子２の位置が各ランド５の位置に対してずれていても、リフロー時に、その位置ずれを修正することができる。その結果、各接続端子２を各ランド５に対して確実に接続させることができ、半導体装置１の実装基板４に対する良好な表面実装を達成することができる。   As described above, the position of the semiconductor device 1 with respect to the mounting substrate 4 is aligned by melting the outer constituent portion 32 of the alignment bump 3 in the reflow. Therefore, even if the position of each connection terminal 2 is shifted from the position of each land 5 in a plan view when the alignment bump 3 is brought into contact with the alignment pad 6, the position shift is corrected at the time of reflow. can do. As a result, each connection terminal 2 can be reliably connected to each land 5, and good surface mounting on the mounting substrate 4 of the semiconductor device 1 can be achieved.

また、アライメント用バンプ３の内側構成部３１は、接続端子２と同じ金属材料を用いられ、ほぼ同じ径を有するボール状に形成されているので、接続端子２と同一工程で作成することができる。内側構成部３１と接続端子２とを同一工程で作成することにより、半導体装置１の製造工程数を削減することができる。
さらに、アライメント用バンプ３が半導体装置１の実装基板４に対する対向面１ａの四隅に配置されている。これにより、その４つのアライメント用バンプ３の外側構成部３２が溶融したときに、溶融したはんだの表面張力により、半導体装置１の対向面１ａの各隅部分において、半導体装置１の実装基板４に対する位置をアライメントすることができる。そのため、接続端子２をより精度よくランド５に対向させることができる。その結果、接続端子２をランド５に対してより確実に接続させることができ、半導体装置１の実装基板４に対する一層良好な表面実装を達成することができる。 Further, since the inner component 31 of the alignment bump 3 is made of the same metal material as that of the connection terminal 2 and is formed in a ball shape having substantially the same diameter, it can be formed in the same process as the connection terminal 2. . The number of manufacturing steps of the semiconductor device 1 can be reduced by forming the inner constituent part 31 and the connection terminal 2 in the same process.
Further, the alignment bumps 3 are arranged at the four corners of the facing surface 1 a of the semiconductor device 1 with respect to the mounting substrate 4. As a result, when the outer constituent portions 32 of the four alignment bumps 3 are melted, the surface tension of the melted solder causes the corners of the facing surface 1a of the semiconductor device 1 to face the mounting substrate 4 of the semiconductor device 1. The position can be aligned. Therefore, the connection terminal 2 can be opposed to the land 5 with higher accuracy. As a result, the connection terminal 2 can be more reliably connected to the land 5, and better surface mounting on the mounting substrate 4 of the semiconductor device 1 can be achieved.

また、半導体装置１の対向面１ａの四隅にアライメント用バンプ３が配置されているので、温度変化に伴って、半導体装置１と実装基板４との間に熱膨張差が生じても、その熱膨張差による応力をアライメント用バンプ３で吸収することができる。そのため、アライメント用バンプ３よりも内方に配置された接続端子２に加わる応力を軽減することができる。   In addition, since the alignment bumps 3 are arranged at the four corners of the opposing surface 1a of the semiconductor device 1, even if a difference in thermal expansion occurs between the semiconductor device 1 and the mounting substrate 4 due to temperature change, The stress due to the expansion difference can be absorbed by the alignment bump 3. Therefore, it is possible to reduce the stress applied to the connection terminal 2 disposed inward of the alignment bump 3.

なお、アライメント用バンプ３の内側構成部３１と外側構成部３２とを、同じ材料を用いて形成することも考えられる。しかし、その場合、リフローにおいて、アライメント用バンプ３が溶けすぎて、半導体装置１と実装基板４とに傾きが生じ、その結果、一部の接続端子２がランド５と接続されないという不具合を生じるおそれがある。これに対し、この半導体装置１では、アライメント用バンプ３が融点の違う材料で形成された内側構成部３１と外側構成部３２とからなるので、リフローの過程で、外側構成部３２のみを先に溶融させることができ、半導体装置１を実装基板４に対して、平行な姿勢を保ったまま近接させることができる。   It is also conceivable to form the inner component 31 and the outer component 32 of the alignment bump 3 using the same material. However, in that case, in reflow, the alignment bump 3 is melted too much, and the semiconductor device 1 and the mounting substrate 4 are inclined. As a result, there is a possibility that a part of the connection terminals 2 is not connected to the land 5. There is. On the other hand, in this semiconductor device 1, since the alignment bump 3 is composed of the inner component part 31 and the outer component part 32 formed of materials having different melting points, only the outer component part 32 is first in the reflow process. The semiconductor device 1 can be brought close to the mounting substrate 4 while maintaining a parallel posture.

以上、この発明の一実施形態について説明したが、この発明は他の形態で実施することもできる。上記の実施形態では、アライメント用バンプ３を四隅に配置したが、図４に示すように互いに対角をなす２つの隅に配置してもよい。
また、上記の実施形態では、ＢＧＡが採用された半導体装置を例にとったが、この発明は、ＢＧＡに限らず、ＬＧＡ（Land Grid Array）やＷＬ−ＣＳＰ（Wafer Level-Chip Size Package）などの他の種類の表面実装型パッケージが採用された半導体装置に適用することができる。 As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form. In the above embodiment, the alignment bumps 3 are arranged at the four corners, but they may be arranged at two corners that are diagonal to each other as shown in FIG.
In the above embodiment, the semiconductor device adopting the BGA is taken as an example. However, the present invention is not limited to the BGA, but is an LGA (Land Grid Array), a WL-CSP (Wafer Level-Chip Size Package), or the like. The present invention can be applied to a semiconductor device employing another type of surface mount package.

その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。   In addition, various design changes can be made within the scope of matters described in the claims.

この発明の一実施形態にかかる半導体装置の構成を図解的に示す側面図である。1 is a side view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention. 図１に示す半導体装置の図解的な平面図（実装基板との対向面の構成を示す図）である。FIG. 2 is a schematic plan view of the semiconductor device illustrated in FIG. 1 (a diagram illustrating a configuration of a surface facing a mounting substrate). 半導体装置と実装基板との接続の過程を図解的に示す側面図（ａ）〜（ｄ）である。It is side view (a)-(d) which shows the process of the connection of a semiconductor device and a mounting board | substrate schematically. この発明の他の実施形態（２個のアライメント用バンプを有する態様）にかかる半導体装置の構成を示す図解的な平面図である。It is an illustration top view showing the composition of the semiconductor device concerning other embodiments (mode which has two bumps for alignment) of this invention.

符号の説明Explanation of symbols

１，１０ 半導体装置
１ａ 一方面（半導体装置の実装基板に対する対向面）
２ 接続端子
３ アライメント用バンプ
３１ 内部構成部
３２ 外側構成部
４ 実装基板
５ ランド
６ アライメント用パッド 1,10 Semiconductor device 1a One surface (opposite surface to mounting substrate of semiconductor device)
2 Connection terminal 3 Bump for alignment 31 Internal component 32 External component 4 Mounting board 5 Land 6 Alignment pad

Claims (2)

実装基板に表面実装される半導体装置であって、
前記実装基板との対向面上に、金属材料を用いてボール状に形成され、前記実装基板上のランドと電気接続される接続端子と、
前記対向面上に、前記接続端子よりも大きな径を有するボール状に形成され、前記実装基板上のアライメント用パッドに当接されるアライメント用バンプとを含み、
前記アライメント用バンプは、
前記接続端子と同じ金属材料を用いて、前記接続端子とほぼ同じ径を有するボール状に形成された内側構成部と、
前記内側構成部を形成する金属材料よりも低い融点を有するはんだ材料を用いて形成され、前記内側構成部の表面を被覆する外側構成部とを備えていることを特徴とする、半導体装置。 A semiconductor device that is surface-mounted on a mounting board,
A connection terminal that is formed in a ball shape using a metal material on a surface facing the mounting substrate, and is electrically connected to a land on the mounting substrate,
An alignment bump formed on the opposing surface in a ball shape having a diameter larger than that of the connection terminal, and abutting against an alignment pad on the mounting substrate;
The alignment bump is
Using the same metal material as the connection terminal, an inner component formed in a ball shape having substantially the same diameter as the connection terminal,
A semiconductor device comprising: an outer constituent part formed of a solder material having a melting point lower than that of the metal material forming the inner constituent part, and covering a surface of the inner constituent part. 前記対向面は、矩形状に形成されており、
前記アライメント用バンプは、前記対向面の四隅に配置されていることを特徴とする、請求項１記載の半導体装置。 The facing surface is formed in a rectangular shape,
The semiconductor device according to claim 1, wherein the alignment bumps are arranged at four corners of the facing surface.
JP2005210380A 2005-07-20 2005-07-20 Semiconductor device Pending JP2007027576A (en)

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