[go: up one dir, main page]

JP2007142345A - Nitride semiconductor light-emitting element - Google Patents

Nitride semiconductor light-emitting element Download PDF

Info

Publication number
JP2007142345A
JP2007142345A JP2005337806A JP2005337806A JP2007142345A JP 2007142345 A JP2007142345 A JP 2007142345A JP 2005337806 A JP2005337806 A JP 2005337806A JP 2005337806 A JP2005337806 A JP 2005337806A JP 2007142345 A JP2007142345 A JP 2007142345A
Authority
JP
Japan
Prior art keywords
nitride semiconductor
layer
substrate
metal film
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005337806A
Other languages
Japanese (ja)
Inventor
Yukio Shakuda
幸男 尺田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2005337806A priority Critical patent/JP2007142345A/en
Priority to TW095143057A priority patent/TW200735418A/en
Priority to PCT/JP2006/323176 priority patent/WO2007060931A1/en
Priority to US12/085,327 priority patent/US7977703B2/en
Publication of JP2007142345A publication Critical patent/JP2007142345A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor light-emitting element having high light-emitting efficiency which can manufacture a vertical element forming a pair of electrodes on the top and bottom of a chip by employing a semiconductor substrate, prevents optical absorption on the substrate while maintaining high heat conductivity and reduces the dislocation density of a nitride semiconductor to be grown thereon. <P>SOLUTION: A first nitride semiconductor layer 2 is formed on the semiconductor substrate 1, a mask 5 having an opening is provided thereon, and a semiconductor stacking section 10 is provided by stacking nitride semiconductor layers so that a second nitride semiconductor layer 6 selectively grown in the lateral direction of the opening on the mask section 5 may be formed and a light-emitting layer 8 may be formed thereon. The mask section 5 is composed of a metal film 3 formed on the first nitride semiconductor layer side, and a dielectric film 4 formed on the metal film 3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は窒化物半導体を用いた発光ダイオード(LED)やレーザダイオード(LD)などの半導体発光素子に関する。さらに詳しくは、発光層での光を吸収する半導体基板を用いた場合であっても、結晶性が優れ、かつ、外部量子効率が優れた窒化物半導体発光素子に関する。   The present invention relates to a semiconductor light emitting device such as a light emitting diode (LED) or a laser diode (LD) using a nitride semiconductor. More specifically, the present invention relates to a nitride semiconductor light emitting device that has excellent crystallinity and excellent external quantum efficiency even when a semiconductor substrate that absorbs light in the light emitting layer is used.

近年、窒化物半導体を用いた青色系発光ダイオード(LED)やレーザダイオード(LD)などの窒化物半導体発光素子が実用化されている。この窒化物半導体を用いた青色系の光を発光するLEDは、たとえば図4(a)に示されるように、サファイア基板41上に、MOCVD法によりGaNなどからなる低温バッファ層42、GaNなどからなるn形層43と、バンドギャップエネルギーがn形層43のそれよりも小さく発光波長を定める材料、たとえばInGaN系(InとGaの比率が種々変り得ることを意味する、以下同じ)化合物半導体からなる活性層(発光層)44と、GaNなどからなるp形層45とが積層されて半導体積層部46が形成され、その表面に透光性導電層47を介して、p側電極48が設けられ、積層された半導体積層部46の一部がエッチングされて露出したn形層43の表面にn側電極49が設けられることにより形成されている(たとえば特許文献1参照)。   In recent years, nitride semiconductor light emitting devices such as blue light emitting diodes (LEDs) and laser diodes (LDs) using nitride semiconductors have been put into practical use. For example, as shown in FIG. 4A, an LED emitting blue light using a nitride semiconductor is formed on a sapphire substrate 41 from a low-temperature buffer layer 42 made of GaN or the like by MOCVD, and from GaN or the like. An n-type layer 43 and a material whose band gap energy is smaller than that of the n-type layer 43 and defines an emission wavelength, for example, an InGaN-based compound semiconductor (which means that the ratio of In and Ga can be changed variously, the same applies hereinafter). An active layer (light emitting layer) 44 and a p-type layer 45 made of GaN or the like are laminated to form a semiconductor laminated portion 46, and a p-side electrode 48 is provided on the surface of the semiconductor laminated portion 46 via a translucent conductive layer 47. The n-side electrode 49 is formed on the surface of the n-type layer 43 exposed by etching a part of the laminated semiconductor laminated portion 46 (for example, a special feature) References 1).

しかし、サファイア基板41は絶縁性基板であり、基板に直接電極を形成できず、前述のように半導体積層部46の一部をエッチングなどの処理を行うことによりメサ構造としなければならない。また、サファイア基板41は、従来赤色系や赤外系半導体発光素子の導電性基板として用いられているGaAs、GaP、Siなどの基板や、青色系半導体発光素子の導電性基板として用いられているSiC基板などに比べて熱伝導性が悪い。そこで、サファイア基板に代りこれらの半導体基板を用いて、窒化物半導体発光素子を形成する構造が考えられる。   However, the sapphire substrate 41 is an insulating substrate, and electrodes cannot be directly formed on the substrate, and a mesa structure must be formed by performing a process such as etching on a part of the semiconductor stacked portion 46 as described above. Further, the sapphire substrate 41 is used as a conductive substrate for GaAs, GaP, Si, etc., which is conventionally used as a conductive substrate for red and infrared semiconductor light emitting devices, and as a conductive substrate for blue semiconductor light emitting devices. Thermal conductivity is poor compared to SiC substrates. Therefore, a structure in which a nitride semiconductor light emitting element is formed using these semiconductor substrates instead of the sapphire substrate is conceivable.

具体的には、図4(b)に示されるように、たとえばSi基板61上に、MOCVD法によりAlGaN系化合物などからなるバッファ層62、GaNなどからなるn形層63と、InGaN系化合物半導体からなる活性層(発光層)64と、GaNなどからなるp形層65とが積層されて半導体積層部66が形成され、その表面に透光性導電層67を介して、p側電極68が設けられ、Si基板61の裏面に直接n側電極69が設けられることにより形成されている。なお、n形層およびp形層はキャリアの閉じ込め効果を向上させるため、活性層側にAlGaN系(AlとGaの比率が種々変り得ることを意味する、以下同じ)化合物などのさらにバンドギャップエネルギーの大きい半導体層が用いられることがある。
特開平10−173222号公報(図1参照)
Specifically, as shown in FIG. 4B, for example, on a Si substrate 61, a buffer layer 62 made of an AlGaN compound or the like by an MOCVD method, an n-type layer 63 made of GaN or the like, and an InGaN compound semiconductor. An active layer (light-emitting layer) 64 made of GaN and a p-type layer 65 made of GaN or the like are laminated to form a semiconductor laminated portion 66, and a p-side electrode 68 is formed on the surface of the p-type electrode 68 via a translucent conductive layer 67. The n-side electrode 69 is provided directly on the back surface of the Si substrate 61. Note that the n-type layer and the p-type layer improve the carrier confinement effect, and therefore further increase the band gap energy such as an AlGaN-based compound (meaning that the ratio of Al and Ga can be variously changed, the same applies hereinafter) on the active layer side. A large semiconductor layer may be used.
Japanese Patent Laid-Open No. 10-173222 (see FIG. 1)

前述のように、サファイアに代えてGaAs、GaP、Si、SiCなどからなる基板上に直接窒化物半導体発光素子を形成することで、チップの上下に一対の電極を形成する垂直型の素子を作製でき、また、サファイア基板よりも熱伝導率が大きいため、高温高出力下での発光効率を向上させることが可能である。   As described above, by forming a nitride semiconductor light-emitting element directly on a substrate made of GaAs, GaP, Si, SiC, or the like instead of sapphire, a vertical element that forms a pair of electrodes above and below the chip is manufactured. In addition, since the thermal conductivity is larger than that of the sapphire substrate, it is possible to improve the light emission efficiency under high temperature and high output.

しかし、窒化物半導体発光素子の発光波長は、黄色から紫外領域であり、半導体積層部の発光層で発生した光が基板方向に伝播して基板へ到達すると、上述の基板を用いている場合、基板で光吸収を起こしてしまい、光取出し効率の優れた発光素子を形成することができないという問題がある。また、これらの基板を用いても、その上に積層される窒化物半導体層との格子定数の差は大きく、基板上の窒化物半導体層の転位密度が大きく、発光効率を向上できないという問題もある。   However, the emission wavelength of the nitride semiconductor light emitting device is in the yellow to ultraviolet region, and when the light generated in the light emitting layer of the semiconductor stacked portion propagates in the direction of the substrate and reaches the substrate, when the above-described substrate is used, There is a problem in that light absorption occurs in the substrate, and a light-emitting element with excellent light extraction efficiency cannot be formed. In addition, even when these substrates are used, there is a problem that the difference in lattice constant from the nitride semiconductor layer laminated thereon is large, the dislocation density of the nitride semiconductor layer on the substrate is large, and the light emission efficiency cannot be improved. is there.

一方、たとえばSi基板上にWなどの金属を蒸着してシリサイド基板にすることで、基板での光吸収を防ぐことが考えられる。しかし、このような場合でもシリサイド部分での反射率があまり高くならず、基板側へ光が透過し、結局基板で光吸収を生じ光取出し効率を高くすることができない。また、Wを用いてシリサイド基板としても、MOCVD成長の際、その上に積層するGaN系化合物の原材料であるアンモニアガスと反応し、シリサイドとAlGaN系化合物層との界面に不純物層が形成され、その上に積層される発光層の結晶性が悪化してしまい、発光効率が低下してしまうという問題もある。   On the other hand, for example, it is conceivable to prevent light absorption by the substrate by evaporating a metal such as W on a Si substrate to form a silicide substrate. However, even in such a case, the reflectance at the silicide portion is not so high, light is transmitted to the substrate side, and eventually light absorption occurs at the substrate, so that the light extraction efficiency cannot be increased. Further, even when a silicide substrate using W is grown by MOCVD, it reacts with ammonia gas, which is a raw material of the GaN-based compound laminated thereon, and an impurity layer is formed at the interface between the silicide and the AlGaN-based compound layer, There is also a problem that the crystallinity of the light emitting layer laminated thereon deteriorates and the light emission efficiency decreases.

本発明はこのような問題を解決するためになされたもので、半導体基板を用いることでチップの上下に一対の電極を形成する垂直型の素子を作製でき、かつ、高い熱伝導性を維持しながら、基板での光吸収を防止すると共に、その上に成長される窒化物半導体の転位密度を低減し、発光効率の高い窒化物半導体発光素子を提供することを目的とする。   The present invention has been made to solve such a problem, and by using a semiconductor substrate, a vertical element that forms a pair of electrodes on the top and bottom of a chip can be manufactured, and high thermal conductivity can be maintained. However, an object of the present invention is to provide a nitride semiconductor light emitting device having high luminous efficiency by preventing light absorption by the substrate and reducing the dislocation density of the nitride semiconductor grown thereon.

本発明による窒化物半導体発光素子は、半導体基板と、該半導体基板上に設けられる第1の窒化物半導体層と、該第1の窒化物半導体層上に設けられ、開口部を有するマスク部と、該マスク部上に前記開口部から横方向に選択成長される第2の窒化物半導体層と、該第2の窒化物半導体層上に発光層を形成するように窒化物半導体層が積層される半導体積層部とからなり、前記マスク部が、前記第1の窒化物半導体層側に設けられる金属膜と、該金属膜上に設けられる絶縁膜とからなる。   A nitride semiconductor light emitting device according to the present invention includes a semiconductor substrate, a first nitride semiconductor layer provided on the semiconductor substrate, and a mask portion provided on the first nitride semiconductor layer and having an opening. A second nitride semiconductor layer selectively grown laterally from the opening on the mask portion, and a nitride semiconductor layer stacked on the second nitride semiconductor layer to form a light emitting layer. The mask portion is composed of a metal film provided on the first nitride semiconductor layer side and an insulating film provided on the metal film.

なお、窒化物半導体とは、III族元素のGaとV族元素のNとの化合物またはIII族元素のGaの一部または全部がAl、Inなどの他のIII 族元素と置換したものおよび/またはV族元素のNの一部がP、Asなどの他のV族元素と置換した化合物(窒化物)からなる半導体をいい、GaN系化合物ともいう。   A nitride semiconductor is a compound in which a group III element Ga and a group V element N or a part or all of a group III element Ga is replaced with another group III element such as Al and In, and / or Alternatively, it refers to a semiconductor made of a compound (nitride) in which a part of N of the group V element is substituted with another group V element such as P or As, and is also referred to as a GaN compound.

また、前記金属膜が、前記第1の窒化物半導体層側に設けられる第1の金属膜および該第1の金属膜上に設けられる第2の金属膜の少なくとも2層構造からなり、前記第1の金属膜が前記半導体積層部の成長温度よりも高い融点を有する金属からなり、第2の金属膜が前記発光層で発生した光を反射する金属からなることが好ましい。   The metal film has at least a two-layer structure of a first metal film provided on the first nitride semiconductor layer side and a second metal film provided on the first metal film, Preferably, the first metal film is made of a metal having a melting point higher than the growth temperature of the semiconductor stacked portion, and the second metal film is made of a metal that reflects light generated in the light emitting layer.

具体的には、前記第1の金属膜が、W、TiおよびPdの少なくとも1種からなり、前記第2の金属膜が、Al、AgおよびAuの少なくとも1種からなるものを使用することができる。   Specifically, the first metal film is made of at least one of W, Ti and Pd, and the second metal film is made of at least one of Al, Ag and Au. it can.

本発明の窒化物半導体発光素子によれば、基板にGaAs、GaP、SiC、Siなど、青色や紫外光を吸収する半導体基板を用いた場合であっても、絶縁膜の下部に光を反射しやすい金属膜が形成されているため、この金属膜により、発光層で発生した光を反射し、基板へ光が到達することを防ぎ、基板での光吸収をなくして、光の取出し効率を高くすることができる半導体発光素子が得られる。また、格子不整合から生じる転位密度が増加することに対しては、開口部を有するマスクを用い、開口部から露出する第1の窒化物半導体層をシードとして横方向選択成長により第2の窒化物半導体層を成長しているため、貫通転位はマスクで阻止されて、転位の少ない結晶性の優れた層が得られる。その結果、その上に積層される発光層においても転位が少なくなり、格子不整合の問題を解消し、従来よりも転位密度の小さい高品質な発光層を形成できる。さらに、基板が半導体基板であるため、ドーピングにより導電性基板とすることができ、LEDを作製する際、メサ構造とする必要がなく、チップの上下に一対の電極を形成する垂直型の素子を作製でき、また、熱伝導率もサファイアに比べ大きいため、高温高出力まで熱飽和することなく発光効率の高い半導体発光素子が得られる。   According to the nitride semiconductor light emitting device of the present invention, even when a semiconductor substrate that absorbs blue or ultraviolet light, such as GaAs, GaP, SiC, or Si, is used as the substrate, the light is reflected below the insulating film. Since an easy-to-use metal film is formed, this metal film reflects light generated in the light emitting layer, prevents light from reaching the substrate, eliminates light absorption by the substrate, and increases light extraction efficiency. A semiconductor light emitting device that can be obtained is obtained. Further, for increasing the dislocation density resulting from lattice mismatch, a mask having an opening is used, and the second nitride is formed by lateral selective growth using the first nitride semiconductor layer exposed from the opening as a seed. Since the physical semiconductor layer is grown, threading dislocations are blocked by a mask, and a layer having excellent crystallinity with few dislocations can be obtained. As a result, dislocations are reduced in the light emitting layer laminated thereon, the problem of lattice mismatch is solved, and a high quality light emitting layer having a lower dislocation density than that of the prior art can be formed. Further, since the substrate is a semiconductor substrate, a conductive substrate can be formed by doping, and when manufacturing an LED, a mesa structure is not necessary, and a vertical element that forms a pair of electrodes on the top and bottom of a chip is provided. Since it can be manufactured and has a higher thermal conductivity than sapphire, a semiconductor light emitting device with high luminous efficiency can be obtained without thermal saturation to high temperature and high output.

また、金属膜を2層構造とし、第1の金属膜が発光層で発生した光を反射する金属、第2金属膜が半導体積層部の成長温度よりも高い融点を有する金属を用いることにより、第1の金属膜の金属が半導体層に拡散することを防止することができ、素子特性を低下させることがなく、基板での光吸収を十分に防止でき、より発光効率の高い半導体発光素子が得られる。   In addition, by using a metal film having a two-layer structure, the first metal film reflects the light generated in the light emitting layer, and the second metal film uses a metal having a melting point higher than the growth temperature of the semiconductor stacked portion, The metal of the first metal film can be prevented from diffusing into the semiconductor layer, the device characteristics can be prevented from being deteriorated, light absorption at the substrate can be sufficiently prevented, and a semiconductor light emitting device with higher luminous efficiency can be obtained. can get.

つぎに、図面を参照しながら本発明の窒化物半導体発光素子について説明をする。本発明による窒化物半導体発光素子は、図1に一実施形態である窒化物半導体発光素子(LEDチップ)の断面説明図が示されるように、半導体基板1上に第1の窒化物半導体層2が設けられ、その上に開口部を有するマスク部5が設けられ、そのマスク部5上に開口部から横方向に選択成長される第2の窒化物半導体層6、さらに発光層8を形成するように窒化物半導体層が積層されて半導体積層部10が設けられている。そして、マスク部5は、第1の窒化物半導体層2の側に設けられる金属膜3と、金属膜3上に設けられる誘電体膜4とからなっている。なお、図1を始め、各図で基板の厚さが他の半導体層と比較して小さく書かれているが、実際には各半導体層より遙かに大きい。   Next, the nitride semiconductor light emitting device of the present invention will be described with reference to the drawings. The nitride semiconductor light-emitting device according to the present invention includes a first nitride semiconductor layer 2 on a semiconductor substrate 1 as shown in a cross-sectional explanatory view of a nitride semiconductor light-emitting device (LED chip) according to an embodiment in FIG. A mask portion 5 having an opening is provided thereon, and a second nitride semiconductor layer 6 and a light emitting layer 8 that are selectively grown laterally from the opening are formed on the mask portion 5. As described above, the semiconductor stacked portion 10 is provided by stacking the nitride semiconductor layers. The mask portion 5 includes a metal film 3 provided on the first nitride semiconductor layer 2 side and a dielectric film 4 provided on the metal film 3. In addition, although the thickness of the substrate is written smaller than the other semiconductor layers in each drawing including FIG. 1, it is actually much larger than each semiconductor layer.

すなわち、本発明は、電気伝導性があり基板裏面に電極を形成でき、かつ、熱伝導性の高い半導体基板を用いた上で、基板側に向かって進む光を反射する金属膜3と、横方向選択成長可能な絶縁膜4とでマスク部5を形成することに特徴がある。前述のように、サファイア基板を用いれば、絶縁性基板であるため、基板裏面に電極を形成することができずメサ構造を採用するほかなく、また、サファイア基板の熱伝導率が悪いため、高温高出力動作で熱飽和が生じ発光効率が上がらない。一方、それを防止するために、導電性の基板であるGaAs、GaP、SiC、Siなどの基板を用いれば、ドーピングにより導電性基板とすることができメサ構造を形成する必要はなく、チップの上下に一対の電極を形成する垂直型の素子が作製でき、かつ、熱伝導性が高いため高温動作での発光効率低下は防ぐことができるが、基板と窒化物半導体層間の格子不整合による転位密度が大きくなり、また、基板での光吸収が生じることになり、発光効率が低下するという問題がある。   That is, the present invention uses a metal film 3 that reflects light traveling toward the substrate side, using a semiconductor substrate that is electrically conductive, can form electrodes on the back surface of the substrate, and has high thermal conductivity, The mask portion 5 is formed by the insulating film 4 capable of selective growth. As described above, if a sapphire substrate is used, since it is an insulating substrate, an electrode cannot be formed on the back surface of the substrate, and a mesa structure must be adopted. Also, because the thermal conductivity of the sapphire substrate is poor, High output operation causes thermal saturation and does not increase luminous efficiency. On the other hand, if a conductive substrate such as GaAs, GaP, SiC, or Si is used to prevent this, a conductive substrate can be formed by doping, and there is no need to form a mesa structure. A vertical element that forms a pair of electrodes on the top and bottom can be fabricated, and because of its high thermal conductivity, it is possible to prevent a decrease in light emission efficiency at high temperature operation, but dislocation due to lattice mismatch between the substrate and the nitride semiconductor layer There is a problem that the density is increased and light absorption occurs at the substrate, resulting in a decrease in luminous efficiency.

しかし、本発明によれば、格子不整合による転位密度が大きくなることに対しては、開口部を有するマスク部5を用い、開口部から露出する第1の窒化物半導体層2をシードとした横方向選択成長により、第2の窒化物半導体層6が成長するため、基板側で発生した転位が上層に貫通するのがマスク部5で阻止される。そのため、貫通転位密度が非常に小さくなり、結晶性の高い窒化物半導体層が得られる。したがって、その上に積層される半導体積層部においても転位の少ない層を形成できるため、格子不整合な基板を用いても従来よりも転位密度は低減される。また、基板で生じる光吸収の問題は絶縁膜4の下に金属膜3が形成されているため、この金属膜3により、発光層8で発生して基板1側に進んだ光を反射して基板1への進入を防ぎ、基板1での光吸収を避けることが可能となる。   However, according to the present invention, for increasing the dislocation density due to lattice mismatch, the mask portion 5 having an opening is used, and the first nitride semiconductor layer 2 exposed from the opening is used as a seed. Since the second nitride semiconductor layer 6 is grown by the lateral selective growth, the mask portion 5 prevents dislocations generated on the substrate side from penetrating into the upper layer. Therefore, the threading dislocation density becomes very small, and a nitride semiconductor layer with high crystallinity can be obtained. Therefore, since a layer with few dislocations can be formed also in the semiconductor laminated portion laminated thereon, the dislocation density is reduced as compared with the conventional case even when a lattice mismatched substrate is used. Further, the problem of light absorption that occurs in the substrate is that the metal film 3 is formed under the insulating film 4, and the metal film 3 reflects the light generated in the light emitting layer 8 and traveling to the substrate 1 side. It is possible to prevent entry into the substrate 1 and avoid light absorption by the substrate 1.

半導体基板1は、図1に示される例ではn形のSi基板が用いられているが、Siに限定されず、SiC、GaAs、GaPなどの半導体基板を用いることができる。特に本発明では、青色光や紫外光などの窒化物半導体層で発光する光を吸収する場合にその効果が大きい。半導体基板であるため、ドーピングすることで導電性が得られ、基板の裏面から一方の電極を取り出すことができる。また、上記のどの材料が用いられても、GaNとは格子定数が合わず、格子整合を採ることができないが、前述のようにマスク部5を介して横方向の選択成長をすることにより、マスク部5の上に転位密度の小さい第2の窒化物半導体層6を成長することができる。なお以下の例では、n形基板を例に説明するが、p形基板であってもよい。   The semiconductor substrate 1 is an n-type Si substrate in the example shown in FIG. 1, but is not limited to Si, and a semiconductor substrate such as SiC, GaAs, or GaP can be used. In particular, in the present invention, the effect is great when absorbing light emitted from a nitride semiconductor layer such as blue light or ultraviolet light. Since it is a semiconductor substrate, conductivity is obtained by doping, and one electrode can be taken out from the back surface of the substrate. In addition, no matter which of the above materials is used, the lattice constant does not match with GaN, and lattice matching cannot be taken, but by performing selective growth in the lateral direction through the mask portion 5 as described above, A second nitride semiconductor layer 6 having a low dislocation density can be grown on the mask portion 5. In the following example, an n-type substrate will be described as an example, but a p-type substrate may be used.

第1の窒化物半導体層2は、たとえば3μm程度の厚さで、n形ドープで、たとえば低温成長のAlGaN系化合物層2a、高温成長のGaN層2bをMOCVD法などの通常のエピタキシャル成長法により形成したもので、格子不整合緩和および後述する第2の窒化物半導体層6を横方向選択成長する際のシードとするものである。なお、第1の窒化物半導体層2は、図1に示される例では2層構造であり、AlGaN系化合物層2aは格子不整合緩和層、GaN層2bはシードとする結晶層であるが、これらの層は単層であっても超格子構造であってもよい。また、組成は、使用する基板と上部に積層される半導体層の格子定数の差によって、AlGaN系化合物やGaNのほか、InGaN系化合物など、窒化物半導体層であればよいし、膜厚も必要に応じ適宜設定される。   The first nitride semiconductor layer 2 has a thickness of about 3 μm, for example, and is n-type doped. For example, a low-temperature growth AlGaN-based compound layer 2a and a high-temperature growth GaN layer 2b are formed by a normal epitaxial growth method such as MOCVD. Therefore, it serves as a seed for lattice mismatch relaxation and for the selective growth of the second nitride semiconductor layer 6 to be described later in the lateral direction. In the example shown in FIG. 1, the first nitride semiconductor layer 2 has a two-layer structure. The AlGaN-based compound layer 2a is a lattice mismatch relaxation layer, and the GaN layer 2b is a seed crystal layer. These layers may be a single layer or a superlattice structure. The composition may be a nitride semiconductor layer such as an AlGaN-based compound or GaN, or an InGaN-based compound, depending on the difference in lattice constant between the substrate to be used and the semiconductor layer stacked thereon, and the film thickness is also required. It is set appropriately according to

マスク部5(51)は、図2にその近傍の拡大説明図が示されるように、第1の窒化物半導体層2上に設けられ、幅Wの開口部53を有し、第1の窒化物半導体層2側に設けられる金属膜3と、金属膜3上に設けられる絶縁膜4とからなっている。   The mask portion 5 (51) is provided on the first nitride semiconductor layer 2 and has an opening 53 with a width W, as shown in FIG. The metal film 3 is provided on the physical semiconductor layer 2 side, and the insulating film 4 is provided on the metal film 3.

金属膜3は、たとえば、Al、Ag、Auなどの青色から紫外領域の光に対して反射率の大きい金属が好ましい。また、図2に示されるように、金属膜3が、第1の窒化物半導体層2側に設けられる第1の金属膜3aおよび第1の金属膜3a上に設けられる第2の金属膜3bの少なくとも2層構造からなり、第2の金属膜3bが前述の材料からなり、第1の金属膜3aが半導体積層部10の成長温度よりも高い融点を有する金属からなることにより、第2の金属膜3bの材料が半導体層と合金化することがなく拡散を防止できるため好ましい。第1の金属膜3aとしては、たとえばW、Ti、Pdなどが好ましく用いられる。第1の金属膜3aは10〜200nm程度、第2の金属膜3bは、10〜200nm程度に形成することが最適である。   The metal film 3 is preferably made of a metal having a high reflectance with respect to light in the blue to ultraviolet region, such as Al, Ag, and Au. 2, the metal film 3 includes a first metal film 3a provided on the first nitride semiconductor layer 2 side and a second metal film 3b provided on the first metal film 3a. The second metal film 3b is made of the aforementioned material, and the first metal film 3a is made of a metal having a melting point higher than the growth temperature of the semiconductor stacked portion 10, thereby The material of the metal film 3b is preferable because it can prevent diffusion without being alloyed with the semiconductor layer. For example, W, Ti, Pd or the like is preferably used as the first metal film 3a. It is optimal to form the first metal film 3a to about 10 to 200 nm and the second metal film 3b to about 10 to 200 nm.

絶縁膜4は、たとえばSiO2、Si34などの、その上には直接半導体層をエピタキシャル成長することができない材料が、スパッタリングなどにより、200nm程度の厚さに形成されている。この絶縁膜4は、第1の窒化物半導体層2上に直接第2の窒化物半導体層6が成長しないようにするもので、マスク機能を有する程度に形成されれば、薄いほど段差が生じにくく好ましい。 The insulating film 4 is formed of a material such as SiO 2 or Si 3 N 4 on which a semiconductor layer cannot be directly epitaxially grown to a thickness of about 200 nm by sputtering or the like. The insulating film 4 prevents the second nitride semiconductor layer 6 from growing directly on the first nitride semiconductor layer 2. If the insulating film 4 is formed to have a mask function, a step difference occurs as the thickness decreases. It is difficult and preferable.

この金属膜3および絶縁膜4は、ウェハ状態の第1の窒化物半導体層2上に全面に順次設けられた後に、パターニングされて溝状(図2で紙面と垂直方向に延びる溝)の開口部53が形成される。開口部53を設けるのは、後述するように、開口部53に露出した第1の窒化物半導体層2をシードとして第2の窒化物半導体層6を横方向選択成長させ、第2の窒化物半導体層6の転位密度を小さくするためである。   The metal film 3 and the insulating film 4 are sequentially provided on the entire surface of the first nitride semiconductor layer 2 in a wafer state, and then patterned to form groove-shaped openings (grooves extending in a direction perpendicular to the paper surface in FIG. 2). A portion 53 is formed. As will be described later, the opening 53 is provided by causing the second nitride semiconductor layer 6 to be selectively grown in the lateral direction using the first nitride semiconductor layer 2 exposed in the opening 53 as a seed and the second nitride. This is for reducing the dislocation density of the semiconductor layer 6.

図1に示される半導体発光素子を製造する場合、マスク部の幅M1(図3参照)は横方向選択成長を実現するため、10〜15μm程度に形成されている。マスク部間隔Wは、広すぎると貫通転位密度の大きい縦方向の成長が起こり、転位密度の小さい横方向選択成長が進まず、また、発光層での光を反射する領域を増やすためにも5μm以下であることが好ましい。また、マスク部間隔Wが狭すぎると第1の窒化物半導体層2のシードからの結晶成長の時間がかかるため、2μm以上であることが好ましい。   When the semiconductor light emitting device shown in FIG. 1 is manufactured, the width M1 (see FIG. 3) of the mask portion is formed to be about 10 to 15 μm in order to realize lateral selective growth. If the mask portion interval W is too wide, the vertical growth with a high threading dislocation density occurs, the lateral selective growth with a low dislocation density does not proceed, and 5 μm for increasing the region for reflecting light in the light emitting layer. The following is preferable. Moreover, since it takes time for crystal growth from the seed of the first nitride semiconductor layer 2 if the mask portion interval W is too narrow, it is preferably 2 μm or more.

さらに、図3に素子分離前の断面説明図で示されるように、素子分離を容易にするため、また、ウェハ状態でのSi基板1と窒化物半導体積層部10との熱膨張率差に基づくウェハの反りを防止するため、素子分離領域15に該当するマスク部52だけ広げると、分離領域のマスク幅M2が、素子内部のマスク部51のマスク幅M1よりも広く、マスク部52上に完全には横方向選択成長が起こらず、該マスク部52により、自然に素子分離されることになる。そこで、素子分離領域15の付近のマスク部52の幅M2は、素子中心部のマスク部51のマスク幅M1よりも広くし、具体的には20〜80μm程度とすることが好ましい。このように、分離領域15のマスク部52の幅M2を大きくすることにより、Si基板1と窒化物半導体層間の熱膨張係数差が大きくても、熱膨張率差に基づく応力を吸収することができ、基板の反りなどを防止することができる。また、各素子間を独立させることができ、ウェハからチップ化の作業も容易になる。   Furthermore, as shown in the cross-sectional explanatory diagram before element isolation in FIG. 3, in order to facilitate element isolation, and based on the difference in thermal expansion coefficient between the Si substrate 1 and the nitride semiconductor multilayer portion 10 in the wafer state. If only the mask portion 52 corresponding to the element isolation region 15 is expanded in order to prevent the warpage of the wafer, the mask width M2 of the isolation region is wider than the mask width M1 of the mask portion 51 inside the element, and is completely on the mask portion 52. In this case, no selective growth occurs in the lateral direction, and elements are naturally separated by the mask portion 52. Therefore, the width M2 of the mask portion 52 in the vicinity of the element isolation region 15 is preferably larger than the mask width M1 of the mask portion 51 in the center portion of the element, specifically about 20 to 80 μm. Thus, by increasing the width M2 of the mask portion 52 in the isolation region 15, even if the difference in thermal expansion coefficient between the Si substrate 1 and the nitride semiconductor layer is large, stress based on the difference in thermal expansion coefficient can be absorbed. And warpage of the substrate can be prevented. In addition, each element can be made independent, and the work of forming a chip from the wafer becomes easy.

第2の窒化物半導体層6は、たとえばn形GaN層で5〜10μm程度の厚さに形成される。この半導体層6は、前述のマスク部5の開口部53から露出する第1のGaN層2bをシードとして成長し始め、マスク部5の表面に達すると、横方向に選択成長する。すなわち、GaN層は、縦方向の成長よりも横方向への成長の方が早くしかも結晶性よく成長するため、横方向に成長しながら上方にも僅かに成長し、最終的にはマスク部5の中央部あたりで両方の開口部から横方向に成長してきた半導体層が合致する。そしてマスク部5の表面が完全に埋まった後は上方に成長し、マスク部5上にも完全に第2のn形GaN層(半導体層)6が成長する。この第2のn形GaN層6は、マスク部5上の両端部(開口部53に接する部分)および中央部の合致する部分を除いた部分の結晶性がよく、転位密度も1桁ほど小さくなる。   Second nitride semiconductor layer 6 is, for example, an n-type GaN layer and is formed to a thickness of about 5 to 10 μm. The semiconductor layer 6 begins to grow using the first GaN layer 2b exposed from the opening 53 of the mask portion 5 as a seed, and when the surface reaches the mask portion 5, the semiconductor layer 6 selectively grows in the lateral direction. That is, the GaN layer grows faster in the lateral direction than in the longitudinal direction and grows with good crystallinity, and thus grows slightly in the upward direction while growing in the lateral direction. The semiconductor layers grown in the lateral direction from both openings coincide with each other around the central portion of each. Then, after the surface of the mask portion 5 is completely buried, it grows upward, and the second n-type GaN layer (semiconductor layer) 6 is also completely grown on the mask portion 5. The second n-type GaN layer 6 has good crystallinity in the portions excluding both ends (portions that contact the opening 53) on the mask portion 5 and the matching portion in the central portion, and the dislocation density is also reduced by an order of magnitude. Become.

第2のn形GaN層6上の半導体積層部10は、通常の発光ダイオードを構成する半導体積層部になっている。すなわち、図1に示される例では、SiをドープしたGaNからなるn形層7が1〜10μm程度、アンドープのInGaN系化合物/GaNのMQW構造(たとえば1〜3nmのIn0.17Ga0.83Nからなるウェル層と10〜20nmのIn0.01Ga0.99Nからなるバリア層とが3〜8ペア積層される多重量子井戸構造)からなる活性層8が全体で0.05〜0.3μm程度、MgをドープしたGaNからなるp形層9が0.2〜1μm程度、それぞれ設けられることにより形成されている。 The semiconductor stacked portion 10 on the second n-type GaN layer 6 is a semiconductor stacked portion constituting a normal light emitting diode. That is, in the example shown in FIG. 1, the n-type layer 7 made of Si-doped GaN is about 1 to 10 μm, and consists of an undoped InGaN-based compound / GaN MQW structure (for example, 1 to 3 nm of In 0.17 Ga 0.83 N). The active layer 8 consisting of a multi-quantum well structure in which 3 to 8 pairs of well layers and 10 to 20 nm In 0.01 Ga 0.99 N barrier layers are laminated is about 0.05 to 0.3 μm in total, doped with Mg The p-type layer 9 made of GaN is formed by providing about 0.2 to 1 μm.

なお、半導体積層部10の構成は、製造する半導体素子に応じて必要な構成に積層され、LEDの場合でも、上述の例に限定されるものではなく、n形層7およびp形層9は、活性層側にバンドギャップエネルギーの大きい層(障壁層)を設ける複層構造にすることもできるし、組成の異なる半導体層間に超格子構造または勾配層を設けることもでき、また、第2の窒化物半導体層6がn形層またはp形層を兼ねていてもよい。また、活性層8も多重量子井戸構造に限られずバルク構造や単一量子井戸(SQW)構造であってもよい。さらに、この例では、n形層7とp形層9とで活性層8が挟持されたダブルヘテロ接合構造であるが、n形層とp形層とが直接接合するヘテロ接合構造のものでもよい。要は、LEDを構成する場合には、発光層を形成するようにn形層7とp形層9が設けられていればよい。また、前述の例ではLEDの例であったが、LDの場合でも半導体積層部の構造をLD用の積層構造にすれば、結晶性が優れリーク電流の少ないLDが得られる。   In addition, the structure of the semiconductor lamination part 10 is laminated | stacked on a required structure according to the semiconductor element to manufacture, and also in the case of LED, it is not limited to the above example, The n-type layer 7 and the p-type layer 9 are In addition, a multilayer structure in which a layer (barrier layer) having a large band gap energy is provided on the active layer side, a superlattice structure or a gradient layer can be provided between semiconductor layers having different compositions, and the second layer The nitride semiconductor layer 6 may also serve as an n-type layer or a p-type layer. Further, the active layer 8 is not limited to the multiple quantum well structure, and may be a bulk structure or a single quantum well (SQW) structure. Furthermore, in this example, the active layer 8 is sandwiched between the n-type layer 7 and the p-type layer 9, but the heterojunction structure in which the n-type layer and the p-type layer are directly joined is also used. Good. In short, when an LED is configured, the n-type layer 7 and the p-type layer 9 may be provided so as to form a light emitting layer. In the above-described example, the example is an LED. Even in the case of an LD, an LD having a high crystallinity and a small leakage current can be obtained if the structure of the semiconductor stacked portion is a stacked structure for LD.

つぎに、この発光ダイオードの製法について説明をする。たとえばMOCVDなどのエピタキシャル成長装置を用いて、基板温度を1100℃程度にしてH2雰囲気でサーマルクリーニングをする。その後、基板温度を400〜500℃程度にして、V族原料ガスであるアンモニアガス(NH3)、III族原料の有機金属であるトリメチリガリウム(TMG)、トリメチルアルミニウム(TMA)n形のドーパントガスとしてのSiH4を導入し、Siドープのn形の第1のAl0.05Ga0.95N層2aを0.01〜0.05μm程度、基板温度を900〜1100℃程度にして、GaN層2bを、1〜3μm程度成長する。 Next, a method for manufacturing the light emitting diode will be described. For example, using an epitaxial growth apparatus such as MOCVD, the substrate temperature is set to about 1100 ° C. and thermal cleaning is performed in an H 2 atmosphere. Thereafter, the substrate temperature is set to about 400 to 500 ° C., and ammonia gas (NH 3 ) which is a group V source gas, trimethyl gallium (TMG) and trimethylaluminum (TMA) n-type dopants which are group III source organic metals. SiH 4 as a gas is introduced, the Si-doped n-type first Al 0.05 Ga 0.95 N layer 2a is set to about 0.01 to 0.05 μm, the substrate temperature is set to about 900 to 1100 ° C., and the GaN layer 2b is formed. 1 to 3 μm.

ついで、成長装置から基板を取りだし、たとえばスパッタリング装置や蒸着装置を用いて、Ti膜を10〜200nm程度、Ag膜を10〜200nm程度、SiO2膜を200〜500nm程度順次成膜する。その後、SiO2膜上にレジスト膜を設け、パターニングし、HF水溶液を用いてSiO2膜を、HCl+HNO3水溶液を用いてAg膜を、HF水溶液を用いてTi膜をそれぞれエッチングすることにより、ストライプ状に開口部を形成し、ストライプ状のマスク層3を形成する。 Next, the substrate is taken out from the growth apparatus, and for example, a Ti film is formed in a thickness of about 10 to 200 nm, an Ag film is formed in a thickness of about 10 to 200 nm, and a SiO 2 film is formed in a thickness of about 200 to 500 nm using a sputtering apparatus or a vapor deposition apparatus. Thereafter, a resist film is provided on the SiO 2 film, patterned, and etched by stripping the SiO 2 film using an HF aqueous solution, the Ag film using an HCl + HNO 3 aqueous solution, and the Ti film using an HF aqueous solution. An opening is formed in a shape, and a striped mask layer 3 is formed.

その後、再度MOCVD装置などの成長装置に入れて、原料ガスとして、前述のガスの他に、Inのトリメチルインジウム(TMIn)、p形ドーパントとしてシクロペンタジエニルマグネシウム(Cp2Mg)またはジメチル亜鉛(DMZn)などの必要なガスをキャリアガスの水素と共に導入して、第2のn形GaN層6および半導体積層部10の各半導体層をそれぞれ前述の厚さで成長する。この場合、n形GaN層6は、基板温度が高いと横方向に成長しやすく、基板温度が低いと縦方向に成長しやすいため、最初は850〜1000℃程度で、開口部が埋まったら950〜1100℃程度で成長し、n形層7は、基板温度を950〜1100℃程度で成長し、活性層8は基板温度を700〜770℃程度にして成長し、その後の各層は再度基板温度を950〜1100℃程度にして成長する。なお、InGaN系化合物やAlGaN系化合物のInやAlの組成を変えるには、Inの原料ガスであるTMIn、Alの原料ガスであるTMAの流量を制御することにより変えることができる。 Then, it is again put in a growth apparatus such as an MOCVD apparatus, and in addition to the above-mentioned gas as a source gas, trimethylindium (TMIn) of In, cyclopentadienylmagnesium (Cp 2 Mg) or dimethylzinc (as a p-type dopant) A necessary gas such as DMZn) is introduced together with hydrogen as the carrier gas, and the second n-type GaN layer 6 and the semiconductor layers of the semiconductor stacked portion 10 are grown to the above-described thicknesses. In this case, the n-type GaN layer 6 easily grows in the horizontal direction when the substrate temperature is high, and easily grows in the vertical direction when the substrate temperature is low. The n-type layer 7 grows at a substrate temperature of about 950 to 1100 ° C., the active layer 8 grows at a substrate temperature of about 700 to 770 ° C., and each subsequent layer is grown again at the substrate temperature. Is grown at about 950 to 1100 ° C. In addition, in order to change the composition of In or Al in an InGaN-based compound or an AlGaN-based compound, it can be changed by controlling the flow rate of TMIn, which is an In source gas, or TMA, which is an Al source gas.

その後、半導体積層部10の表面に、たとえばZnOなどからなり、p形層9とオーミックコンタクトをとることができる透光性導電層11を0.01〜5μm程度設ける。このZnOは、Gaをドープして3〜5×10-4Ω・cm程度の比抵抗になるように成膜する。この透光性導電層11は、ZnOに限定されるものではなく、ITOやNiとAuとの2〜100nm程度の薄い合金層でも、光を透過させながら、電流をチップ全体に拡散することができる。 Thereafter, a light-transmitting conductive layer 11 made of, for example, ZnO and capable of making ohmic contact with the p-type layer 9 is provided on the surface of the semiconductor stacked portion 10 to about 0.01 to 5 μm. This ZnO is formed by doping Ga so as to have a specific resistance of about 3 to 5 × 10 −4 Ω · cm. The translucent conductive layer 11 is not limited to ZnO, and even a thin alloy layer of about 2 to 100 nm of ITO or Ni and Au can diffuse current throughout the chip while transmitting light. it can.

そして、基板1の裏面を研磨して基板1の厚さを100μm程度にした後に、その裏面にTi/AuまたはCr/Pt/AuまたはNi/Auなどを積層してn側電極13を形成し、さらに、透光性導電層7の表面にリフトオフ法により、Ti/Auの積層構造でp側電極12を形成し、最後にプラズマCVD法により図示しないSiON膜でチップ全体を覆い、電極部に開口部を形成する。その後、ウェハからチップ化することにより、図1に示される構造の発光素子チップが形成される。   Then, after polishing the back surface of the substrate 1 so that the thickness of the substrate 1 is about 100 μm, the n-side electrode 13 is formed by laminating Ti / Au, Cr / Pt / Au, Ni / Au or the like on the back surface. Further, the p-side electrode 12 is formed with a Ti / Au laminated structure on the surface of the translucent conductive layer 7 by a lift-off method, and finally the entire chip is covered with a SiON film (not shown) by a plasma CVD method to form an electrode portion. An opening is formed. Thereafter, the wafer is chipped to form a light emitting element chip having the structure shown in FIG.

本発明によれば、半導体基板に窒化物半導体層を積層しているため、基板の裏面に一方の電極を形成することができ、チップの上下に一対の電極を形成する垂直型の素子とすることができる。しかし、このような半導体基板が用いられる場合でも、積層した半導体積層部10の一部をドライエッチングによりエッチングして露出するn形層7にn側電極12を形成することができる。この構造であっても、従来のサファイア基板を用いる場合よりも基板の熱伝導率がよいため、高温高出力まで発光効率の低下が起こらない素子が得られる点で本発明を適用する効果がある。   According to the present invention, since the nitride semiconductor layer is laminated on the semiconductor substrate, one electrode can be formed on the back surface of the substrate, and a vertical element in which a pair of electrodes are formed above and below the chip. be able to. However, even when such a semiconductor substrate is used, the n-side electrode 12 can be formed on the n-type layer 7 which is exposed by etching a part of the laminated semiconductor laminated portion 10 by dry etching. Even with this structure, since the thermal conductivity of the substrate is better than when a conventional sapphire substrate is used, there is an effect of applying the present invention in that an element in which the light emission efficiency does not decrease until high temperature and high output can be obtained. .

本発明による窒化物半導体素子の一実施形態であるLEDの断面説明図である。It is sectional explanatory drawing of LED which is one Embodiment of the nitride semiconductor element by this invention. 本発明によるマスク部近傍の拡大断面説明図である。It is an expanded sectional explanatory view of the mask part vicinity by this invention. 本発明による窒化物半導体素子の素子分離前の断面説明図である。FIG. 4 is a cross-sectional explanatory diagram of the nitride semiconductor device according to the present invention before device separation. 従来の窒化物半導体を用いたLEDの構成例を示す図である。It is a figure which shows the structural example of LED using the conventional nitride semiconductor.

符号の説明Explanation of symbols

1 半導体基板
2 第1の窒化物半導体層
3 金属膜
4 絶縁膜
5 マスク部
6 第2の窒化物半導体層
10 半導体積層部
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st nitride semiconductor layer 3 Metal film 4 Insulating film 5 Mask part 6 2nd nitride semiconductor layer 10 Semiconductor laminated part

Claims (3)

半導体基板と、該半導体基板上に設けられる第1の窒化物半導体層と、該第1の窒化物半導体層上に設けられ、開口部を有するマスク部と、該マスク部上に前記開口部から横方向に選択成長される第2の窒化物半導体層と、該第2の窒化物半導体層上に発光層を形成するように窒化物半導体層が積層される半導体積層部とからなり、前記マスク部が、前記第1の窒化物半導体層側に設けられる金属膜と、該金属膜上に設けられる絶縁膜とからなる窒化物半導体発光素子。   A semiconductor substrate, a first nitride semiconductor layer provided on the semiconductor substrate, a mask portion provided on the first nitride semiconductor layer and having an opening, and on the mask portion from the opening The mask comprising: a second nitride semiconductor layer selectively grown in a lateral direction; and a semiconductor stacked portion in which the nitride semiconductor layer is stacked so as to form a light emitting layer on the second nitride semiconductor layer. A nitride semiconductor light-emitting element, the portion of which comprises a metal film provided on the first nitride semiconductor layer side and an insulating film provided on the metal film. 前記金属膜が、前記第1の窒化物半導体層側に設けられる第1の金属膜および該第1の金属膜上に設けられる第2の金属膜の少なくとも2層構造からなり、前記第1の金属膜が前記半導体積層部の成長温度よりも高い融点を有する金属からなり、前記第2の金属膜が前記発光層で発生した光を反射する金属からなる請求項1記載の窒化物半導体発光素子。   The metal film has at least a two-layer structure of a first metal film provided on the first nitride semiconductor layer side and a second metal film provided on the first metal film, 2. The nitride semiconductor light emitting element according to claim 1, wherein the metal film is made of a metal having a melting point higher than a growth temperature of the semiconductor stacked portion, and the second metal film is made of a metal that reflects light generated in the light emitting layer. . 前記第1の金属膜が、W、TiおよびPdの少なくとも1種からなり、前記第2の金属膜が、Al、AgおよびAuの少なくとも1種からなる請求項2記載の窒化物半導体発光素子。   3. The nitride semiconductor light emitting element according to claim 2, wherein the first metal film is made of at least one of W, Ti, and Pd, and the second metal film is made of at least one of Al, Ag, and Au.
JP2005337806A 2005-11-22 2005-11-22 Nitride semiconductor light-emitting element Pending JP2007142345A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2005337806A JP2007142345A (en) 2005-11-22 2005-11-22 Nitride semiconductor light-emitting element
TW095143057A TW200735418A (en) 2005-11-22 2006-11-21 Nitride semiconductor device
PCT/JP2006/323176 WO2007060931A1 (en) 2005-11-22 2006-11-21 Nitride semiconductor device
US12/085,327 US7977703B2 (en) 2005-11-22 2006-11-21 Nitride semiconductor device having a zinc-based substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005337806A JP2007142345A (en) 2005-11-22 2005-11-22 Nitride semiconductor light-emitting element

Publications (1)

Publication Number Publication Date
JP2007142345A true JP2007142345A (en) 2007-06-07

Family

ID=38204810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005337806A Pending JP2007142345A (en) 2005-11-22 2005-11-22 Nitride semiconductor light-emitting element

Country Status (1)

Country Link
JP (1) JP2007142345A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008159980A (en) * 2006-12-26 2008-07-10 Kyocera Corp LIGHT EMITTING ELEMENT AND LIGHTING DEVICE
KR20120017935A (en) * 2010-08-20 2012-02-29 엘지이노텍 주식회사 Light emitting element
US8183591B2 (en) 2009-03-31 2012-05-22 Samsung Electronics Co., Ltd. Light-emitting devices
JP2013517622A (en) * 2010-01-15 2013-05-16 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method of forming a composite substrate and growing a III-V light emitting device on the composite substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031068A (en) * 1998-07-14 2000-01-28 Mitsubishi Cable Ind Ltd SUBSTRATE FOR GaN CRYSTAL GROWTH
JP2004014996A (en) * 2002-06-11 2004-01-15 Sanyo Electric Co Ltd Optical semiconductor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031068A (en) * 1998-07-14 2000-01-28 Mitsubishi Cable Ind Ltd SUBSTRATE FOR GaN CRYSTAL GROWTH
JP2004014996A (en) * 2002-06-11 2004-01-15 Sanyo Electric Co Ltd Optical semiconductor element

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008159980A (en) * 2006-12-26 2008-07-10 Kyocera Corp LIGHT EMITTING ELEMENT AND LIGHTING DEVICE
US8183591B2 (en) 2009-03-31 2012-05-22 Samsung Electronics Co., Ltd. Light-emitting devices
US8299492B2 (en) 2009-03-31 2012-10-30 Samsung Electronics Co., Ltd. Light-emitting devices
US8546843B2 (en) 2009-03-31 2013-10-01 Samsung Electronics Co., Ltd. Light emitting devices
US8772823B2 (en) 2009-03-31 2014-07-08 Samsung Electronics Co., Ltd. Light-emitting devices
JP2013517622A (en) * 2010-01-15 2013-05-16 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method of forming a composite substrate and growing a III-V light emitting device on the composite substrate
KR20120017935A (en) * 2010-08-20 2012-02-29 엘지이노텍 주식회사 Light emitting element
KR101710359B1 (en) 2010-08-20 2017-02-27 엘지이노텍 주식회사 Light emitting device

Similar Documents

Publication Publication Date Title
CN101297410B (en) III-nitride light-emitting device with double heterostructure light-emitting region
CN101689586B (en) Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor
JP4954536B2 (en) Nitride semiconductor light emitting device
JP4895587B2 (en) Nitride semiconductor light emitting device
KR100784065B1 (en) Nitride semiconductor light emitting device and manufacturing method
WO2007060931A1 (en) Nitride semiconductor device
JP3924303B2 (en) Nitride semiconductor device and manufacturing method thereof
CN101292328A (en) Nitride semiconductor device and manufacturing method thereof
JP2006332205A (en) Nitride semiconductor light emitting device
CN101667614A (en) Light emitting diode device and manufacturing method thereof
JP2009224370A (en) Nitride semiconductor device
KR20150015760A (en) Template for light emitting device fabricating and method of fabricating ultraviolet light emitting device
JP2009123836A (en) Nitride semiconductor light-emitting element
JP6153351B2 (en) Semiconductor light emitting device
JP2012069982A (en) Nitride semiconductor light-emitting element
JP2006339427A (en) Method of manufacturing epitaxial wafer for nitride semiconductor light emitting diode, epitaxial wafer for nitride semiconductor light emitting diode, and nitride semiconductor light emitting diode
JP5379703B2 (en) Ultraviolet semiconductor light emitting device
JP2008294018A (en) Method of manufacturing group iii nitride-based compound semiconductor light emitting element
JP2007142345A (en) Nitride semiconductor light-emitting element
KR20050063493A (en) A wafer-bonded semiconductor led and a method for making thereof
JP4304984B2 (en) Nitride semiconductor growth substrate and nitride semiconductor device using the same
KR101124470B1 (en) Semiconductor light emitting device
JP2007019526A (en) Process for fabricating nitride semiconductor element
JP2007019526A5 (en)
JP4954534B2 (en) Nitride semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20081022

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110920

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111118

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120313