JP2007149745A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing ON-resistance by improving mobility of a carrier in a p-channel trench gate transistor, and its manufacturing method. <P>SOLUTION: The semiconductor device having a p-channel trench gate MOS on a p-type substrate 1 includes a p-type drift layer 2 provided on the principal plane of the substrate 1, an n-type body region 3 provided on the layer 2, a trench 6 provided on the region 3 having at least part of its bottom reaching the drift layer 2, a gate insulation film 7 provided on a sidewall and the bottom of the trench 6, polysilicon 8 provided on the gate insulation film 7 for filling the trench 6, a p-type source region 4 provided in the body region 3 adjacent to the trench 6, and so on. The principal plane of the p-type substrate 1 is (111) or (110), and the sidewall of the trench 6 (that is, a channel formation plane) is ä110}. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to increase carrier mobility and reduce on-resistance in a P-channel trench gate type transistor.

  In planar type MOSFETs (MOS) having a wafer main surface as a channel or trench gate type MOSFETs (trench gate MOS) having a channel on the side wall of a trench formed in a wafer, lowering the on-resistance reduces power consumption and heat generation. It becomes suppression. However, to reduce the on-resistance, for example, if the gate oxide film is thinned or the resistance of the diffusion resistance is lowered, the withstand voltage also decreases accordingly. There is an upper limit.

  On the other hand, as means for lowering the on-resistance without lowering the withstand voltage, a method using a plane orientation or current direction with high mobility is conceivable (for example, see Non-Patent Document 1). Non-Patent Document 1 describes that in an N-channel MOS, the carrier mobility is maximum when the channel forming surface is {100}. In the P-channel MOS, the carrier mobility is maximum when the channel forming surface is {110} and the current direction is <110>, and when the channel forming surface is {110}, the mobility depends on the current direction. It is written to do.

Patent Document 1 describes that the mobility of electrons as carriers is high when the channel formation surface is {100} in an N-channel trench gate MOS. Patent Document 2 describes that a trench of a trench gate MOS is formed in a hexagonal pattern in a plan view and its effect (a large gate width can be taken).
Here, the notation of the crystal plane orientation and direction in the present application will be described. A specific crystal plane orientation is represented by Miller index (hkl). In addition, the whole or a part of a set equivalent to the (hkl) plane is denoted by {hkl}, and the direction perpendicular to the (hkl) plane is denoted by <hkl>.

JP 2002-231948 A US Pat. No. 5,008,725 T. T. et al. Sato, Y. et al. Takeshi, H .; Hara and Y.H. Okamoto: Phys. Rev. , B4, 1950 (1971)

In general, in a manufacturing process of a semiconductor device, a wafer whose surface orientation is (100) on the substrate surface (hereinafter simply referred to as “(100) wafer”) is used. When a trench gate MOS that connects the drain electrode to the back surface of the wafer is formed using such a wafer, the current flows between the front surface and the back surface of the substrate, so that the current direction is <100> (that is, the (100) plane. The direction of the perpendicular line passing through. Therefore, when a P-channel trench gate MOS is formed using a (100) wafer, the trench sidewall which is a channel formation surface (that is, a channel formation region) is a {110} surface having a high hole mobility. Even in this case, since the current direction is <100>, there is a problem that the resultant mobility is suppressed to a low level.
The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof in which the carrier mobility in a P-channel trench gate type transistor can be increased and the on-resistance can be reduced. For the purpose of provision.

[Invention 1] In order to achieve the above object, a semiconductor device of Invention 1 is a semiconductor device having a P-channel trench gate type transistor in a semiconductor substrate, and a first P provided on the surface of the semiconductor substrate. Type semiconductor layer, an N-type semiconductor layer provided on the first P-type semiconductor layer, and a trench provided in the N-type semiconductor layer and having at least a part of a bottom surface reaching the first P-type semiconductor layer An insulating film provided on the side wall and the bottom surface of the trench; a conductor provided on the insulating film to embed the trench; and a first electrode provided in the N-type semiconductor layer adjacent to the trench. The P-type semiconductor layer, and the side wall of the trench made of the N-type semiconductor layer is a channel formation region of the trench gate type transistor, and the surface orientation of the surface of the semiconductor substrate is (111) and the surface orientation of the side wall of the trench is {110}.
With such a configuration, the direction of the current flowing through the channel formation region is the direction of the perpendicular passing through the (111) plane which is the plane orientation of the substrate surface, that is, <111>. The plane orientation of the channel formation region is {110}. Therefore, the carrier mobility in the channel formation region can be increased as compared with the conventional example.

[Invention 2] The semiconductor device of Invention 2 is characterized in that, in the semiconductor device of Invention 1, the shape of the portion of the insulating film provided on the side wall in a plan view is a hexagon. is there.
With such a configuration, the gate width of the transistor per unit area in plan view can be increased, which is advantageous in that a large current flows between the source and drain sandwiching the channel formation region from above and below. Further, since the surface orientation of all the sidewalls of the trench is {110}, the thickness can be made uniform even when the insulating film is formed by thermal oxidation.

[Invention 3] The semiconductor device of Invention 3 is a semiconductor device having a P-channel trench gate type transistor in a semiconductor substrate, the first P-type semiconductor layer provided on the surface of the semiconductor substrate, and the first An N-type semiconductor layer provided on the P-type semiconductor layer, a trench provided in the N-type semiconductor layer and having at least a part of a bottom surface reaching the first P-type semiconductor layer, a sidewall of the trench, and the An insulating film provided on the bottom surface, a conductor provided on the insulating film and filling the trench, and a second P-type semiconductor layer provided in the N-type semiconductor layer adjacent to the trench The sidewall of the trench made of the N-type semiconductor layer is a channel formation region of the trench gate type transistor, the surface orientation of the surface of the semiconductor substrate is (110), and the tray The surface orientation of the side wall of the punch is {110}.
With such a configuration, the direction of the current flowing through the channel formation region is the direction of the perpendicular passing through the (110) plane which is the plane orientation of the substrate surface, that is, <110>. The plane orientation of the channel formation region is {110}. Therefore, carrier mobility in the channel formation region can be increased as compared with the first aspect.

[Invention 4] A manufacturing method of a semiconductor device of Invention 4 is a manufacturing method of a semiconductor device in which a P-channel trench gate type transistor is formed on a semiconductor substrate, wherein a first P-type semiconductor layer is formed on the surface of the semiconductor substrate. Forming a step, forming an N-type semiconductor layer on the first P-type semiconductor layer, forming a trench in the N-type semiconductor layer, and at least a part of the bottom surface of the first P-type semiconductor layer. A step of reaching the semiconductor layer, a step of forming an insulating film on the side wall and the bottom surface of the trench, a step of embedding the trench by forming a conductor on the insulating film, and the adjoining the trench Forming a second P-type semiconductor layer in the N-type semiconductor layer, wherein the sidewall of the trench made of the N-type semiconductor layer is a channel formation region of the trench gate type transistor. In the step of forming the first P-type semiconductor layer, the semiconductor substrate having a surface orientation of (111) is used as the semiconductor substrate, and in the step of forming the trench, the surface of the side wall of the trench is used. The N-type semiconductor layer is etched so that the orientation is {110}.

Here, the “semiconductor substrate” is a wafer made of, for example, silicon. In addition, in the invention 4, as a method of “etching the N-type semiconductor layer so that the surface orientation of the side wall of the trench is {110}”, for example, the surface orientation of the surface (slice surface) is (111) and the orientation There is a method of preparing a wafer having a flat plane orientation of (11-2) and forming a trench in an N-type semiconductor layer on the wafer.
According to the method of manufacturing a semiconductor device of the fourth aspect, a P-channel trench gate type transistor in which the channel orientation of the channel formation region is {110} and the direction of the current flowing through the channel formation region is <111> is formed. Therefore, carrier mobility in the channel formation region can be increased as compared with the conventional example.

[Invention 5] A manufacturing method of a semiconductor device of Invention 5 is a manufacturing method of a semiconductor device in which a P-channel trench gate type transistor is formed on a semiconductor substrate, wherein a first P-type semiconductor layer is formed on the surface of the semiconductor substrate. Forming a step, forming an N-type semiconductor layer on the first P-type semiconductor layer, forming a trench in the N-type semiconductor layer, and at least a part of the bottom surface of the first P-type semiconductor layer. A step of reaching the semiconductor layer, a step of forming an insulating film on the side wall and the bottom surface of the trench, a step of embedding the trench by forming a conductor on the insulating film, and the adjoining the trench Forming a second P-type semiconductor layer in the N-type semiconductor layer, wherein the sidewall of the trench made of the N-type semiconductor layer is a channel formation region of the trench gate type transistor. In the step of forming the first P-type semiconductor layer, the semiconductor substrate having a surface orientation of (110) is used as the semiconductor substrate, and in the step of forming the trench, the surface of the side wall of the trench is used. The N-type semiconductor layer is etched so that the orientation is {110}.

Here, in the invention 5, as a method of “etching the N-type semiconductor layer so that the surface orientation of the side wall of the trench is {110}”, for example, the surface orientation of the surface (slice surface) is (110) and There is a method in which a wafer having an orientation flat plane orientation of (−110) is prepared, and a trench is formed in an N-type semiconductor layer on the wafer.
According to the semiconductor device manufacturing method of the fifth aspect of the invention, a P-channel trench gate type transistor in which the channel orientation of the channel formation region is {110} and the direction of the current flowing through the channel formation region is <110> is formed. Therefore, carrier mobility in the channel formation region can be increased as compared with the fourth aspect.

  According to the present invention, carrier mobility in a P-channel trench gate type transistor can be increased, and its on-resistance can be reduced.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is an actual measurement result showing the relationship between carrier mobility (μ ₀ ) and current direction (S / D direction) in a P-channel planar type MOS (gate length L / gate width W = 100 μm / 100 μm). is there. The angle in the current direction in FIG. 1 is defined as <100> being 0 °. <100> = 0 °, <111> ≈54.7 °, <110> = 90 °.

  The present inventor performed such measurement separately for a case where the channel forming surface is {100} and a case where {110}. As a result, the present inventors have found that, in the P-channel MOS, “the channel forming surface has a higher mobility than {100} in {110} in all current directions” and “the channel forming surface. Is {110}, the mobility of carriers on the channel formation surface depends on the current direction, and when the current direction is <111>, the mobility is 1 compared to the case where the current direction is <100>. When the current direction is <110>, the mobility is increased by about 1.6 times. ” The above are actual measurement results of the P-channel planar type MOS. In the planar type MOS, the plane direction of the wafer and the plane direction of the channel forming surface are the same, and the current direction can be determined as a desired direction by changing the mask design.

  Here, the present inventor was able to obtain both the “plane orientation of the channel forming surface” and the “current direction” by the above-described measurement even in the P-channel type trench gate MOS which has been conventionally formed only on the (100) wafer. It has been found that the mobility can be increased by setting each to a suitable value. The inventor then selects the wafer surface orientation to set the “current direction” to a suitable value, and the wafer surface orientation to set the “channel forming surface orientation” to a preferred value. And selecting a combination of orientation plane orientations.

  When the actual measurement result of FIG. 1 is applied to the P-channel trench gate MOS, the current flows in the trench gate MOS from the front surface side to the back surface side (or from the back surface side to the front surface side) of the semiconductor substrate. The direction of the perpendicular line passing through the substrate surface. Specifically, in the case of a trench gate MOS formed on a semiconductor substrate whose surface orientation is (100), (111), (110), the current directions are <100>, <111>, <110>, respectively. become. <100> is the direction of the perpendicular passing through the (100) plane (that is, the direction perpendicular to the (100) plane), and <111> is the direction of the perpendicular passing through the (111) plane. , <110> is the direction of a perpendicular line passing through the (110) plane.

  In FIG. 1, the mobility when the channel forming surface is {110} and the current direction is <100>, <111>, <110> respectively corresponds to A, B, and C in the figure. From FIG. 1, when forming a P-channel trench gate with a channel forming surface of {110}, it is compared with A formed with a (100) substrate (that is, the channel forming surface is {110} and the current direction is <100>). Then, B (that is, the channel forming surface is {110} and the current direction is <111>) formed by the (110) substrate is about 1.3 times C (that is, the channel forming surface is {110} and the current direction is the current direction). <110>), it can be expected that the mobility is increased by about 1.6 times.

(First embodiment)
FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device according to the embodiment of the present invention. As shown in FIG. 2, this semiconductor device is a semiconductor device having a P-type trench gate MOS on a P-type semiconductor substrate (hereinafter simply referred to as “P-type substrate”) 1. A P-type drift layer 2 provided on the main surface, an N-type body region 3 provided on the P-type drift layer 2, and an N-type body region 3, at least a part of the bottom surface of which is the P-type drift layer 2 , Trench 8 that is provided on the sidewall and bottom surface of trench 6, polysilicon 8 that is provided on gate insulating film 7 and fills trench 6, and N-type body region adjacent to trench 6 3 includes a P-type source region 4, an N-type body contact region 5, an interlayer insulating film 9, and a wiring layer 10 made of aluminum or the like.

  In this P channel type trench gate MOS, the P type drift layer 2 is a drain region, and the side wall (consisting of the N type body region 3) of the trench 6 is a channel formation surface. Further, in this P channel type trench gate MOS, the main surface (ie, slice surface) of the P type substrate 1 is (111), and the side wall (ie, channel forming surface) of the trench 6 is {110}. .

3A to 3C are process diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Next, a method for manufacturing the semiconductor device shown in FIG. 2 will be described.
First, as shown in FIG. 3A, a P-type drift layer 2 having a boron concentration of 8E15 [cm ⁻³ ] is epitaxially grown by 8 μm on a P-type substrate 1 whose slice plane is a (111) plane. After ion implantation of P ⁺ with a dose amount of 1E14 [cm ⁻² ], annealing is performed at 1100 [° C.] for 400 minutes to form the N-type body region 3. The P-type substrate 1 used here preferably has a low resistance because the drain is connected to the back side.

  Next, as shown in FIG. 3B, a trench 6 having a depth of 2 [μm] is formed in the gate region by dry etching. For example, if the trench is formed so that the stripe pattern 1a is raised with the plane orientation relationship as shown in FIG. 4A (that is, the slice plane is (111) and the orientation flat is (11-2)). Of the two pairs of trench sidewalls, the wider one (that is, the main channel formation surface) is constituted by {110} planes.

  Note that the relationship between the plane orientations of FIG. 4A shown here is an example, and it is not particularly necessary to limit the orientation flat plane orientation to (11-2) as shown in FIG. 4A. In the present invention, it is only necessary to form the trench so that the side wall of the trench becomes {110}. However, it is preferable to set the trench and the orientation flat vertically or in parallel from the viewpoint of mask alignment at the time of forming the trench.

Returning to FIG. 3B, after forming the trench 6, thermal oxidation is performed at 950 [° C.] for 25 minutes to form a gate insulating film 7 of 70 [nm]. When the gate insulating film 7 is formed by thermal oxidation, the bottom of the trench can be thicker than the trench side wall due to the difference in oxidation rate. The thicker the bottom oxide film, the better from the standpoint of breakdown voltage and parasitic capacitance. Therefore, it is better to form the gate insulating film 7 by thermal oxidation than CVD or plasma oxidation.
Next, as shown in FIG. 3C, 700 nm of polysilicon 8 having a phosphorus concentration of 1E20 [cm ⁻³ ] is deposited by low pressure CVD using silane as a raw material. Annealing at 1000 [° C.] is performed for 2 minutes.

Next, as shown in FIG. 3D, the polysilicon on the entire surface is etched, and the oxide film on the surface of the substrate is etched. By photolithography, ions of BF2 ⁺ are implanted into the source region 4 at a dose of 1E15 [cm ⁻² ]. Similarly, As ⁺ is ion-implanted into the body contact region 5 at a dose of 1E16 [cm ⁻² ]. FIG. 5A shows a planar structure of the P-channel trench gate MOS formed through the steps so far. In the x part of the figure, the trench sidewall is the {112} plane, and in the y part of the figure, the trench sidewall is {110}. The ratio of the length of the x portion and the y portion is not particularly limited, but it is preferable from the viewpoint of the surface anisotropy of mobility that y is longer than x.

  Next, as shown in FIG. 2, an interlayer insulating film 9 is deposited by 1000 [nm]. By photolithography, the source region and the body contact region of the photoresist are opened, and the insulating film is dry etched to form the source contact. Finally, aluminum is sputtered to form the wiring layer 10. As a result, a P-channel trench gate MOS having a channel forming surface of {110} and a current direction of <111> is completed.

  Thus, according to the manufacturing method of the semiconductor device according to the first embodiment of the present invention, the current direction on the channel formation surface is the direction of the perpendicular passing through the (111) plane which is the surface orientation of the substrate surface, that is, < 111>. The plane orientation of the channel formation surface is {110}. As clarified in FIG. 1, when the channel forming surface is set to {110}, the movement of holes as carriers is more in the case of <111> than in the case where the current direction in the channel forming surface is <100>. Since the degree becomes higher, the on-resistance can be lowered.

(Second Embodiment)
In the first embodiment, the case where the trench is formed so that the stripe pattern 1a is raised when the trench 6 is formed as shown in FIG. 4A has been described. However, the trench formation pattern is not limited to the stripe shape, and may have other shapes.
For example, as shown in FIG. 4B while maintaining the relationship of the plane orientation as shown in FIG. 4A (that is, the slice plane is (111) and the orientation flat is (11-2)). As described above, the trench may be formed so that the hexagonal pattern 2a is raised. FIG. 5B is a diagram showing an example of a planar structure of the P-channel trench gate MOS according to the second embodiment. As shown in FIG. 5B, the shape of the portion of the gate insulating film 7 formed on the trench sidewall in a plan view is a hexagon. In addition, x, y, and z in FIG. The ratio of the widths of the respective trenches is not particularly limited, but it is preferable that they are all equal because the most efficient spread is achieved.

In the P-channel trench gate MOS having such a hexagonal pattern, all six channel formation surfaces are {110} and the current direction is <111>. The hexagonal pattern has an advantage that the gate length per unit area can be larger than that of the stripe pattern. Moreover, since the crystal of the (111) substrate has sixfold symmetry, it is convenient for a hexagonal pattern. For example, since all six sides of the sidewall of the trench are equivalent, even if the oxide film is formed by thermal oxidation, the film thickness of the six sides is formed uniformly.
In addition, in this 2nd Embodiment, since structures other than a trench formation pattern are the same as 1st Embodiment, the overlapping description is abbreviate | omitted.

(Third embodiment)
In the third embodiment, a P-channel trench gate MOS in which the surface orientation of the main surface of the P-type substrate is (110) and the surface orientation of the channel formation surface is (110) will be described. The third embodiment differs from the first embodiment in the plane orientation of the main surface of the P-type substrate 1 to be used and the plane orientation of the orientation flat. Since the other configuration is the same as that of the first embodiment, the description overlapping that of the first embodiment is omitted.

FIG. 4C is a plan view showing an example of a plane orientation relationship according to the third embodiment.
In the third embodiment, a stripe pattern 3a as shown in FIG. 4C has the plane orientation relationship shown in FIG. 4C (that is, the slice plane is (110) and the orientation flat is (−110)). A trench is formed so as to be raised. When the trench 6 shown in FIG. 3B is formed on the premise of such a plane orientation relationship, the sidewall of the trench 6 is constituted by a {110} plane.

Further, when the trench gate MOS is formed on the P-type substrate 1 whose main surface has a plane orientation of (110), the current direction on the channel formation surface is <110>. Therefore, a P-channel trench gate MOS having a channel forming surface of {110} and a current direction of <110> can be formed.
As clarified in FIG. 1, when the channel formation surface is set to {110}, the movement of holes as carriers is greater in the case of <110> than in the case where the current direction in the channel formation surface is <111>. Since the degree becomes higher, it is possible to lower the on-resistance.

  In this embodiment, the P-type substrate 1 corresponds to the “semiconductor substrate” of the present invention, and the P-type drift layer 2 corresponds to the “first P-type semiconductor layer” of the present invention. The N-type body 3 corresponds to the “N-type semiconductor layer” of the present invention, and the source region 4 corresponds to the “second P-type semiconductor layer” of the present invention. Further, the gate insulating film 7 corresponds to the “insulating film” of the present invention, and the polysilicon 8 corresponds to the “conductor” of the present invention.

The figure which shows the result of having simulated the relationship between the mobility of the carrier in P channel type trench gate MOS, and an electric current direction (S / D direction). FIG. 14 is a cross-sectional view illustrating a structure example of a semiconductor device according to an embodiment. FIG. 6 is a process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. The conceptual diagram which shows an example of the relationship of the surface orientation which concerns on 1st, 2nd and 3rd embodiment. The figure which shows an example of the planar structure of P channel type trench gate MOS.

Explanation of symbols

1 P-type substrate 2 P-type drift layer 3 N-type body 4 Source region 5 Body contact region 6 Trench 7 Gate insulating film 8 Polysilicon 9 Interlayer insulating film 10 Wiring layer

Claims (5)

A semiconductor device having a P-channel trench gate type transistor on a semiconductor substrate,
A first P-type semiconductor layer provided on the surface of the semiconductor substrate;
An N-type semiconductor layer provided on the first P-type semiconductor layer;
A trench provided in the N-type semiconductor layer, at least a part of the bottom reaching the first P-type semiconductor layer;
An insulating film provided on the side wall and the bottom surface of the trench;
A conductor provided on the insulating film and filling the trench;
A second P-type semiconductor layer provided in the N-type semiconductor layer adjacent to the trench,
The side wall made of the N-type semiconductor layer of the trench is a channel formation region of the trench gate type transistor,
The semiconductor device according to claim 1, wherein the surface orientation of the surface of the semiconductor substrate is (111), and the surface orientation of the side wall of the trench is {110}.   The semiconductor device according to claim 1, wherein a shape of the portion of the insulating film provided on the side wall in a plan view is a hexagon. A semiconductor device having a P-channel trench gate type transistor on a semiconductor substrate,
A first P-type semiconductor layer provided on the surface of the semiconductor substrate;
An N-type semiconductor layer provided on the first P-type semiconductor layer;
A trench provided in the N-type semiconductor layer, at least a part of the bottom reaching the first P-type semiconductor layer;
An insulating film provided on the side wall and the bottom surface of the trench;
A conductor provided on the insulating film and filling the trench;
A second P-type semiconductor layer provided in the N-type semiconductor layer adjacent to the trench,
The side wall made of the N-type semiconductor layer of the trench is a channel formation region of the trench gate type transistor,
The semiconductor device according to claim 1, wherein the surface orientation of the surface of the semiconductor substrate is (110), and the surface orientation of the side wall of the trench is {110}. A method of manufacturing a semiconductor device for forming a P-channel trench gate type transistor on a semiconductor substrate, comprising:
Forming a first P-type semiconductor layer on a surface of the semiconductor substrate;
Forming an N-type semiconductor layer on the first P-type semiconductor layer;
Forming a trench in the N-type semiconductor layer and causing at least a part of the bottom surface to reach the first P-type semiconductor layer;
Forming an insulating film on the side wall and the bottom surface of the trench;
Forming a conductor on the insulating film to bury the trench;
Forming a second P-type semiconductor layer in the N-type semiconductor layer so as to be adjacent to the trench,
The side wall made of the N-type semiconductor layer of the trench is a channel formation region of the trench gate type transistor,
In the step of forming the first P-type semiconductor layer, the semiconductor substrate having a surface orientation of (111) is used,
In the step of forming the trench, the N-type semiconductor layer is etched so that the surface orientation of the side wall of the trench is {110}. A method of manufacturing a semiconductor device for forming a P-channel trench gate type transistor on a semiconductor substrate, comprising:
Forming a first P-type semiconductor layer on a surface of the semiconductor substrate;
Forming an N-type semiconductor layer on the first P-type semiconductor layer;
Forming a trench in the N-type semiconductor layer and causing at least a part of the bottom surface to reach the first P-type semiconductor layer;
Forming an insulating film on the side wall and the bottom surface of the trench;
Forming a conductor on the insulating film to bury the trench;
Forming a second P-type semiconductor layer in the N-type semiconductor layer so as to be adjacent to the trench,
The side wall made of the N-type semiconductor layer of the trench is a channel formation region of the trench gate type transistor,
In the step of forming the first P-type semiconductor layer, the semiconductor substrate having a surface orientation of (110) is used,
In the step of forming the trench, the N-type semiconductor layer is etched so that the surface orientation of the side wall of the trench is {110}.

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