JP2007158783A - Input clock phase compensation device - Google Patents

Abstract

A phase delay of an input clock is compensated.
SOLUTION: The phase comparators 120 and 130 for detecting a phase difference between two clock signals, and the stage after the phase comparators 120 and 130 and the stage before the oscillator 150 are provided. A signal switching unit 140 that switches and outputs one of the output signals, and an oscillator 150 that is provided in a subsequent stage of the signal switching unit 140 and outputs a frequency according to the output voltage of the phase comparison units 120 and 130. The phase comparators 120 and 130 compare the phases of the external clock signal and the clock signal output from the oscillator 150 and output a differential signal. The oscillator 150 is output from the signal switching unit 140. A phase compensation device 10 for an input clock, wherein the clock signal is inputted and the clock signal is given to the phase comparators 120 and There is provided.
[Selection] Figure 1

Description

  The present invention relates to an input clock phase compensation device.

  In signal processing circuits that handle high-speed clocks, such as video equipment, it is important to manage the phases of clocks and signals input from outside. In particular, in a system that handles high-definition video such as HDTV (High Definition TeleVision), the frequency of the clock input to the signal processing circuit increases, and the LSI (Large Scale Integration) increases in scale. As a result, the clock delay inside the LSI cannot be ignored.

  9 and 10 are explanatory diagrams when a clock delay occurs inside the LSI. As shown in FIG. 9, when the number of D-type flip-flops (hereinafter referred to as “DFF”) 17 of the signal processing apparatus 10 using LSI increases, It is necessary to distribute the clock. In this case, a delay or skew occurs due to the clock tree 16, and a phenomenon in which the phases of the video signal input and the clock input are aligned is shifted when input to the internal DFF 17 occurs. .

  In FIG. 10, (a) shows a timing chart when the video signal input and the clock input are in phase, and (b) shows a timing chart when the video signal input and the clock input are out of phase. Show. As shown in FIG. 10A, when the video signal input and the clock input are in phase, the setup / hold condition is satisfied in the DFF. However, as shown in FIG. 10B, when the video signal input and the clock input are out of phase and do not match, a hold violation occurs in the DFF in the input stage. When a hold violation occurs in the DFF, a problem that data cannot be received normally occurs.

  In order to solve this problem, as shown in FIG. 11, a PLL (Phase Locked Loop) is usually provided at the clock input so that the phase of the clock input from the outside matches the phase of the clock input to the DFF. There is known a method of compensating for a phase shift by performing the above. The signal processing apparatus 10 shown in FIG. 11 includes a PLL 11 and a clock tree 16 that distributes a clock to a plurality of flip-flops. The PLL 11 includes a phase comparator 12 and an oscillator 15. In FIG. 11, a DFF 17 is shown as one of the plurality of flip-flops.

  In the PLL 11 of FIG. 11, the phase is adjusted so that the skew of the DFF 17 matches. As a result, the phase shift due to the delay of the clock tree 16 can be compensated. FIG. 12 shows that, as a result of the phase adjustment, the phases of the input clock and the clock input to the DFF 17 are the same, and the video signal is in a relationship satisfying the setup / hold condition with respect to the DFF input clock. It is a timing chart. FIG. 12A shows a timing chart in the case where the phase of the video signal input and the clock input coincide with each other, and FIG. 12B shows the result of adjusting the phase so that the input clock and the DFF 17 are input. The timing chart in the case where the phases of the clocks to be matched match and the video signal is in a relationship satisfying the setup / hold condition with respect to the input clock of the DFF is shown.

  However, this method can compensate for a phase shift when there is only one clock input, but if there are multiple clock inputs, a delay occurs in the signal switching unit that switches between multiple clock inputs. . As a result of the clock delay occurring in the clock switching means, there arises a problem that it is not possible to compensate for the phase shift when there are a plurality of clock inputs. Therefore, Patent Document 1 and Patent Document 2 describe a phase compensation method when a plurality of clock inputs are switched.

JP-A-6-85803 JP-A-10-271102

  FIG. 13 shows an example of a signal processing apparatus when there are two clock inputs. The signal processing device 10 shown in FIG. 13 includes a clock switch 14, a PLL 11, a clock tree 16, and a DFF 17. The clock switch 14 is an example of clock switching means. The PLL 11 includes a phase comparator 12 and an oscillator 15 as in FIG. The PLL 11 in FIG. 13 can compensate for the phase shift caused by the clock tree 16, but cannot compensate for the phase shift caused by the clock switch 14. For this reason, a hold violation occurs in the DFF 17 and the output determination from the DFF 17 is delayed. In a circuit with a high signal frequency, even a slight delay in determining the output will have a large effect.

  Here, as a method of compensating for the phase shift due to the delay caused by the clock switch, there is a method of providing a delay buffer for the video signal input and inputting it to the DFF as shown in FIG. 14 to compensate for the phase shift. .

  The signal processing device 10 shown in FIG. 14 includes a clock switch 14, a PLL 11, a clock tree 16, a DFF 17, and a delay buffer 18. The PLL 11 includes a phase comparator 12 and an oscillator 15 as in FIG. The delay buffer 18 is a video input from the video signal input so that a hold violation does not occur in the DFF 17 in accordance with the phase delay generated in the clock switch 14 so that the phases of the video signal input and the clock input match. Delay the signal. By doing so, the phase of the input clock signal and the video signal can be matched so that no hold violation occurs in the DFF 17.

  However, since the delay buffer 18 has temperature dependence, there is a problem that the amount of delay varies depending on the temperature. Therefore, there is a problem that it is difficult to completely compensate for the phase shift. As the clock speed increases, the timing adjustment in the flip-flop is strictly required. Therefore, it is necessary to completely absorb the phase shift caused by the clock switching means and compensate the phase.

  Therefore, the present invention has been made in view of such problems, and an object of the present invention is to accurately compensate the clock phase regardless of the operating environment when there are a plurality of input clocks. An object of the present invention is to provide an input clock phase compensation device capable of

  In order to solve the above-described problems, according to an aspect of the present invention, there is provided an input clock phase compensation device, comprising at least two phase comparison units for detecting a phase difference between two clock signals, and at least two phase comparisons. A signal switching unit for switching and outputting one of the output signals from the phase comparison unit, and a signal switching unit for the output of the phase comparison unit. An oscillator for outputting a frequency corresponding to the output voltage, and the phase comparator compares the phase of the clock signal input from the outside with the clock signal output from the oscillator and outputs a differential signal. Provides a phase compensation device for an input clock, wherein the clock signal output from the signal switching unit is input and the clock signal is supplied to the phase comparison unit.

  According to such a configuration, the at least two phase comparison units compare the phases of the clock signal from the outside and the clock signal from the voltage control transmitter and output a differential signal, and the signal switching unit outputs from the phase comparison unit. One clock signal is switched and output from among the plurality of clock signals, and the oscillator outputs a clock signal having an appropriate phase corresponding to the output voltage from the phase comparison unit. As a result, according to the phase compensation device for the input clock in the first aspect of the present invention, the delay of the clock signal generated in the signal switching unit can be compensated, and when there are a plurality of input clocks, the clock accurately Can be compensated for.

  In order to solve the above-described problem, according to another aspect of the present invention, an input clock phase compensation device compares at least phase differences between two clock signals and operates so that the phases are equal. Including two PLLs and a signal switching unit provided at a subsequent stage of at least two PLLs and switching one of the clock signals output from the PLL. The PLL includes an external clock signal, A phase compensation device for an input clock, characterized in that the clock signal is output by comparing the phase with the clock signal output from the signal switching unit.

  According to such a configuration, the at least two PLLs compare the phases of the clock signal from the outside and the clock signal from the voltage control transmitter to output the clock signal, and the signal switching unit outputs a plurality of signals output from the PLL. One clock signal is switched and output from the clock signals. As a result, the input clock phase compensation device according to the second aspect of the present invention can also compensate for the delay of the clock signal generated in the signal switching unit, and can accurately detect the clock when there are a plurality of input clocks. The phase can be compensated.

  In order to solve the above-described problem, according to another aspect of the present invention, there is provided an input clock phase compensation device, comprising at least two phase comparison units for detecting a phase difference between two clock signals, and at least two phases. Provided between the subsequent stage of the comparison unit and the previous stage of the oscillator, and is provided at the subsequent stage of the signal switching unit and the signal switching unit that switches and outputs one of the output signals from the phase comparison unit. And a clock tree that distributes the clock signal, and the phase comparator has the same phase as the clock signal that is input from the outside and the clock signal that is distributed from the clock tree. The phase difference information is output by comparing the phase with the clock signal, and the oscillator outputs the clock signal based on the phase difference information output from the signal switching unit. Click of the phase compensation device is provided.

  According to such a configuration, the at least two phase comparison units compare the phases of the clock signal from the outside and the delayed clock signal from the clock tree, and the signal switching unit compares the plurality of clock signals output from the phase comparison unit. One clock signal is switched and output, and the oscillator outputs a clock signal having an appropriate phase corresponding to the output voltage from the phase comparator, and inputs the clock signal to the flip-flop via the clock tree. . As a result, the signal processing apparatus for the input clock according to the third aspect of the present invention can also compensate for the delay of the clock signal generated in the signal switching unit and the clock tree, and can accurately correct when there are a plurality of input clocks. The clock phase can be compensated for.

  In order to solve the above-described problem, according to another aspect of the present invention, there is provided an input clock phase compensation device, which includes at least two PLLs for detecting a phase difference between two clock signals, and subsequent stages of at least two PLLs. And a signal switching unit that switches and outputs one of the clock signals output from the PLL, and a clock tree that distributes the clock signal. The PLL includes an external clock signal and a clock tree. A phase compensation device for an input clock is provided, which compares the phase of a clock signal distributed from and a clock signal of the same phase and outputs the clock signal.

  According to such a configuration, the at least two PLLs compare the phases of the clock signal from the outside and the delayed clock signal from the clock tree and output the clock signal, and the signal switching unit has a plurality of clocks output from the PLL. One clock signal is switched and output from the signal, and the oscillator outputs a clock signal having an appropriate phase corresponding to the output voltage from the phase comparator, and the clock signal is sent to the flip-flop via the clock tree. input. As a result, the signal processing apparatus for the input clock according to the fourth aspect of the present invention can also compensate for the delay of the clock signal generated in the signal switching unit and the clock tree, and is accurate when there are a plurality of input clocks. The clock phase can be compensated for.

  As described above, according to the present invention, when there are a plurality of input clocks, it is possible to provide an input clock phase compensation device that can accurately compensate the clock phase regardless of the operating conditions. is there.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
FIG. 1 is an explanatory diagram showing a phase compensation device for an input clock according to the first embodiment of the present invention. As shown in FIG. 1, the input clock phase compensation device 110 according to the first embodiment of the present invention includes a first phase comparator 120, a second phase comparator 130, a switch 140, And an oscillator 150.

  In this embodiment, there are two input clocks. However, the present invention is not limited to this, and the number of input clocks may be three or more.

  The first phase comparator 120 is an example of a phase comparison unit, compares the phase of the clock signal from the first clock input with the clock output signal, and outputs phase difference information. That is, the phase difference information is output by comparing the difference between the phase of the clock signal from the first clock input and the clock output signal output from the oscillator 150. Similarly, the second phase comparator 130 is an example of a phase comparison unit. The phase difference information is output by comparing the phase of the clock signal from the second clock input and the clock output signal, that is, the phase difference of the clock output signal output from the oscillator 150. Here, the phase difference information may be a digital waveform or an analog voltage.

  The switch 140 is an example of a signal switching unit, and switches to either one of the phase difference information output from the first phase comparator 120 and the second phase comparator 130. That is, the switching device 140 switches to the one generated using the clock input that the system intends to use. The switcher 140 inputs the phase difference information from either the first phase comparator 120 or the second phase comparator 130 to the oscillator 150. Here, the oscillator 150 may be composed of, for example, a loop filter that converts phase difference information into a voltage and a VCO that varies the frequency according to the voltage output from the loop filter. In addition, a mode in which the phase comparator outputs an analog voltage is also possible. When the phase comparator outputs an analog voltage, the switch 140 uses an analog switch, and the oscillator 150 has only a VCO.

  The oscillator 150 changes the clock signal based on the phase difference information from the switch 140 and outputs it. When the output from the switch 140 is a digital signal, the oscillator 150 includes a loop filter that converts phase difference information into a voltage, and a VCO that varies the frequency according to the voltage output from the loop filter. When the output from the clock switch is an analog voltage, the oscillator 150 has only a VCO.

  FIG. 2 is an explanatory diagram showing a signal processing apparatus using the phase compensation apparatus for an input clock according to the first embodiment of the present invention. As shown in FIG. 2, the signal processing device 100 using the input clock phase compensation device according to the first embodiment of the present invention includes an input clock phase compensation device 110 and a plurality of flip-flops including a DFF 170. A clock tree 160 for distributing clocks. The input clock phase compensation device 110 includes a first phase comparator 120, a second phase comparator 130, a switch 140, and an oscillator 150.

  The first phase comparator 120 receives the clock signal input from the first clock input and the clock signal output from the oscillator 150 and delayed by the clock tree 160, and compares the phases of the two clock signals. Thus, the phase difference information is input to the switch 140.

  The second phase comparator 130 inputs the clock signal input from the second clock input and the clock signal output from the oscillator 150 and delayed by the clock tree 160, and compares the phases of the two clock signals. Thus, the phase difference information is input to the switch 140.

  The switcher 140 selects phase difference information with respect to the input clock to be used from the phase difference information output from the first phase comparator 120 and the second phase comparator 130 and inputs the selected phase difference information to the oscillator 150. .

  The oscillator 150 receives the phase difference information from the switch 140, controls the oscillation frequency according to the input information, outputs a clock signal of the controlled frequency, and inputs it to the clock tree 160. The clock tree 160 is for distributing the clock signal output from the oscillator 150 in order to input the clock signal to the DFF 170. The DFF 170 is an example of a flip-flop. In the present embodiment, a D-type flip-flop is used, but the present invention is not limited to such an example, and may be another form of flip-flop.

  When the clock signal output from the oscillator 150 passes through the clock tree 160, a phase difference occurs between the output clock signal from the oscillator 150 and the output clock signal after passing through the clock tree 160. Therefore, when an output clock signal after passing through the clock tree is applied to the DFF, a phase difference from the clock signal of the video signal input occurs, and a hold violation occurs in the DFF.

  Therefore, the clock signal after passing through the clock tree 160 is input to the first phase comparator 120 and the second phase comparator 130. The first phase comparator 120 compares the phases of the clock signal after passing through the clock tree 160 and the clock signal of the first clock input. Further, the second phase comparator 130 compares the phases of the clock signal after passing through the clock tree 160 and the clock signal of the second clock input. The first phase comparator 120 and the second phase comparator 130 each output phase difference information. The switch 140 selects a phase difference signal on the phase comparator side to which the clock to be used at present is input from the two clock inputs, and inputs it to the oscillator 150. For example, if the clock used as the system is a clock signal from the first clock input, the output of the first phase comparator 120 is selected, and if the clock used as the system is a clock signal from the second clock input, The output of the second phase comparator 130 is selected.

  As a result, the phase of the clock signal output from the oscillator 150 and passed through the clock tree 160 matches the phase of the video signal input clock signal. Accordingly, the DFF 170 satisfies the setup / hold condition, and the video signal data can be normally transferred.

  As described above, according to the phase compensation device for the input clock according to the first embodiment of the present invention, it is possible to compensate for the phase delay caused by the clock switcher and to normally transfer the signal from the outside. I can do it.

(Second Embodiment)
FIG. 3 is an explanatory diagram showing an input clock phase compensation device according to the second embodiment of the present invention. As shown in FIG. 3, the input clock phase compensator 210 according to the second embodiment of the present invention includes a first PLL 220, a second PLL 230, and a switch 240.

  The first PLL 220 controls the output clock according to the phase difference between the clock signal from the first clock input and the clock signal output from the switch 240.

  FIG. 4 is an explanatory diagram showing the internal structure of the first PLL 220. As shown in FIG. 4, the first PLL 220 includes a phase comparator 222 and an oscillator 224. The phase comparator 222 compares the clock signal of the clock input with the clock signal output from the oscillator 224 and then delayed, and outputs phase difference information. The oscillator 224 outputs a clock signal having a frequency controlled by the phase difference information. Here, the phase difference information may be a digital waveform or an analog voltage.

  Similarly, the output clock of second PLL 230 is controlled according to the phase difference between the clock signal from the second clock input and the clock signal output from switch 240. Since the internal structure of the second PLL is substantially the same as the internal structure of the first PLL, description thereof is omitted here.

  The switcher 240 is an example of a signal switching unit, and selects a clock to be used from the output clocks of the first PLL 220 and the second PLL 230. For example, when the clock used as the system is a clock signal from the first clock input, the output from the first PLL 220 is selected and output, and the clock used as the system is the clock from the second clock input. If it is a signal, the output from the second PLL 230 is selected and output.

  FIG. 5 is an explanatory diagram showing a signal processing device 200 using a phase compensation device for an input clock according to the second embodiment of the present invention. As shown in FIG. 5, the signal processing device 200 according to the second embodiment of the present invention includes an input clock phase compensation device 210 and a clock tree that distributes a clock to a plurality of flip-flops. In FIG. 5, a DFF 270 is shown as one of the plurality of flip-flops. The input clock phase compensation device 210 includes a first PLL 220, a second PLL 230, and a switcher 240.

  The first PLL 220 inputs the clock signal input from the first clock input and the clock signal output from the switch 240 and delayed by the clock tree 260, and outputs the clock signal according to the phase difference between the two. Input to the switch 240.

  The second PLL 230 receives the clock signal input from the second clock input and the clock signal output from the switch 240 and delayed by the clock tree 260, and outputs the clock signal according to the phase difference between the two. Input to the switch 240.

  The switcher 240 selects a clock to be used from the output clocks of the first PLL 220 and the second PLL 230, and outputs a clock signal.

  The clock tree 260 is for distributing the clock signal output from the clock switcher 240 in order to input the clock signal to the DFF 270. The DFF 270 is an example of a flip-flop. In the present embodiment, a D-type flip-flop is used, but the present invention is not limited to such an example, and may be another form of flip-flop.

  When the clock signal output from the clock switcher 240 passes through the clock tree 260, a phase difference occurs between the output clock signal from the phase compensator 210 and the output clock signal after passing through the clock tree 260. Therefore, when an output clock signal after passing through the clock tree 260 is applied to the DFF 270, a phase difference is generated between the DFF 270 and the clock signal input to the video signal, and a hold violation occurs in the DFF 270.

  Therefore, the output clock signal after passing through the clock tree 260 is input to the first PLL 220 and the second PLL 230. As a result of feedback that compares the phase of the output clock signal after passing through the clock tree 260 and the clock signal of each input and generates a clock signal based on the phase difference, two clocks input to the selected PLL The phase difference of the signal converges to zero. As a result, the phase of the selected input clock signal and the output clock signal of the clock tree converges to zero.

  As described above, the phase compensation apparatus for the input clock according to the second embodiment of the present invention can also compensate for the phase delay caused by the clock switcher, and can normally pass the signal from the outside.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, the phase compensation device according to the present invention can be applied not only to the phase compensation of the input clock signal but also to the phase compensation of the output clock signal. FIG. 6 is an explanatory diagram of a conventional clock output. As shown in FIG. 6, the signal processing device 30 that performs conventional clock output includes a PLL 31, a clock tree 36, and a DFF 37. The PLL 31 includes a phase comparator 32 and an oscillator 35.

  The phase comparator 32 compares the input clock signal from the clock input with the output signal from the clock tree 36 and inputs the phase difference information to the oscillator 35.

  The oscillator 35 receives the phase difference information output from the phase comparator 32, controls the oscillation frequency according to the input phase difference information, and outputs a clock signal having an internally controlled frequency. The clock tree 36 is for distributing the clock signal output from the oscillator 35. The DFF 37 receives a clock signal from the clock tree 36 and a video signal from an external video signal input (not shown), and outputs a video signal corresponding to the input signal to a video signal output.

  FIG. 7 is a timing chart showing the phase relationship between the clock input and the video signal. As shown in FIG. 7A, the phase of the input clock is controlled so as to satisfy the setup / hold condition between the input clock and the video signal at the time of clock input, but it passes through the clock tree 36. As a result, the clock is delayed, and as a result, the setup / hold condition is not satisfied between the video signal and the clock signal after passing through the clock tree 36 as shown in FIG. A hold violation occurs at.

  FIG. 8 shows a modification of the first embodiment of the present invention. A signal processing device 300 using a phase compensation device for an input clock according to a modification of the first embodiment of the present invention includes a phase compensation device 310 and a clock tree 360 that distributes a clock to a plurality of flip-flops. Including. In FIG. 8, a DFF 370 is shown as one of the plurality of flip-flops.

  The phase compensator 310 selects either the first clock input or the second clock input, obtains a phase difference from the output clock from the clock tree 360, and generates a clock signal according to the phase difference. . The phase compensation device 310 includes a first phase comparator 320, a second phase comparator 330, a switch 340, and an oscillator 350. Since the roles of the first phase comparator 320, the second phase comparator 330, the switch 340, the oscillator 350, and the clock tree 360 are substantially the same as those in the first embodiment, a detailed description will be given here. Omit. The DFF 370 is an example of a flip-flop. In the present embodiment, a D-type flip-flop is used, but the present invention is not limited to such an example, and may be another form of flip-flop.

  By inputting the input clock signal delayed by the clock tree 360 to the phase compensation device 310 again, the phase of the input clock signal matches the phase of the clock signal input to the DFF 370. Therefore, according to the modification of the first embodiment of the present invention, the phase at the clock input and the phase at the video signal output coincide with each other, so that information can be transmitted accurately.

  The present invention is applicable to an input clock phase compensation device and a signal processing device.

It is explanatory drawing which shows the phase compensation apparatus of the input clock which concerns on the 1st Embodiment of this invention. It is explanatory drawing of the signal processing apparatus using the phase compensation apparatus of the input clock which concerns on the 1st Embodiment of this invention. It is explanatory drawing which shows the phase compensation apparatus of the input clock which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which shows the structure of PLL used with the phase compensation apparatus of the input clock which concerns on the 2nd Embodiment of this invention. It is explanatory drawing of the signal processing apparatus using the phase compensation apparatus of the input clock which concerns on the 2nd Embodiment of this invention. It is explanatory drawing of the signal processing apparatus using PLL which concerns on a prior art. It is a timing chart in the signal processing apparatus using PLL which concerns on the prior art. It is explanatory drawing of the signal processing apparatus using the phase compensation apparatus of the input clock which concerns on the example of a change of the 1st Embodiment of this invention. It is explanatory drawing of the signal processing apparatus using PLL which concerns on a prior art. It is a timing chart in the signal processing apparatus using PLL which concerns on the prior art. It is explanatory drawing of the signal processing apparatus using PLL which concerns on a prior art. It is a timing chart in the signal processing apparatus using PLL which concerns on the prior art. It is explanatory drawing of the signal processing apparatus using PLL which concerns on a prior art. It is explanatory drawing of the signal processing apparatus using PLL which concerns on a prior art.

Explanation of symbols

100, 200, 300 Signal processor 110, 210, 310 Phase compensator 120, 320 First phase comparator 130, 330 Second phase comparator 140, 240, 340 Switcher 150, 350 Oscillator 160, 260, 360 Clock tree 170, 270, 370 DFF
220 First PLL
222 Phase comparator 224 Oscillator 230 Second PLL

Claims (4)

An input clock phase compensator:
At least two phase comparators for detecting a phase difference between the two clock signals;
A signal switching unit provided between the subsequent stage of the at least two phase comparison units and the previous stage of the oscillator, and switching and outputting one of the output signals from the phase comparison unit;
The oscillator provided at a subsequent stage of the signal switching unit and outputting a frequency according to an output voltage of the phase comparison unit;
Including
The phase comparison unit compares a phase of a clock signal input from the outside with a clock signal output from the oscillator and outputs a differential signal;
A phase compensation device for an input clock, wherein the oscillator receives the clock signal output from the signal switching unit and supplies the clock signal to the phase comparison unit. An input clock phase compensator:
At least two PLLs that compare the phase differences of the two clock signals and operate so that their phases are equal;
A signal switching unit provided at a subsequent stage of the at least two PLLs and switching one of the clock signals output from the PLL;
Including
The phase compensation device for an input clock, wherein the PLL compares the phases of an external clock signal and the clock signal output from the signal switching unit and outputs a clock signal. An input clock phase compensator:
At least two phase comparators for detecting a phase difference between the two clock signals;
A signal switching unit provided between the subsequent stage of the at least two phase comparison units and the previous stage of the oscillator, and switching and outputting one of the output signals from the phase comparison unit;
The oscillator provided at a subsequent stage of the signal switching unit and outputting a frequency according to the output of the phase comparison unit;
A clock tree for distributing clock signals;
Including
The phase comparison unit compares the phases of an externally input clock signal and a clock signal having the same phase as the clock signal distributed from the clock tree, and outputs phase difference information.
The input clock phase compensation apparatus, wherein the oscillator outputs a clock signal based on the phase difference information output from the signal switching unit. An input clock phase compensator:
At least two PLLs for detecting the phase difference between the two clock signals;
A signal switching unit provided at a subsequent stage of the at least two PLLs and switching one of the clock signals output from the PLL;
A clock tree for distributing clock signals;
Including
The PLL compares the phases of an external clock signal and a clock signal having the same phase as that of the clock signal distributed from the clock tree, and outputs a clock signal. .

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