JP2007164345A - Designing method for semiconductor integrated circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a designing method of a semiconductor integrated circuit for reducing errors caused due to influence of jitters and to provide the semiconductor integrated circuit. <P>SOLUTION: A first circuit block and a second circuit block are integrated in the same semiconductor integrated circuit, and an operating frequency of the second circuit block is adjusted to N times or 1/N times (2<SP>n</SP>times, preferably) that of the first circuit block. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for designing a semiconductor integrated circuit having a plurality of circuit blocks, and a semiconductor integrated circuit. In particular, the present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit in which the influence of jitter caused by the operation of a plurality of circuits is suppressed.

  Conventionally, a semiconductor integrated circuit in which a plurality of circuit blocks are integrated on the same semiconductor substrate has been proposed.

  For example, Patent Document 1 discloses a plurality of data transmission / reception circuits (USB control unit 1002, SAI circuit (serial I / F input / output to DAC and ADC) 1009 that use a clock having a frequency determined by the unified standard as a transmission / reception clock. ) The mounted semiconductor device is described. In this semiconductor device, oscillation circuits 1006 and 1007 and clock generators 1005 and 1008 are provided for each data transmission / reception circuit (see FIG. 5).

In Patent Document 2, in the data processing device, the frequencies of the clocks CK1 and CK2 supplied to the plurality of arithmetic modules 4 and 5 that receive the data D1 via the FIFOs 21 and 22 are made variable for the purpose of reducing power consumption. Is disclosed (see FIG. 6).
JP 2004-086555 A JP 09-282042 A

  In Patent Documents 1 and 2, different circuit blocks in the same semiconductor integrated circuit operate in synchronization with clocks having different frequencies. Each of these different circuit blocks applies voltage fluctuations to the power supply in a cycle synchronized with the respective clocks. This power supply voltage fluctuation causes jitter with respect to signals received or transmitted by other circuit blocks in the semiconductor integrated circuit.

  For this reason, jitter occurs at a random timing that is not synchronized with the clock of a signal processed by a certain circuit block in synchronization with a clock of a specific frequency, for example, a signal received or transmitted. As jitter occurs at random timing in this way, an error may occur in data transmission / reception.

  In particular, there is a high possibility that an error will occur in transmission / reception of data at a high data rate outside the semiconductor integrated circuit, specifically, for example, data transmission / reception with an external memory or data transmission / reception through a high-speed serial interface.

  It is an object of the present invention to provide a semiconductor integrated circuit design method and a semiconductor integrated circuit in which the occurrence of errors due to the influence of jitter is suppressed.

  In order to solve the above-described problems, the present invention provides a method for designing a semiconductor integrated circuit having a plurality of circuit blocks that operate in synchronization with a clock signal, and includes a first clock signal from the plurality of circuit blocks. The first circuit block that operates in synchronization with the second clock signal and the second circuit block that operates in synchronization with the second clock signal are selected, and the frequency of the second clock signal is set to the first clock signal. A design method of a semiconductor device is provided in which the frequency is changed to a third frequency that is N times or 1 / N times (N is an integer of 1 or more).

  Here, it is preferable that the first circuit block is a circuit block that receives or transmits first data in synchronization with the first clock signal via an external terminal of the semiconductor integrated circuit.

  More specifically, the second circuit block receives or transmits via the second external terminal of the semiconductor integrated circuit in synchronization with the data clock signal of the frequency before the change of the second clock signal. It is preferable that a data rate adjustment circuit is inserted between the second circuit block and the second external terminal together with the change to the third clock frequency. . Alternatively, whether the second circuit block receives data generated by processing the first data in the first circuit block from the first circuit block via a data rate adjustment circuit. Alternatively, it is preferably a circuit block that transmits data to be processed by the first circuit block to the first circuit block.

Furthermore, it is preferable that the third frequency is 2 ⁿ times (n is an integer) the frequency of the first clock signal.

  In order to solve the above-described problem, the present invention operates in synchronization with a clock signal having a first frequency, and transmits a first data signal synchronized with the clock signal having the first frequency via a first external terminal. Different from the second frequency, a first circuit block for receiving or transmitting in this way, a second external terminal to which a second data signal synchronized with a clock signal of the second frequency is input or output, and A second circuit block that operates in synchronization with a clock signal having a third frequency that is N times or 1 / N times the first frequency (N is an integer equal to or greater than 1); the second external terminal; A second data block provided between the second circuit block and included in the second data signal input to the second external terminal is transmitted to the second circuit block; or 2nd data from 2 circuit blocks Receiving and generating the second data signal, to provide a semiconductor integrated circuit and having a data rate adjustment circuit.

  The present invention also operates in synchronization with a clock signal having a first frequency, and receives or transmits a first data signal synchronized with the clock signal having the first frequency via a first external terminal. A second circuit block that operates in synchronization with a clock signal having a third frequency that is N times or 1 / N times (N is an integer equal to or greater than 1) the first frequency; Second data generated by processing the first data signal in the first circuit block is provided between the first circuit block and the second circuit block. Receiving and transmitting to the second circuit block, or receiving second data to be processed by the first circuit block from the second circuit block and transmitting to the first circuit block; Data rate To provide a semiconductor integrated circuit, characterized in that it comprises a circuit.

In the semiconductor integrated circuit design method and semiconductor integrated circuit of the present invention, the operating frequency of the second circuit block integrated in the same semiconductor integrated circuit is set to N with respect to the operating frequency of the first circuit block. Double or 1 / N times (more preferably ²ⁿ times). Thereby, the timing of jitter generation with respect to the operation of the first circuit block becomes constant, and the occurrence of errors can be suppressed.

  FIG. 1 is a configuration diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.

  The semiconductor integrated circuit 100 of FIG. 1 has a first data processing circuit 110 and a second data processing circuit 120 as first and second first circuit blocks. The first and second data processing circuits 110 and 120 are integrated on the same semiconductor substrate, and operate by receiving power supply from a common power supply wiring. The semiconductor integrated circuit 100 of FIG. 1 also has a first data input terminal 112, a first clock input terminal 114, a first output terminal 116, a second data input terminal 122, and a second clock input as external terminals. A terminal 124 and a second output terminal 126 are provided.

  A first input data signal is input to the first data input terminal 112. The first input data signal is a parallel data signal having a k-bit width, for example, synchronized with the first clock signal (first data clock signal). As a result, the first data processing circuit 110 receives the first input data signal via the first data input terminal 112 in synchronization with the first clock signal. The first data processing circuit 110 is supplied with the first clock signal via the first clock input terminal 114.

  The first data processing circuit 110 operates in synchronization with the first clock signal, processes the first data included in the first input data signal, and outputs the generated first output signal to the first data signal. Output from the output terminal 116.

  A second input data signal is input to the second data input terminal 122. The second input data signal is, for example, a k-bit width parallel data signal synchronized with the second clock signal. Then, the second data processing circuit 120 receives the second data included in the second input data signal through the data rate adjustment circuit 140, processes it, and generates the generated second output signal. Output from the second output terminal 126.

  Here, the frequency of the first clock signal (first clock frequency) is, for example, 100 MHz, whereas the frequency of the second clock signal (second clock frequency) is, for example, 75 MHz, which are different from each other. . Moreover, there is no relationship of N times or 1 / N times (N is a positive integer). However, in the semiconductor integrated circuit 100 of FIG. 1, the second clock signal is not supplied as it is to the second data processing circuit 120, but the frequency is converted to the third frequency by the clock frequency conversion circuit 130. The internal clock signal thus supplied is supplied from the internal clock wiring 138. Therefore, the second data processing circuit 120 operates in synchronization with the internal clock signal, that is, the clock signal having the third frequency.

  Specifically, in the semiconductor integrated circuit 100 of FIG. 1, the second clock signal is converted into an internal clock signal having a frequency of 100 MHz that is a frequency that is one time the first clock frequency. This is supplied to the data processing circuit 120. The clock frequency conversion circuit 130 is a combination of a PLL circuit block 134 and two frequency dividing circuits 132 and 136. The PLL circuit block 134 includes a phase comparison circuit, a voltage control oscillator, and the like, and forms a Phase Locked Loop in combination with the frequency dividing circuit 136. The frequency dividing ratios of the two frequency dividing circuits 132 and 136 (in the case of FIG. 1, the frequency dividing ratio of the previous frequency dividing circuit 132 is 3, and the frequency dividing ratio of the subsequent frequency dividing circuit 136 is 4. ) Is appropriately set, it is possible to generate an internal clock frequency having a desired ratio of frequency to the second clock frequency. A frequency conversion circuit using such a PLL circuit is well known, and detailed description thereof is omitted.

  Before considering the operation of the semiconductor integrated circuit 100 of FIG. 1, first, the second clock signal is directly supplied to the second data processing circuit 120 without providing the clock frequency conversion circuit 130, and the second data processing circuit is provided. Consider the case where 120 is operated in synchronization with the second clock signal. Here, the frequency of the second clock signal is different from the frequency of the first clock signal. Further, there is no relation of N times or 1 / N times (N is a positive integer) with respect to the first clock frequency. Therefore, the power supply voltage fluctuation due to the operation of the first data processing circuit 110 occurs at random timing with respect to the operation of the second data processing circuit 120.

  That is, the timing of occurrence of jitter generated in the signal processed by the first data processing circuit 110 due to the power supply voltage fluctuation generated by the operation of the second data processing circuit 120 is the same as that of the first data processing circuit 110. Random for movement. Thus, when jitter occurs at random timing, there is a high possibility that an error will occur.

  On the other hand, in the semiconductor integrated circuit 100 of FIG. 1, an internal clock signal having the same frequency as the first clock signal generated by the clock frequency conversion circuit 130 is supplied to the second data processing circuit 120. The Therefore, the second data processing circuit 120 operates in synchronization with the internal clock signal, that is, at the same frequency as the first data processing circuit 110. Accordingly, voltage fluctuations generated in the power supply by the operation of the second data processing circuit 120 occur at a constant timing with respect to the operation of the first data processing circuit 110.

  Therefore, the timing of the occurrence of jitter generated in the signal processed by the first data processing circuit 110 due to the power supply voltage fluctuation generated by the operation of the second data processing circuit 120 is the same as that of the first data processing circuit 110. Constant for operation. The occurrence of errors due to jitter that occurs at such a constant timing can be easily suppressed. Specifically, for example, in the reception of the first input data signal synchronized with the first clock signal in the first data processing circuit 110, the occurrence of an error can be effectively suppressed. As described above, in the semiconductor integrated circuit 100 of FIG. 1, the first and second input data signals processed in the first and second input data signals received in synchronization with the clock signals having different frequencies are processed. Although the data processing circuits 110 and 120 are integrated and operated by supplying power from a common power supply wiring, it is possible to suppress the occurrence of errors due to the influence of jitter.

  Further, in the semiconductor integrated circuit 100 of FIG. 1, data using a FIFO (First-in First-Out) memory 142 is provided between the second data input terminal 122 and the input terminal of the second data processing circuit 120. A rate adjustment circuit 140 is provided to adjust the data input timing to the second data processing circuit 120. Providing such a data rate adjustment circuit is not necessarily essential to the present invention. However, for example, when it is necessary to perform processing in the second data processing circuit 120 in a certain amount of data group, it is preferable to provide a data rate adjustment circuit. Further, when it is necessary to output the second output signal generated by the second data processing circuit 120 in synchronization with a clock signal having a frequency different from the internal clock frequency, the second data processing circuit 120 is used. It is preferable to provide a similar data rate adjustment circuit on the output side.

  In FIG. 1, the first clock signal and the second clock signal are shown as independent signals. Therefore, even if an internal clock signal having the same frequency as the first clock frequency is generated by the clock frequency conversion circuit 130, strictly speaking, the frequency of the internal clock signal is slightly different from the frequency of the first clock signal. There is a possibility. In this case, the timing with respect to the operation of the first data processing circuit of the occurrence of jitter due to the power supply voltage fluctuation generated by the operation of the second data processing circuit 120 is not strictly constant.

  In order to prevent such a slight timing shift and further suppress the occurrence of an error, for example, it is preferable to supply an internal clock signal generated from the first clock signal to the second data processing circuit 120. . In the example shown in FIG. 1, since the internal clock signal having the same frequency as the first clock signal is supplied to the second data processing circuit 120, in the simplest case, the first clock signal is used as it is. What is necessary is just to supply to the 2nd data processing circuit 120. As a result, the second data processing circuit 120 has an exactly same frequency as the first clock signal supplied to the first data processing circuit 110 and has the same phase (synchronized). Can be supplied.

  However, in reality, the first clock signal and the second clock signal are obtained by using a common reference signal generated by a common oscillation circuit provided on a circuit board on which the semiconductor integrated circuit 100 is mounted. Often it is generated. In such a case, the frequency of the first clock signal and the frequency of the second clock signal have an accurate ratio. Therefore, an internal clock signal having the same frequency as that of the first clock signal can be generated using the second clock signal.

  In the semiconductor integrated circuit 100 of FIG. 1, the first data processing circuit 110 is operated in synchronization with the first clock signal, and the second data processing circuit 120 has a frequency of the first clock signal. It was operated in synchronism with an internal clock signal having a frequency of 1 time. However, operating a plurality of circuit blocks integrated in a semiconductor integrated circuit in this way in synchronization with a clock signal having the same frequency is not essential for suppressing the influence of jitter.

The second circuit block is supplied with a clock signal having a third frequency N times or 1 / N times the frequency of the first clock signal supplied to the first circuit block. It is possible to operate in synchronization with a clock signal having a frequency of 3. Thereby, it is possible to suppress the influence of jitter on the first data signal that the first circuit block receives in synchronization with the first clock signal or transmits in synchronization with the first clock signal. . Here, N is an integer of 1 or more. Furthermore, by supplying a clock signal having a frequency ²ⁿ times the frequency of the first clock signal supplied to the first circuit block to the second circuit block and operating in synchronization with the clock signal, The influence of jitter can be suppressed. Here, n is an integer (0, a positive or negative integer).

  FIG. 2 is a flowchart showing an embodiment of a semiconductor integrated circuit design method of the present invention for designing a semiconductor integrated circuit as shown in FIG. 1, for example.

  In the semiconductor integrated circuit design method of FIG. 2, first, the system design of the entire semiconductor integrated circuit is performed (ST1). Then, a plurality of types of circuit blocks necessary for configuring the designed system are selected from the circuit block group prepared in the design library. Each of these plural types of circuit blocks operates in synchronization with a clock signal, and a standard clock frequency and an allowable clock frequency range in which the operation is possible are determined.

Next, a first circuit block is selected from these plural types of circuit blocks (ST2), and further a second circuit block is selected (ST3). Then, assuming that the first circuit block and the second circuit block are supplied with clock signals of the respective standard clock frequencies, the frequency of the first clock signal and the frequency of the second clock signal are: It is checked whether or not a specific relationship is satisfied (ST4). In the example shown in FIG. 2, the frequency of the second clock signal (second clock frequency) is N times or 1 / N times the frequency of the first clock signal (first clock frequency). Check whether or not. Here, N is a positive integer. Alternatively, the check condition can be whether the second clock frequency is 2 ⁿ times the first clock frequency. Here, n is an integer (0, a positive or negative integer).

  If the above relationship is not satisfied, the frequency of the second clock signal is changed so as to satisfy the above relationship within the allowable clock frequency range of the second circuit block. Further, a data rate adjustment circuit is added as necessary (ST5).

  Such processing is also performed for other circuit blocks selected to configure the system designed in ST1. Here, in FIG. 2, the second and subsequent circuit blocks, that is, the circuit blocks other than the first circuit block are collectively referred to as “second circuit block”. Then, a clock frequency check and a necessary clock frequency change process are performed for all circuit blocks (ST6), and the design of the semiconductor integrated circuit is completed.

  Here, it is arbitrary which of the plurality of circuit blocks integrated in the semiconductor integrated circuit is the first circuit block. However, if there is a circuit block that is likely to cause an error due to the influence of jitter among the plurality of circuit blocks, that is, has a small margin for the occurrence of the error, it is preferable to use it as the first circuit block. Thereby, the occurrence of errors in the first circuit block having a small error margin can be effectively suppressed.

  In addition, it is not always essential to check and change the clock frequency shown in ST4 and ST5 in FIG. 2 for all circuit blocks in the method of designing a semiconductor integrated circuit of the present invention. For example, circuit blocks with a low operating frequency and small fluctuations in the power supply voltage accompanying the operation, circuit blocks that receive power from a power supply wiring different from other circuit blocks, etc. may be excluded from the check. Is possible.

  Another example of the semiconductor integrated circuit of the present invention will be further described.

  FIG. 3 is a configuration diagram showing the configuration of another example of the semiconductor integrated circuit of the present invention.

  The semiconductor integrated circuit 200 of FIG. 3 includes a memory interface circuit 210 as a first circuit block, and a data processing circuit 220 and an output circuit 230 (230a, 230b, 230c) as a second circuit block. These first and second circuit blocks are arranged on the same semiconductor substrate and operate by being supplied with power from a common power supply wiring. In addition, the semiconductor integrated circuit 200 of FIG. 3 includes, as external terminals, a memory interface port 212, a clock output terminal 214, a reference clock input terminal 252, a data input terminal 222, first, second, and third video output terminals 234a, 234b and 234c, and first, second and third video output clock input terminals 236a, 236b and 236c.

  The semiconductor integrated circuit 200 in FIG. 3 performs various processes on the input video data received via the data input terminal 222 in the data processing circuit 220, and outputs video in various formats in the output circuits 230a, 230b, and 230c. Signals are generated and output via output terminals 234a, 234b, and 234c, respectively. Here, in the processing in the data processing circuit 220, it is necessary to temporarily store input video data, intermediate data generated during the processing, and the like. An external memory 240 is used as a storage area for this purpose.

  In the semiconductor integrated circuit 200 of FIG. 3, a memory interface circuit 210 is provided for data input / output to / from the external memory 240. The memory interface circuit 210 transmits / receives data to / from the external memory 240 via the memory interface port 212 and supplies a memory clock signal to the external memory 240 via the clock output terminal 214. Data transmission / reception via the memory interface port 212 is performed in synchronization with the memory clock signal.

  Here, in order to process video data in the data processing circuit 220, it is necessary to transmit and receive a large amount of data to and from the external memory 240 at high speed. For this reason, as the frequency of the memory clock signal, for example, a high frequency of 300 MHz or higher is employed. In such a large amount and high speed data transmission / reception, the error margin is small and there is a high risk of causing an error due to the influence of jitter or the like. Therefore, in the method of designing a semiconductor integrated circuit as shown in FIG. 2, the memory interface circuit 210 that transmits and receives a large amount of data at a high speed that easily causes an error is used as the first circuit block. It is preferable to adjust the operating frequency of the circuit block.

  The semiconductor integrated circuit 200 in FIG. 3 receives a reference clock signal from the outside via the reference clock input terminal 252. Then, using this reference clock signal, the internal clock generation circuit 254 generates an internal clock signal and supplies it to the memory interface circuit 210 via the internal clock signal wiring 256. Then, the memory interface circuit 210 supplies the supplied internal clock signal to the external memory 240 via the clock output terminal 214. That is, the internal clock signal is supplied as the first clock signal to the memory interface circuit 210 which is the first circuit block.

  Here, as the internal clock generation circuit 254 labeled “PLL” in FIG. 3, for example, the same one as the clock frequency conversion circuit 130 shown in FIG. 1 can be used. The internal clock generation circuit 254 generates an internal clock signal that is synchronized with the received reference clock signal and has a frequency different from that of the reference clock signal (usually higher than the reference clock signal).

In the semiconductor integrated circuit 200 of FIG. 3, the internal clock signal generated by the internal clock signal generation circuit 254 is further supplied to the frequency dividing circuit 260. Then, the frequency dividing circuit divides the frequency by 1 / N times (N is an integer of 2 or more), more preferably ²ⁿ times (n is a negative integer), thereby generating a low-speed clock signal. The generated low-speed clock signal is supplied to the data processing circuit 220, the output circuits 230a, 230b, 230c, etc. via the low-speed clock wiring 264. That is, in the semiconductor integrated circuit 30 of FIG. 3, the frequency dividing circuit 260 serves as a clock frequency conversion circuit. Then, the low-speed clock signal is supplied to the data processing circuit 220 and the output circuits 230a, 230b, and 230c, which are the second circuit block, as a clock signal having the third frequency.

In the semiconductor integrated circuit 200 of FIG. 3, the memory interface circuit 210 as the first circuit block is supplied with the internal clock frequency that is the clock signal of the first frequency, and operates in synchronization with the internal clock signal. . On the other hand, the data processing circuit 220, which is the second circuit block, divides the internal clock frequency by 1 / N times (N is an integer of 2 or more), more preferably ²ⁿ times (n is negative). A low-speed clock signal, which is a third frequency clock signal, is supplied and operates in synchronization with the low-speed clock signal. Therefore, jitter due to power supply voltage fluctuations generated by the operation of the data processing circuit 220 occurs at a fixed timing with respect to the operation of the memory interface circuit 210. For this reason, it is possible to suppress the occurrence of errors in the processing of the memory interface circuit 210 due to jitter caused by the operation of the data processing circuit 220. In particular, the occurrence of errors in data transmission / reception with the external memory 240 having a small error margin can be effectively suppressed.

Here, the data processing circuit 220 for processing the video data is required to have a high processing capability, and thus may cause a large fluctuation in the power supply voltage. Therefore, the operation frequency is adjusted to 1 / N times (N is an integer of 2 or more), more preferably 2 ⁿ times (n is a negative integer), that of the memory interface circuit 210. There is a high need to prevent errors.

  In the semiconductor integrated circuit 200 of FIG. 3, a FIFO 216 is further provided as a data rate adjustment circuit between the memory interface circuit 210 and the data processing circuit.

  In the semiconductor integrated circuit 200 of FIG. 3, the output circuits 230a, 230b, and 230c that are the other second circuit blocks are also supplied to the low-speed clock signal that is the third frequency clock signal generated by the frequency divider circuit 260. Is supplied. Accordingly, these output circuits 230a, 230b, and 230c also operate in synchronization with the low-speed clock signal. For this reason, it is possible to suppress the occurrence of errors in the memory interface circuit 210 due to jitter caused by power supply voltage fluctuations generated by these output circuits 230a, 230b, and 230c.

  In the semiconductor integrated circuit 200 of FIG. 3, the output circuits 230a, 230b, and 230c each generate video signals to be supplied to different devices. For example, a video signal for video, a video signal for television, and a video signal for personal computer. Such a video signal needs to be transmitted in synchronization with the clock frequency of the second frequency defined in each standard. Therefore, in a conventional semiconductor integrated circuit, an output circuit for generating such a video signal is generally operated at a clock frequency determined by each standard. However, the operating frequency of these output circuits cannot be kept in a relationship of N times or 1 / N times (N is an integer of 1 or more) with respect to the operating frequency of the memory interface circuit 210. There is a high probability that an error will occur.

  Therefore, in the semiconductor integrated circuit 200 of FIG. 3, the output circuits 230a, 230b, and 230c supply a low-speed clock signal that is a third-frequency clock signal obtained by dividing the internal clock signal supplied to the memory interface circuit 210. The operation was performed in synchronization with the low-speed clock signal. A data rate adjustment circuit 232 including FIFOs 232a, 232b, and 232c is provided on the output side of these output circuits 230a, 230b, and 230c. Then, a clock signal having a second frequency determined by each standard is supplied to the output side of these FIFOs 232a, 232b, 232c, and the video signals generated by the respective output circuits 230a, 230b, 230c The video output terminals 234a, 234b, and 234c, which are external terminals, are output (transmitted) in synchronization with the clock signals of the second frequencies.

  FIG. 4 is a block diagram showing still another example of the semiconductor integrated circuit of the present invention.

  The semiconductor integrated circuit 300 of FIG. 4 includes a receiver circuit 310 as a first circuit block and a data processing circuit 320 as a second circuit block. In addition, an input terminal 312 and an output terminal 322 are provided as external terminals. In the semiconductor integrated circuit 300 of FIG. 4, the data processing circuit 320 performs various processes on the signal received by the receiver circuit 310 via the input terminal 312, and the resulting signal is sent via the output terminal 322. Output. Here, the receiver circuit 310 and the data processing circuit 320 are integrated on the same semiconductor substrate and operate by receiving power supply from a common power supply wiring.

  In the receiver circuit 310, a line receiver 314, a clock data recovery (CDR) circuit 316, and a deserializer 318 are provided. The line receiver 314 receives a serial data signal input via the input terminal 312. The clock data recovery circuit 316 shapes the serial data signal received by the line receiver 314 and extracts the clock signal from the serial data signal. The deserializer 318 receives the serial data signal shaped by the clock data recovery circuit 316 and the extracted clock signal. The deserializer 318 converts the received serial data signal into a parallel data signal having a predetermined bit width (for example, 8 bit width) and outputs the parallel data signal through the internal data wiring 324. The deserializer 318 also divides the clock signal extracted by the clock data recovery circuit 316 by a ratio (for example, 8) corresponding to the bit width, generates an internal clock signal, and outputs it through the internal clock wiring 326.

  As described above, the receiver circuit 310 receives the serial data signal synchronized with the clock signal, rearranges the data (first data) included in the serial data signal, and generates a parallel data signal. . The receiver circuit 310 further extracts a clock signal from the received serial data signal, divides it by a predetermined ratio, and generates an internal clock signal.

  Here, the serial data signal received by the receiver circuit 310 is a signal synchronized with a clock signal having a high frequency exceeding 1 GHz. The reception of a data signal synchronized with such a high frequency is easily affected by jitter. Therefore, in the design of the semiconductor integrated circuit in the flow as shown in FIG. 2, it is preferable that the receiver circuit 310 is the first circuit block. In this case, the clock signal extracted by the clock data recovery circuit 316 from the serial data signal is the clock signal having the first frequency.

The data processing circuit 320, which is the second circuit block, has 1 / N times (N is an integer of 2 or more), more preferably 2 ⁿ times (N is an integer greater than or equal to) the clock signal extracted by the clock data recovery circuit 316. A clock signal having a third frequency (n is a negative integer) is supplied. Then, the operation of the data processing circuit 320 is synchronized with the clock signal having the third frequency. As a result, the timing of jitter generation due to power supply voltage fluctuations generated by the operation of the second circuit block becomes constant with respect to the operation of the receiver circuit 310, which is the first circuit block, and an operation error of the receiver 310 occurs. It is suppressed. In particular, the occurrence of errors in serial data signal reception is suppressed.

  Specifically, in the semiconductor integrated circuit 300 of FIG. 4, the data processing circuit 320 as the second circuit block converts the data (second data) included in the parallel data signal generated by the receiver circuit 310 into data The data is received via a FIFO 328 that is a rate adjustment circuit. The data processing circuit 320 is also supplied with a low-speed clock signal from the low-speed clock wiring 332. This low-speed clock signal is generated by dividing the internal clock signal generated by the receiver circuit 310 at a predetermined ratio by the frequency dividing circuit 330 which is a clock frequency conversion circuit.

Here, the frequency dividing ratio of the frequency dividing circuit 330 is appropriately set in consideration of the frequency dividing ratio in the clock data recovery circuit 316. Accordingly, the frequency of the low-speed clock signal (third frequency) is 1 / N times (N is an integer of 2 or more) compared to the frequency of the internal clock signal (first frequency) generated by the receiver circuit 310. More preferably, it is ²ⁿ times (n is a negative integer).

  The semiconductor integrated circuit and the method for designing the semiconductor integrated circuit according to the present invention have been specifically described according to the embodiments. However, the semiconductor integrated circuit and the method for designing the semiconductor integrated circuit of the present invention are not limited to the above-described embodiments, and it goes without saying that various improvements and modifications are possible.

It is a block diagram which shows one Embodiment of the semiconductor integrated circuit of this invention. It is a flowchart which shows one Embodiment of the design method of the semiconductor integrated circuit of this invention. It is a block diagram which shows other one Embodiment of the semiconductor integrated circuit of this invention. It is a block diagram which shows another one Embodiment of the semiconductor integrated circuit of this invention. It is a block diagram which shows an example of the conventional semiconductor integrated circuit. It is a block diagram which shows the other example of the conventional semiconductor integrated circuit.

Explanation of symbols

100, 200, 300 Semiconductor integrated circuit 110, 210, 310 First circuit block 120, 220, 230, 320 Second circuit block 130, 260, 330 Clock frequency conversion circuit 140, 216, 232, 328 Data rate adjustment circuit 112, 114, 116, 122, 124, 126, 212, 214, 222, 234, 236, 252, 312, 322 External terminal

Claims (8)

A method of designing a semiconductor integrated circuit having a plurality of circuit blocks each operating in synchronization with a clock signal,
A first circuit block that operates in synchronization with a first clock signal and a second circuit block that operates in synchronization with a second clock signal are selected from the plurality of circuit blocks,
The frequency of the second clock signal is changed to a third frequency that is N times or 1 / N times the frequency of the first clock signal (N is an integer of 1 or more). Design method.   2. The circuit block according to claim 1, wherein the first circuit block receives or transmits first data in synchronization with the first clock signal via an external terminal of the semiconductor integrated circuit. The semiconductor integrated circuit design method described.   A circuit for processing data received or transmitted by the second circuit block in synchronization with a data clock signal having a frequency before the change of the second clock signal via the second external terminal of the semiconductor integrated circuit. And a data rate adjusting circuit is inserted between the second circuit block and the second external terminal together with the change of the second clock signal to the third frequency. A method for designing a semiconductor integrated circuit according to claim 2.   The second circuit block receives data generated by processing the first data in the first circuit block from the first circuit block via a data rate adjustment circuit; or 3. The method of designing a semiconductor integrated circuit according to claim 2, wherein the circuit block is a circuit block that transmits data to be processed by the first circuit block to the first circuit block. 5. The method of designing a semiconductor integrated circuit according to claim 1, wherein the third frequency is ²ⁿ times (n is an integer) the frequency of the first clock signal. A first circuit block that operates in synchronization with a clock signal of a first frequency and receives or transmits a first data signal synchronized with the clock signal of the first frequency via a first external terminal;
A second external terminal to which a second data signal synchronized with a clock signal having a second frequency is input or output;
A second circuit block that is different from the second frequency and operates in synchronization with a clock signal having a third frequency N times or 1 / N times the first frequency (N is an integer of 1 or more). When,
Provided between the second external terminal and the second circuit block, the second data contained in the second data signal input to the second external terminal is transferred to the second circuit block. A semiconductor integrated circuit, comprising: a data rate adjusting circuit that transmits or receives second data from the second circuit block and generates the second data signal. A first circuit block that operates in synchronization with a clock signal of a first frequency and receives or transmits a first data signal synchronized with the clock signal of the first frequency via a first external terminal;
A second circuit block that operates in synchronization with a clock signal having a third frequency that is N times or 1 / N times the first frequency (N is an integer of 1 or more);
Second data provided between the first circuit block and the second circuit block and generated by processing the first data signal in the first circuit block is converted to the first circuit. Receive from the block and transmit to the second circuit block, or receive second data to be processed by the first circuit block from the second circuit block and transmit to the first circuit block A semiconductor integrated circuit comprising a data rate adjusting circuit. 8. The semiconductor integrated circuit according to claim 6, wherein the third frequency is 2 ⁿ times the first frequency (n is an integer).

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