JP2007189513A - Clamp circuit and test signal generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a clamp voltage is fluctuated due to dynamic resistance to generate a bump on a clamped waveform at a clamp circuit using a Zener diode, and a pulse width is shortened or a feedback loop performance becomes unstable at a clamp circuit of a conventional feedback system due to delay for turning off a surge absorption semiconductor device, thereby, to provide a clamp circuit and a test signal generator capable of generating a flat and accurate load dumping surge test voltage with proper repeatability. <P>SOLUTION: An output of a window comparator with a first reference voltage and a second reference voltage inputted thereinto is adopted as a loop performance reference voltage for a feedback loop circuit. A detected voltage of a load dumping surge waveform is feedback controlled into a voltage width range specified by the two reference voltages, and a flat clamped waveform is acquired. Since the loop performance reference voltage is maintained at substantially constant, loop performance becomes stable at wide range of surge voltage and surge absorption current. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clamp circuit and an apparatus for generating a test signal. More specifically, the present invention relates to a clamp circuit used in a test signal generator such as an in-vehicle electronic device.

  In a vehicle-mounted electronic device that operates by inputting a power supply voltage from a vehicle-mounted battery, a surge occurs when the power-source terminal of the vehicle-mounted battery is separated for some reason during traveling. This surge is also called a load dump surge. The in-vehicle electronic device needs to have a predetermined resistance against the load dump surge. In order to evaluate the reliability of the in-vehicle electronic device, when testing the resistance against the load dump surge, it is necessary to apply a prescribed test signal to the device under test.

  FIG. 2 is a diagram illustrating an example of a test signal waveform defined by an international standard. 2a and 2b are Test Pulse 5a and Test Pulse 5b defined by ISO (Non-Patent Document 1), respectively. In the present specification, for the sake of simplicity, they are referred to as a test pulse 5a and a test pulse 5b. These test signals are well known and will not be described in detail here. The test pulse 5b is obtained by clamping the test pulse 5a with a predetermined threshold (clamp voltage) level. In FIG. 2a and FIG. 2b, td represents the duration of the pulse and is also called the wave tail length.

  Since the reliability test inherently applies a great stress to the device under test, the reliability test is often performed only once. The above test signal applied to the device under test by simulating a load dump surge needs to generate a signal faithful to a prescribed waveform. That is, it is required to stably generate the maximum voltage value and duration (wave tail length td) in the test signal waveform with good reproducibility.

  A specific method for generating the test signal waveforms of the test pulse 5a and the test pulse 5b is also exemplified in the ISO international standard, and conventionally a configuration such as a capacitor charge / discharge system and a clamp circuit is known.

  FIG. 3 is a diagram illustrating a configuration of a load dump surge generation circuit using charge / discharge of a capacitor. With this circuit, the test pulse 5a can be generated. The charge charged in the capacitor 26 from the high voltage source 21 through the charging resistor 22 is discharged by closing the switch 28, and the test pulse 5 a can be generated at both ends of the resistor 25. The pulse width can be adjusted by the resistors 23 and 25, and the pulse rise time can be adjusted by the inductor 29 (see Non-Patent Document 2). The voltage value of the high voltage source 21 corresponds to, for example, the peak height Us in the surge voltage waveform shown in FIG.

  FIG. 4 is a diagram showing a clamp circuit using a Zener diode. This is a clamp circuit that uses the constant voltage characteristic of a Zener diode, and is well known (see Non-Patent Document 1). The test pulse 5b can be formed by clamping the surge waveform using the clamp circuit of FIG. For example, as shown in FIG. 5, the waveform of the test pulse 5b can be obtained at the output terminal by connecting the clamp circuit of FIG. 4 in parallel to the output terminal of the surge generating circuit of FIG.

  As another load dump surge waveform generation method, a method using a power amplifier is known. In this method, a waveform similar to the target load dump surge waveform is input as the control signal input of the amplifying element, amplified to a predetermined test signal voltage / current by a power amplifier (amplifying element), and the test signal waveform Is generated.

ISO 7637-2: 2004 Second edition, 2004-06-15, Road vehicles-Electrical disturbances from conduction and coupling IEC61000-4-5 Edition 1.1 2001-04

  However, the conventional load dump surge test signal generation method has various problems as described below. In the case of the load dump surge generator configured as shown in FIG. 5, the Zener voltage itself fluctuates due to a sudden increase in Zener current at the peak portion of the surge waveform clamped by the Zener diode in the clamp circuit. Since a Zener diode has a finite operating resistance in the Zener operating region, an ideal constant voltage characteristic cannot be obtained in reality. When a voltage higher than a certain voltage is applied to the Zener diode, the operating resistance rapidly decreases, and a Zener voltage depending on the current value flowing through the Zener diode is generated. When the load dump surge test signal of the test pulse 5b is formed, a high voltage is applied to the clamp circuit when a threshold voltage (clamp voltage) is exceeded, and a large current flows through the Zener diode. For this reason, the influence of the operation resistance mentioned above becomes remarkable. It is difficult to obtain a flat ideal clamp waveform as shown in FIG.

  FIG. 6 is a diagram for explaining a problem that occurs in a conventional load dump surge waveform generation circuit. FIG. 6a shows the waveform of the test pulse 5a in the ISO standard. FIG. 6b shows the waveform of an ideal test pulse 5b when the test pulse 5a is clamped by an ideal clamp circuit. Actually, the operating resistance of the Zener diode is dynamically changed to cause a hump as shown in part A of FIG. 6c. Therefore, it is difficult to obtain a flat clamping characteristic.

  Furthermore, when a load dump surge is generated by the capacitor charge / discharge surge generating circuit as shown in FIG. 5, the energy of the electric charge charged in the capacitor 26 is consumed by the operating resistance of the Zener diode in the clamp circuit, As shown in part B of FIG. 6c, there also arises a problem that the wave tail length is shortened. The shortening amount of the wave tail length changes depending on the peak voltage value of the surge voltage, the target length of the wave tail length, the impedance condition of the device under test, its variation, and the like. Therefore, it is difficult to generate a surge waveform having a predetermined shape with high reproducibility. In addition, when using the load dump surge generation circuit of FIG. 5, it is necessary to adjust the wave tail length setting value in consideration of the shortening amount of the wave tail length in accordance with the test voltage to be applied and the individual DUTs. Sometimes it becomes. This adjustment operation is troublesome and complicated, and there is a possibility that the DUT is destroyed due to this adjustment operation.

As a method for generating a load dump surge waveform that solves such a problem, a clamp circuit using feedback control has been considered. FIG. 7 is a diagram illustrating a configuration of a clamp circuit using feedback control. When the load dump surge test signal of the test pulse 5a is input to the input terminal, the input surge voltage is divided by the resistors 31 and 32. The divided surge voltage is input to the inverting input terminal of the comparator 34, and the reference voltage V _L 33 is connected to the non-inverting input terminal of the comparator 34. The output of the comparator 34 is inverted and amplified by the amplifier 35 and then connected to the control input terminal of the surge absorbing semiconductor element 36. When the divided surge voltage becomes larger than the reference voltage 33, the surge absorbing semiconductor element 36 is turned on, the surge voltage is absorbed through the surge absorbing semiconductor element 36 and the resistor 37, and the output voltage is maintained at a predetermined clamp voltage. To work.

  However, even when the clamp circuit of FIG. 6 is used instead of the clamp circuit using the Zener diode, there are still the following problems. In general, a semiconductor device can be controlled at high speed when the operation state of the device is turned on. On the other hand, when the operation state is changed from on to off, the control response is relatively slow. When the load dump surge is to be shaped into a clamp waveform, the surge absorbing semiconductor element 36 is a power transistor, power FET, or the like that operates at a high voltage and a large current. The delay time when changing the operating state from on to off is particularly large. Due to this delay time, the charge of the capacitor 26 of the surge generating circuit is discharged before the surge absorbing semiconductor element 36 returns from the on state to the off state. For this reason, the problem that the wave tail length shown in FIG. The shortening of the wave tail occurs similarly even in the case of a system using a power amplifier that can supply a relatively larger absorption current.

Therefore, when trying to widen the feedback loop characteristics in order to compensate for the response delay when trying to switch off the semiconductor element, there is a problem that the loop operation becomes unstable and oscillation occurs in the worst case. . In order to increase the bandwidth, it is possible to use a transistor 36 that switches at high speed or a broadband operational amplifier. However, placing broadband loop components in the feedback circuit leads to instability of the loop operation. The conditions of the DUT to which the load dump surge is applied vary, and it must be ensured that a load dump surge waveform can be generated with high reproducibility over a wide range of peak voltage, clamp voltage, and absorption current conditions. For example, stable operation must be ensured over a wide range of 50 to 200 V applied to the surge absorbing semiconductor element and a current flowing to the surge absorbing semiconductor element of 5 to 400 A. In general, the range of the control voltage (for example, gate voltage) for turning on and off the semiconductor element 36 is very narrow, and the above-described clamping operation is performed over all the conditions of the operating voltage and operating current of a wide range of semiconductor elements as described above. It was difficult to design a loop to achieve this normally. This is because the on / off control characteristics of the semiconductor element also vary depending on the voltage / current operation state of the surge absorbing semiconductor element.
In the method of generating a load dump surge using a power amplifier, the surge source impedance (Zsurge) and the impedance of the DUT to which the surge is applied (the voltage clamped by Zeut is divided and a predetermined surge It was also difficult to apply a voltage stably and reproducibly to the device under test.

  As described above, a test voltage generator that generates a load dump surge waveform that satisfies international standards with high reproducibility regardless of test setting conditions and conditions of the device under test has not yet been realized. The present invention has been made in view of the problems as described above, and the object of the present invention is to provide a clamp circuit capable of stably generating a load dump surge test signal waveform satisfying international standards with high reproducibility. And providing a test signal generator.

  In order to achieve such an object, the present invention provides a clamp circuit for generating a signal in which a surge voltage signal is clamped to a predetermined threshold voltage, wherein the predetermined threshold voltage is provided. And a second reference voltage higher than the first reference voltage are input, and a surge detection voltage proportional to the surge voltage is represented by the first reference voltage and the second reference voltage. A dynamic loop operation reference voltage generating means for outputting a predetermined dynamic loop operation reference voltage when the voltage is between, and the surge voltage signal is applied, and the surge voltage is greater than the predetermined threshold voltage. Surge voltage absorbing means for absorbing the surge voltage according to the control of the surge absorption control voltage input to the surge absorption control terminal, the dynamic loop operation reference voltage and the surge A feedback circuit for comparing the surge detection voltage proportional to the pressure and outputting the surge absorption control voltage to the surge voltage absorption means, wherein the surge detection voltage increases based on the result of the comparison The surge voltage absorbing means operates to short-circuit the surge voltage and absorb the surge voltage when changing in the direction, and opens the surge voltage absorbing means when the surge detection voltage changes in the decreasing direction. Generating the surge absorption control voltage that operates to stop absorption of the surge voltage.

  According to a second aspect of the present invention, in the first aspect of the invention, the dynamic loop operation reference voltage generating means includes a first comparator to which the first reference voltage and the surge detection voltage are input, and the A window comparator comprising a second reference voltage and a second comparator to which the surge detection voltage is input.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the surge voltage absorbing means applies the surge voltage between a drain and a source, and the surge absorption control voltage is applied to the gate. It is a MOSFET to be applied.

  According to a fourth aspect of the present invention, in the invention according to the first or second aspect, the surge voltage absorbing means is configured such that the surge voltage is applied between a collector and an emitter, and the surge absorption control voltage is based on the base. It is a transistor to be applied.

  The invention according to claim 5 is configured by connecting the clamp circuit according to any one of claims 1 to 4 to a surge output terminal of a load dump surge generating circuit of a power amplifier system. This is a load dump surge voltage generator.

  As described above, according to the present invention, it is possible to provide a clamp circuit and a test signal generator capable of stably generating a load dump surge test signal waveform satisfying international standards with high reproducibility.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present invention, as the reference voltage of the feedback control circuit, the first reference voltage and the second reference voltage are provided, and the clamp voltage is controlled within a voltage range of a certain width between the two reference voltages. It is characterized in that a stable load dump surge test signal can be generated.

  FIG. 1 is a configuration diagram of a load dump surge test signal device according to an embodiment of the present invention. The load dump surge test signal generator according to the present invention includes a surge voltage generation circuit unit 20 and a clamp circuit 10. The above-described test test pulse 5a is output from the surge voltage generation circuit 20, and this test pulse 5a is clamped by the clamp circuit 10 of the present invention and operates to output the test pulse 5b.

  The surge generation circuit 20 is a power amplifier type surge generation circuit. The power source 21 is connected to a charging capacitor 26 through a charging resistor 22. The resistor 22 is connected to the output control semiconductor amplifying element 27, and a surge output voltage is output through a saddle type resistor network composed of resistors 23, 24, and 25. The resistor 24 is a surge current limiting resistor, and is usually set in the range of 0.5 to 8Ω. The semiconductor element 27 can be, for example, an FET. In this case, the resistor 22 and the drain of the FET 27 are connected, and the source of the FET 27 is connected to the resistor 23. The resistors 23 and 25 are for stabilizing the surge voltage by preventing the source of the FET 27 from being opened. A control signal is input to the gate of the FET 27. By inputting a control signal similar to the target surge voltage waveform as this control signal, a desired surge output waveform is output to the output terminal of the surge generation circuit 20. The voltage when the FET 27 is completely turned on corresponds to the peak voltage of the surge waveform. When the output surge waveform changes at high speed, the capacitor 26 operates so that a desired surge waveform can be obtained by discharging the power from the capacitor 26 when the power supply from the power source 21 is not in time.

The clamp circuit 10 operates to clamp the test pulse 5 a output from the surge generation circuit 20. The clamp circuit 10 is configured to be connected in parallel to the output of the surge generation circuit 20. When the surge voltage exceeds a certain threshold voltage (clamp voltage), feedback control is performed by the clamp circuit 10 so that the surge voltage becomes a constant voltage, and as a result, a clamped test pulse 5b is obtained at the output terminal Vout. .
The surge voltage input to the clamp circuit 10 is divided by the resistor 6 and the resistor 7 into a voltage in a range that can be easily handled by a feedback circuit described later. A branch point A of the resistors 6 and 7 is connected to the input of the amplifier 1. The output of the amplifier 1 is connected to the inverting input terminal of the comparator 4. Further, the branch point A of the resistors 6 and 7 is also connected to the window comparator 50. The voltage dividing circuit including the resistors 6 and 7 has a function of detecting a surge voltage that is a control target in order to perform feedback control. As long as the function of detecting the surge voltage can be achieved, the circuit is not limited to the resistance voltage dividing circuit, and can be realized by other configurations. It is only necessary to extract a part of the surge voltage, detect an instantaneous fluctuation of the input surge waveform to the clamp circuit 10, and supply a detection voltage proportional to the surge voltage to the feedback circuit described below.

The window comparator 50 includes a comparator 2 and a comparator 3, and has a configuration in which two comparators are connected in parallel. A first reference voltage V _L 12 is connected to the half-turn input terminal of the comparator 3. A second reference voltage V _h 11 is connected to the non-inverting input terminal of the comparator 2. The branch points A of the resistors 6 and 7 are connected to the inverting input terminal of the comparator 2 and the non-inverting input terminal of the comparator 3, respectively. The outputs of the comparator 2 and the comparator 3 are connected in common and connected to the non-inverting input terminal of the comparator 4 as the output of the window comparator 50.

  The output of the comparator 4 is connected to the input of the amplifier 5, and the output of the amplifier 5 is connected to the control terminal of the surge absorbing semiconductor element 9. The surge absorbing semiconductor element 9 is composed of, for example, an FET or a transistor. The surge absorbing semiconductor element 9 is connected to the output end of the surge generating circuit 20 in parallel via a resistor 8 in series. As an example, when the surge absorbing semiconductor element 9 is an FET, the drain of the FET 9 is connected to the terminal side where the peak voltage of the surge generating circuit 20 appears, and the source is connected to the ground side via the resistor 8.

  The voltage dividing circuit using the resistors 6 and 7 described above, the amplifier 1, the comparator 4, and the amplifier 5 constitute a feedback circuit that feedback-controls the surge voltage to be controlled, and each is a loop component. The surge absorbing semiconductor 9 is a control means, but may be included in one of the loop components of the feedback circuit. In FIG. 1, for the sake of simplicity, components (resistors, capacitors, etc.) for setting the operating point and gain of each loop component are not shown.

  FIG. 9 is a diagram for explaining operation waveforms of each part of the clamp circuit 10. The operation of the load dump surge test signal generator according to the present invention will be described below. The basic operation of the clamp circuit 10 is based on feedback control. The operation differs depending on the voltage range of the surge voltage input to the clamp circuit 10. In addition, the waveform of each part that can be observed when the feedback operation is working is a waveform in a steady state after the control is achieved. Therefore, the operation will be described while comparing the state assumed that the feedback control is not performed and the state where the feedback control is working.

  FIG. 9A is a diagram illustrating a voltage waveform at the branch point A of the resistors 6 and 7 when the clamp circuit 10 is not performing the feedback control operation. As will be described later, when the feedback control is not working dynamically, the surge absorbing semiconductor element 9 remains off. Taking the FET as an example, the drain and source of the FET are open. Therefore, even at the point A, it is observed as a surge detection voltage similar to the surge waveform output from the surge generation circuit 20. However, the absolute value of the voltage value is divided by the ratio of the resistance values of the resistors 6 and 7, so that the amplifier 1, the amplifier 5, the comparator 4, the comparator 2, and the comparator 3 operate stably. It has been converted to a voltage range.

FIG. 9c is a diagram for explaining the operation of the window comparator. The waveform at the output point B of the window comparator 50 when the clamp circuit 10 is not performing the feedback control operation is shown. Therefore, they are common in that feedback control is not working, and FIGS. 9a and 9c are in a corresponding relationship. When the input voltage to the window comparator 50 is between the first reference voltage V _L 12 and the second reference voltage V _h 11, the output of the window comparator 50 is H. Here, the second reference voltage V _h is higher than the first reference voltage V _L , and both have a relationship of V _L <V _h . As shown in FIG. 9c, only when it is in the range of V _h voltage at the branch point A of the aforementioned from V _L, the output of the window comparator 50 becomes H (B point).

Next, the operation in a state where the clamp circuit 10 of the present invention normally performs a feedback control operation and outputs a clamp waveform will be described. FIG. 9B is a diagram illustrating a voltage waveform at the output point B of the window comparator 50 when the clamp circuit 10 is performing a feedback control operation. When the surge detection voltage at the branch point A of the resistors 6 and 7 is lower than the first reference voltage _VL , the output point B of the window comparator 50 is in the output L state. At this time, a surge absorption control voltage for turning off the surge absorbing semiconductor element 9 is applied to the point C. As long as the L voltage is output at point B, the DC loop operating points of the amplifier 1, the comparator 4 and the amplifier 5 of the loop component of the feedback circuit are set so that the surge absorbing semiconductor element 9 is turned off. To do. In this state, dynamic feedback control is not working. That is, the window comparator output point (point B) remains the output L having a constant value. As long as the divided voltage (point A) of the surge voltage is lower than the first reference voltage V _L , at least one of the loop components of the feedback circuit sticks to one end of the upper limit or the lower limit of the limit point of the DC loop operation. It has been left. Therefore, it should be noted that even if the feedback control is working statically (direct current), the dynamic (alternating current) feedback control is not working.

As a more specific example, a case where the surge absorbing semiconductor element 9 is a MOSFET will be described. The gate-source voltage at which this MOSFET is turned on is 4V. When the surge voltage input to the clamp circuit 10 is low and the detection voltage at the branch A point does not exceed _VL , the surge absorption control voltage (gate-source voltage) at the C point becomes 4 V or less. As described above, the configuration of the amplifier 1, the comparator 4, and the amplifier 5 (inversion type and non-inversion type), setting of the DC operating point, gain setting, and the like are performed. As an example, the amplifier 1 can be a non-inverting operational amplifier, the comparator 4 can be an inverting adder, and the amplifier 5 can be an inverting operational amplifier.

Next, when the input surge voltage further increases and the surge detection voltage at point A exceeds _VL , the output of the window comparator 50 becomes H (output point B). At this time, the input to the non-inverting input terminal of the comparator 4 becomes H, the surge absorption control voltage (gate voltage) at the point C rises, and the MOSFET 9 is turned on. When the MOSFET 9 is turned on, the surge voltage is connected to the ground via the MOSFET 9 and the discharge resistor 8. The electric charge at the output of the surge generation circuit 20 is discharged, and the surge voltage decreases. In this state, dynamic feedback control is working.

When the surge detection voltage at the point A to the contrary is in the range of V _L of V _h, a surge voltage descends, by dynamic feedback control, the surge absorption control voltage at the point C (the gate voltage) Gradually go down. At this time, the current between the drain and the source decreases, and the operating point moves in the direction in which the MOSFET 9 is turned off. The surge absorption current flowing between the drain and source of the MOSFET 9 is narrowed down, and the surge absorption capability is reduced. As a result, the absorption of the surge voltage is stopped, and the surge voltage drop is suppressed.

While the voltage of the point A exceeds the first reference voltage V _L is the dynamic feedback control described above, the voltage at point A is maintained between the V _L of V _h. As shown in FIG. 9b, the voltage at the point B remains at the H output and becomes a substantially constant value. Further, the surge absorption control voltage (gate voltage) at the point C has a waveform similar to the input surge voltage as shown in FIG. 9d. It should be noted that neither of the waveforms of FIGS. 9a and 9c can be observed during normal operation of the feedback circuit. As described above, when the output (point B) of the window comparator 50 is an L output, the voltage at the point C is set so that the MOSFET 9 is completely turned off, and the feedback circuit is limited in its DC operation. Sticks to one end of the upper or lower limit of the point. That is, at least one of the loop components of the feedback circuit is in either the upper limit or the lower limit of its DC operating limit point. Therefore, as long as the output (point B) of the window comparator 50 is an L output, the change in the input voltage to the clamp circuit is not controlled, which means that “dynamic control is not working”. However, it should be noted that the static (direct current) control of the feedback circuit works in that each loop component is set to an operating point corresponding to the L output of the window comparator 50.

  As can be understood from the above description, the output voltage of the window comparator 50 has a function of giving a reference voltage for dynamic loop operation to the feedback circuit so that dynamic feedback control works in the feedback circuit. That is, it has a function of switching the (bias) operating point of each loop component from a static feedback control state to a dynamic feedback control state. As described above, the window comparator has been described as outputting the L output or the H output and supplying the output voltage like a logic circuit to the feedback circuit. However, as indicated by the point C voltage waveform during normal operation of the feedback circuit (FIG. 9d), from the viewpoint of providing a reference voltage for dynamic loop operation, the H output provides an analog bias voltage to the feedback circuit. Note also that it may include functionality.

  The clamp circuit of the present invention is characterized in that the operating range in which dynamic feedback control is activated in the feedback circuit is determined by the dynamic loop operation reference voltage from the window comparator. Furthermore, the dynamic feedback control is also characterized in that it operates within a voltage range with a constant width between the first reference voltage and the second reference voltage to the window comparator. These features are further clarified by contrast with the operation of the prior art clamp circuit shown in FIG.

In the prior art clamp circuit of FIG. 7, the divided voltage is directly compared with a reference voltage V _L 33 which is a reference for feedback control. According to the comparison result of both voltages, the loop operating point of the comparator 34 and the amplifier 35 is instantaneously changed in either direction. The operating conditions (loop gain, bias point) of the loop components that can achieve both elimination of delay (broadband) and avoidance of loop oscillation (loop stabilization) when the surge absorbing semiconductor 36 is switched from on to off. The setting range is very narrow. Furthermore, it is difficult to stably operate feedback control over a wide range of peak voltages, clamp voltages, and surge absorption currents required for a test surge voltage.

  On the other hand, in the clamp circuit of the configuration of the present invention, the feedback circuit is fixed to a good loop by the dynamic loop operation reference voltage output from the window comparator within a predetermined voltage range defined by the two reference voltages. The operating point can be maintained. Thus, stable clamping of the surge voltage is realized by dynamic feedback control within the range of the clamping voltage corresponding to the predetermined voltage width. Since the reference voltage for which dynamic feedback control is working has a certain width, the resulting clamp voltage value also has a certain width. However, the first reference voltage and the second reference voltage can be set so that the fluctuation amount is within the allowable range defined in the international standard.

  As described above in detail, the clamp circuit of the present invention employs a window comparator that operates in accordance with a reference voltage having a predetermined voltage width, so that the operating point of each loop component of the feedback circuit is within a certain range. By maintaining the above, a stable clamp waveform can be generated over a wide range of peak voltage, clamp voltage, and surge absorption current conditions. Since the clamp voltage is stabilized, the adjustment of the applied voltage when performing a reliability test can be simplified, and even if the number of samples of the device under test is limited, depending on the predetermined conditions A reliability test can be performed.

  In the embodiment of FIG. 1, a power amplifier type low dump surge generation circuit is described as an example of the surge generation circuit 20, but the surge voltage from the capacitor charge / discharge type load dump surge generation circuit shown in FIG. Even in the case of providing the above, the above-described effects can be obtained. However, in the case of a power amplifier type load dump surge generation circuit, combined with the effect of preventing the shortening of the wave tail length, the load dump surge test signal waveform can be generated stably with better reproducibility.

In the embodiment of FIG. 1, a window comparator is employed as a method for generating a dynamic loop operation reference voltage in accordance with a reference voltage having a predetermined voltage width, but other means for performing the same operation are used. It can also be taken. (For example, there is a method in which a surge voltage is detected by an AD converter, a dynamic loop operation reference voltage corresponding to a predetermined detection voltage value is generated by a DA converter, and applied to the comparator 4).
In the embodiment, the feedback circuit includes the amplifier 1, the comparator 4, and the amplifier 4, but is not limited to this configuration. In other words, any configuration can be used as long as it can act on the surge absorbing semiconductor 9 (control means) and perform feedback control based on the surge detection voltage (control target) detected by the voltage dividing circuit using the resistors 6 and 7. Such a configuration is also possible. Accordingly, the inversion / non-inversion amplification operation type and the number of amplification stages in the amplifiers 1 and 5 can be variously changed or modified. The semiconductor element for surge absorption is not limited to a MOSFET, and various devices such as a bipolar transistor can be used.

  The surge detection voltage from the voltage dividing circuit by the resistors 6 and 7 is supplied from the common voltage dividing circuit to the feedback circuit and the window comparator, but can also be supplied from separate detection circuits.

It is a block diagram which shows the load dump surge waveform generation circuit concerning one Embodiment of this invention. It is a figure which shows the load dump surge waveform prescribed | regulated by the international standard. This is a load dump surge generating circuit of a capacitor charging / discharging method. It is a figure which shows an example of the clamp circuit by ZD recommended to the international standard. It is a figure which shows an example of the loaded danceage generation circuit of a prior art. It is a figure explaining the problem of a prior art. It is a figure which shows an example of the clamp circuit by a prior art. It is a figure explaining the problem of the partial pressure in the load dump surge generation circuit of a power amplifier system. It is a figure explaining operation | movement of the clamp circuit which concerns on this invention.

Explanation of symbols

1, 5, 35 Amplifier 2, 3, 4, 34 Comparator 6, 7, 31, 32 Voltage dividing resistor 8, 22, 23, 24, 25, 37 Resistor 9, 36 Surge absorbing semiconductor element 10 Clamp circuit 11 First Reference voltage of 2 12 First reference voltage 20 Surge generating circuit 21 High voltage DC power supply 26 Energy charging / discharging capacitor 27 Surge waveform forming semiconductor switch 28 Switch 29 Rise time forming inductor 33 Reference voltage 40 Power amplifier type surge generating circuit 41 DUT 50 Wind comparator

Claims (5)

A clamp circuit that generates a signal in which a surge voltage signal is clamped to a predetermined threshold voltage,
A first reference voltage corresponding to the predetermined threshold voltage and a second reference voltage higher than the first reference voltage are input, and a surge detection voltage proportional to the surge voltage is the first reference voltage and the Dynamic loop operation reference voltage generating means for outputting a predetermined dynamic loop operation reference voltage when in a voltage range between the second reference voltages;
Surge voltage absorbing means for absorbing the surge voltage according to control of the surge absorption control voltage input to the surge absorption control terminal when the surge voltage signal is applied and the surge voltage is higher than the predetermined threshold voltage; ,
Comparing means for comparing the dynamic loop operation reference voltage and a surge detection voltage proportional to the surge voltage, the feedback circuit for outputting the surge absorption control voltage to the surge voltage absorbing means, the result of the comparison When the surge detection voltage changes in the increasing direction, the surge voltage absorbing means operates to absorb the surge voltage by short-circuiting the surge voltage, and when the surge detection voltage changes in the decreasing direction. Generating the surge absorption control voltage that operates to open the surge voltage absorbing means and stop absorbing the surge voltage;
A clamp circuit comprising:   The dynamic loop operation reference voltage generating means includes a first comparator to which the first reference voltage and the surge detection voltage are input, and a second comparator to which the second reference voltage and the surge detection voltage are input. The clamp circuit according to claim 1, wherein the comparator is a window comparator.   The clamp circuit according to claim 1 or 2, wherein the surge voltage absorbing means is a MOSFET in which the surge voltage is applied between a drain and a source, and the surge absorption control voltage is applied to a gate.   3. The clamp circuit according to claim 1, wherein the surge voltage absorbing means is a transistor to which the surge voltage is applied between a collector and an emitter, and the surge absorption control voltage is applied to a base. 5. A load dump surge test signal generator comprising the clamp circuit according to claim 1 connected to a surge voltage output terminal of a power amplifier type load dump surge generator circuit. .

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