JP2007103491A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress current leakage by a parasitic transistor while suppressing deterioration of crystallinity of a semiconductor layer in which a field effect transistor is formed.
An etching gas or an etchant is brought into contact with a first semiconductor layer through a groove to remove the first semiconductor layer by etching, and a cavity is formed between the semiconductor substrate and the second semiconductor layer. After forming the portion 9, the impurity introduction layer 3 a is formed on the side wall of the second semiconductor layer 3 by performing oblique ion implantation IP of impurities on the side wall of the second semiconductor layer 3 through the groove 8.
[Selection] Figure 5

Description

A field effect transistor formed on an SOI (Silicon On Insulator) substrate has attracted attention because of its ease of element isolation, latch-up free, and small source / drain junction capacitance.
Further, for example, in Patent Document 1, in order to form a silicon thin film with good crystallinity and uniformity on a large-area insulating film, an amorphous or polycrystalline silicon layer formed on the insulating film is irradiated with ultraviolet rays. By irradiating the beam in a pulse shape, a polycrystalline silicon film in which single crystal grains close to squares are arranged in a grid pattern is formed on an insulating film, and the surface of the polycrystalline silicon film is subjected to CMP (chemical mechanical film). A method of flattening by mechanical polishing) is disclosed.

Non-Patent Document 1 discloses a method by which an SOI transistor can be formed at a low cost by forming an SOI layer over a bulk substrate. In the method disclosed in Non-Patent Document 1, a Si / SiGe layer is formed on a Si substrate, and only the SiGe layer is selectively removed using a difference in selectivity between Si and SiGe. A cavity is formed between the Si substrate and the Si layer. Then, by performing thermal oxidation of Si exposed in the cavity, an SiO ₂ layer is embedded between the Si substrate and the Si layer, and a BOX layer is formed between the Si substrate and the Si layer.

Here, when the SOI transistor is formed in the SOI layer, there is a method of using a mesa isolation method for element isolation. This mesa isolation method has many advantages such as no transistor is formed between adjacent semiconductor layers because transistors are formed in an island-shaped semiconductor layer that is completely isolated from the surrounding semiconductor layers. It has been reported.
JP-A-10-261799 T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International GiGe Technology and Device Abstraction, pp. 230-231, May (2004)

However, the silicon thin film formed on the insulating film has grain boundaries, micro twins, and various other minute defects. For this reason, the field effect transistor formed on such a silicon thin film has a problem that the transistor characteristics are inferior to that of a field effect transistor formed on completely single crystal silicon.
When a field effect transistor formed on a silicon thin film is stacked, the field effect transistor is present in the lower layer. As a result, the flatness of the underlying insulating film on which the upper silicon thin film is formed deteriorates, and heat treatment conditions for forming the upper silicon thin film are limited, and the crystallinity of the upper silicon thin film is lower than that of the lower silicon thin film. There was a problem that it was inferior to the crystallinity of the thin film.

  Further, when element isolation is performed by the mesa isolation method, an inversion layer serving as a channel of the parasitic transistor is formed on the side surface or corner portion of the isolated SOI layer. For this reason, in the Vg-Id characteristic of the MOS transistor formed in the SOI layer, even when the gate voltage is relatively low, a leakage current flows in the source / drain region, and an abnormality is observed in the rising characteristic of the current. there were.

  Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress current leakage due to a parasitic transistor while suppressing deterioration in crystallinity of a semiconductor layer in which a field effect transistor is formed. It is to be.

  In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, a semiconductor layer formed by epitaxial growth on a semiconductor substrate and separated by mesa, and between the semiconductor substrate and the semiconductor layer are provided. A buried oxide film, a first conductivity type impurity introduction layer formed at an end of the mesa-isolated semiconductor layer, a gate electrode formed on the semiconductor layer, and formed in the semiconductor layer; A second conductivity type source layer disposed on one side of the gate electrode; and a second conductivity type drain layer formed on the semiconductor layer and disposed on the other side of the gate electrode. To do.

  As a result, the semiconductor substrate and the semiconductor layer can be insulated from each other by the buried oxide film buried under the semiconductor layer, and the semiconductor layer under the gate electrode can be isolated even when the semiconductor layer is separated into a mesa shape. The impurity concentration at the end can be increased. Therefore, a channel can be prevented from being formed at the end of the semiconductor layer under the gate electrode, and a parasitic transistor can be prevented from being formed on the side surface of the mesa-isolated semiconductor layer. At the same time, a transistor can be formed in an island-shaped semiconductor layer completely isolated from the surrounding semiconductor layers, and element isolation of the semiconductor layer formed over the insulator can be stably performed. As a result, an SOI transistor can be formed on the semiconductor layer without using an SOI substrate, and the SOI transistor can be reduced in price and current leakage due to a parasitic transistor can be suppressed. Therefore, the SOI transistor can be driven at a low voltage, reduced in power consumption, and increased in speed.

In the semiconductor device according to one embodiment of the present invention, the first conductivity type impurity introduction layer is formed at least at an end portion of the semiconductor layer where the gate electrode intersects.
Accordingly, it is possible to prevent a channel from being formed at the end portion of the semiconductor layer under the gate electrode, and it is possible to prevent a parasitic transistor from being formed on the side surface of the mesa-isolated semiconductor layer.

In the semiconductor device according to one aspect of the present invention, the impurity concentration of the first conductivity type impurity introduction layer is substantially constant in the depth direction of the semiconductor layer.
As a result, the impurity concentration of the entire end portion of the semiconductor layer under the gate electrode can be uniformly increased, and a channel can be stably prevented from being formed at the end portion of the semiconductor layer under the gate electrode. It becomes.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer over the semiconductor substrate, and the second semiconductor layer having an etching rate smaller than that of the first semiconductor layer are provided in the first semiconductor layer. Forming on the first semiconductor layer; forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate; and the second semiconductor through the first groove. Forming a support for supporting a layer on the semiconductor substrate, forming a second groove exposing a portion of the first semiconductor layer from the second semiconductor layer, and via the second groove Forming a cavity from the first semiconductor layer under the second semiconductor layer by selectively etching the first semiconductor layer; and the second semiconductor layer through the second groove. The first conductivity type impurities on the side wall Forming a first conductivity type impurity introduction layer on the side wall of the second semiconductor layer, forming a buried oxide film buried in the cavity, and disposing on the second semiconductor layer Forming a gate electrode, a second conductivity type source layer disposed on one side of the gate electrode, and a second conductivity type drain layer disposed on the other side of the gate electrode. And a step of forming the layer.

  As a result, even when the second semiconductor layer is stacked on the first semiconductor layer, it becomes possible to bring the etching gas or the etchant into contact with the first semiconductor layer through the second groove. The first semiconductor layer can be removed using the difference in etching rate between the first and second semiconductor layers, and a buried oxide film buried in the cavity below the second semiconductor layer can be removed. Can be formed. Also, by providing a support that supports the second semiconductor layer on the semiconductor substrate, the second semiconductor layer is prevented from dropping onto the semiconductor substrate even when a cavity is formed below the second semiconductor layer. can do. Further, by forming the first conductivity type impurity introduction layer on the side wall of the second semiconductor layer, even when the second semiconductor layer is separated in a mesa shape, a channel is formed at the end of the second semiconductor layer under the gate electrode. It is possible to prevent the formation of a parasitic transistor and the formation of a parasitic transistor on the side surface of the mesa-isolated semiconductor layer.

  Therefore, an SOI transistor can be formed on the second semiconductor layer without using an SOI substrate, and even when the second semiconductor layer is separated in a mesa shape, an increase in the number of processes is suppressed. In addition, current leakage due to parasitic transistors can be suppressed, the SOI transistor can be reduced in price, and the SOI transistor can be driven at a lower voltage, reduced in power consumption, and increased in speed. .

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer over the semiconductor substrate, and the second semiconductor layer having an etching rate smaller than that of the first semiconductor layer are provided in the first semiconductor layer. Forming on the first semiconductor layer; forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate; and the second semiconductor through the first groove. Forming a support for supporting a layer on the semiconductor substrate, forming a second groove exposing a portion of the first semiconductor layer from the second semiconductor layer, and via the second groove Forming a cavity under the second semiconductor layer by selectively etching the first semiconductor layer, and forming a buried oxide film embedded in the cavity; And the step of forming the second groove Forming a first conductivity type impurity introduction layer on the sidewall of the second semiconductor layer by obliquely ion implanting the first conductivity type impurity on the sidewall of the second semiconductor layer on the buried oxide film; Forming a gate electrode disposed on the second semiconductor layer; a second conductivity type source layer disposed on one side of the gate electrode; and a second conductivity type disposed on the other side of the gate electrode. Forming a drain layer on the second semiconductor layer.

  Thereby, after forming the buried oxide film under the second semiconductor layer, the first conductivity type impurity introduction layer can be formed on the side wall of the second semiconductor layer. For this reason, the redistribution of impurities in the first conductivity type impurity introduction layer accompanying the heat treatment at the time of forming the buried oxide film can be suppressed, and the impurity concentration on the surface of the sidewall of the second semiconductor layer can be increased. For this reason, even when the second semiconductor layer is separated in a mesa shape, it is possible to stably prevent a channel from being formed at the end of the second semiconductor layer under the gate electrode, and the mesa-isolated semiconductor It is possible to prevent a parasitic transistor from being formed on the side surface of the layer.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor substrate and the second semiconductor layer are Si, and the first semiconductor layer is SiGe.
As a result, it is possible to increase the etching rate of the first semiconductor layer compared to the half of the semiconductor substrate and the second semiconductor layer while allowing lattice matching between the semiconductor substrate, the second semiconductor layer and the first semiconductor layer. Become. For this reason, it becomes possible to form the second semiconductor layer with good crystal quality on the first semiconductor layer, and insulation between the second semiconductor layer and the semiconductor substrate is achieved without impairing the quality of the second semiconductor layer. It becomes possible.

In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the second groove and the gate electrode are orthogonal to each other.
This makes it possible to prevent the channel from being formed at the end of the second semiconductor layer under the gate electrode, and to prevent the formation of a parasitic transistor on the side surface of the mesa-isolated second semiconductor layer. be able to.

Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.
FIGS. 1A to 9A are perspective views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 1B to 9B are FIGS. Cross-sectional views cut along lines A1-A1 ′ to A9-A9 ′ in FIG. 9A, and FIGS. 1C to 9C are cross-sectional views taken along B1- in FIGS. 1A to 9A, respectively. It is sectional drawing cut | disconnected by the B1'-B9-B9 'line | wire, respectively.

  In FIG. 1, a first semiconductor layer 2 is formed on a semiconductor substrate 1 by epitaxial growth, and a second semiconductor layer 3 is formed on the first semiconductor layer 2 by epitaxial growth. The first semiconductor layer 2 can be made of a material having an etching rate larger than that of the semiconductor substrate 1 and the second semiconductor layer 3. In particular, when the semiconductor substrate 1 is Si, the first semiconductor layer 2 is SiGe, 2 It is preferable to use Si as the semiconductor layer 3. Accordingly, it is possible to secure a selection ratio between the first semiconductor layer 2 and the second semiconductor layer 3 while enabling lattice matching between the first semiconductor layer 2 and the second semiconductor layer 3. it can. Moreover, the film thickness of the 1st semiconductor layer 2 and the 2nd semiconductor layer 3 can be about 10-200 nm, for example.

Then, a base oxide film 4 is formed on the surface of the second semiconductor layer 3 by thermal oxidation of the second semiconductor layer 3. Then, an antioxidant film 5 is formed on the entire surface of the base oxide film 4 by a method such as CVD. For example, a silicon nitride film can be used as the antioxidant film 5.
Next, as shown in FIG. 2, by using the photolithography technique and the etching technique, the antioxidant film 5, the base oxide film 4, the second semiconductor layer 3, and the first semiconductor layer 2 are patterned, thereby the semiconductor substrate 1 A groove 6 for exposing a part of the groove 6 is formed. The arrangement position of the groove 6 can correspond to a part of the element isolation region of the second semiconductor layer 3.

  Next, as shown in FIG. 3, a support 7 embedded in the groove 6 is formed so as to cover the entire surface of the substrate by a method such as CVD. The support 7 is also formed on the sidewalls of the first semiconductor layer 2 and the second semiconductor layer 3 in the groove 6, and can support the second semiconductor layer 3 on the semiconductor substrate 1. As the material of the support 7, an insulator such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used.

Next, as shown in FIG. 4, the first semiconductor layer is patterned by patterning the antioxidant film 5, the base oxide film 4, the second semiconductor layer 3, and the first semiconductor layer 2 using a photolithography technique and an etching technique. A groove 8 exposing a part of 2 is formed. Here, the arrangement position of the groove 8 can correspond to a part of the element isolation region of the second semiconductor layer 3.
Next, as shown in FIG. 5, the first semiconductor layer 2 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 2 through the groove 8, and the semiconductor substrate 1 and the second semiconductor layer are removed. And a cavity 9 is formed between the two.

  Here, by providing the support 7 in the groove 6, the second semiconductor layer 3 can be supported on the semiconductor substrate 1 even when the first semiconductor layer 2 is removed, and the groove 6. By providing the groove 8 separately, the etching gas or the etching liquid can be brought into contact with the first semiconductor layer 2 below the second semiconductor layer 3. For this reason, it is possible to achieve insulation between the second semiconductor layer 3 and the semiconductor substrate 1 without impairing the quality of the second semiconductor layer 3.

  When the semiconductor substrate 1, the second semiconductor layer 3 and the support 7 are Si and the first semiconductor layer 2 is SiGe, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid and water) is used as an etching solution for the first semiconductor layer 2. Is preferably used. As a result, a Si / SiGe selection ratio of about 1: 100 to 1000 can be obtained, and the first semiconductor layer 2 is removed while suppressing overetching of the semiconductor substrate 1, the second semiconductor layer 3, and the support 7. It becomes possible to do.

Next, as shown in FIG. 6, the impurity introduction layer 3 a is formed on the side wall of the second semiconductor layer 3 by performing oblique ion implantation IP of impurities on the side wall of the second semiconductor layer 3 through the groove 8. Note that, by forming the impurity introduction layer 3a on the side wall of the second semiconductor layer 3 by oblique ion implantation IP, the impurity concentration of the impurity introduction layer 3a is made substantially constant in the depth direction of the second semiconductor layer 3. be able to. Further, when an N channel field effect transistor is formed in the second semiconductor layer 3, the conductivity type of the impurity introduction layer 3a is P type, and when a P channel field effect transistor is formed in the second semiconductor layer 3, the impurity is introduced. The conductivity type of the introduction layer 3a is preferably N-type. Here, when the conductivity type of the impurity introduction layer 3a is P type, B and BF ₂ as impurities implanted into the impurity introduction layer 3a, and when the conductivity type of the impurity introduction layer 3a is N type, the impurity introduction layer 3a P, As, or the like can be used as an impurity implanted into the substrate.

  Next, as shown in FIG. 7, a buried oxide film 10 is formed in the cavity 9 between the semiconductor substrate 1 and the second semiconductor layer 3 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3. To do. At this time, the side wall of the second semiconductor layer 3 is also oxidized, and an oxide film 11 is formed on the side wall of the second semiconductor layer 3. In the case where the buried oxide film 10 is formed by thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3, it is preferable to use low-temperature wet oxidation that is reaction-controlled in order to improve the embeddability.

  Next, as shown in FIG. 8, after the buried insulator 13 is buried in the groove 8 by a method such as CVD, the buried insulator 13 and the support 7 are thinned by a method such as CMP or etchback. Then, planarization by CMP is stopped using the antioxidant film 5 as a stopper layer. Subsequently, the surface of the second semiconductor layer 3 is exposed by removing the base oxide film 4 and the antioxidant film 5. For example, an insulator such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used as the buried insulator 13.

  Next, as shown in FIG. 9, a gate insulating film 21 is formed on the surface of the second semiconductor layer 3 by performing thermal oxidation of the surface of the second semiconductor layer 3. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 3 on which the gate insulating film 21 is formed by a method such as CVD. Then, the gate electrode 22 is formed on the second semiconductor layer 3 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique. The gate electrode 22 is preferably arranged so as to be orthogonal to the groove 8.

  Next, by using the gate electrode 22 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3, thereby forming LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 22. Layers 23 a and 23 b are formed on the second semiconductor layer 3. Then, an insulating layer is formed on the second semiconductor layer 3 on which the LDD layers 23a and 23b are formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 24a and 24b are formed on the side walls of the electrode 22, respectively. Then, by using the gate electrode 22 and the sidewalls 24a and 24b as masks, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3 to be respectively disposed on the sides of the sidewalls 24a and 24b. A source 25 a and a drain layer 25 b made of a high concentration impurity introduction layer are formed in the second semiconductor layer 3.

  As a result, the semiconductor substrate 1 and the second semiconductor layer 3 can be insulated from each other by the buried oxide film 10 buried under the second semiconductor layer 3, and the second semiconductor layer 3 is separated into a mesa shape. Even in this case, the impurity concentration at the end of the second semiconductor layer 3 under the gate electrode 22 can be increased. For this reason, it is possible to prevent a channel from being formed at the end of the second semiconductor layer 3 below the gate electrode 22, and to form a parasitic transistor on the side surface of the second semiconductor layer 3 that is mesa-isolated. The transistor can be formed in the island-shaped second semiconductor layer 3 that is completely isolated from the surrounding second semiconductor layer 3 and can be prevented, and the second semiconductor formed on the buried oxide film 10 It becomes possible to perform element isolation of the layer 3 stably. As a result, an SOI transistor can be formed on the second semiconductor layer 3 without using an SOI substrate, so that the SOI transistor can be reduced in price and current leakage due to a parasitic transistor can be suppressed. Therefore, the SOI transistor can be driven at a low voltage, reduced in power consumption, and increased in speed.

In the above-described embodiment, the method of laminating the second semiconductor layer 3 by one layer on the semiconductor substrate 1 through the buried oxide film 10 has been described. However, a plurality of semiconductor layers are formed on the semiconductor substrate through the oxide films, respectively. It may be laminated on the substrate 1.
Further, in the above-described embodiment, a method of forming the antioxidant film 5 on the second semiconductor layer 3 in order to prevent thermal oxidation of the surface of the second semiconductor layer 3 when forming the buried oxide film 10. As described above, the buried oxide film 10 may be formed without forming the antioxidant film 5 on the second semiconductor layer 3. In this case, the oxide film formed on the surface of the second semiconductor layer 3 when the buried oxide film 10 is formed may be removed by etching or polishing.

  In the above-described embodiment, the buried oxide film 10 is formed in the cavity 9 between the semiconductor substrate 1 and the second semiconductor layer 3 in order to form the impurity introduction layer 3 a on the sidewall of the second semiconductor layer 3. The method of performing the oblique ion implantation IP of impurities on the sidewall of the second semiconductor layer 3 has been described before, but after the buried oxide film 10 is formed in the cavity 9 between the semiconductor substrate 1 and the second semiconductor layer 3. The impurity introduction layer 3 a may be formed on the side wall of the second semiconductor layer 3. Thereby, the redistribution of impurities in the impurity introduction layer 3a accompanying the heat treatment when forming the buried oxide film 10 can be suppressed, and the impurity concentration on the surface of the sidewall of the second semiconductor layer 3 can be increased. For this reason, even when the second semiconductor layer 3 is separated in a mesa shape, it is possible to stably prevent a channel from being formed at the end of the second semiconductor layer 3 under the gate electrode 22, and to separate the mesa. It is possible to prevent a parasitic transistor from being formed on the side surface of the formed second semiconductor layer 3.

The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 1st semiconductor layer, 3rd 2nd semiconductor layer, 3a Impurity introduction | transduction layer, 4 Base oxide film, 5 Antioxidation film, 6, 8 Element isolation groove, 7 Support body, 9 Cavity part, 10 Embedded oxidation Film, 11 oxide film, 13 buried insulator, 21 gate insulating film, 22 gate electrode, 23a, 23b LDD layer, 24a, 24b sidewall spacer, 25a source layer, 25b drain layer

Claims (7)

A mesa-isolated semiconductor layer formed by epitaxial growth on a semiconductor substrate;
A buried oxide film buried between the semiconductor substrate and the semiconductor layer;
A first conductivity type impurity introduction layer formed at an end of the mesa-isolated semiconductor layer;
A gate electrode formed on the semiconductor layer;
A second conductivity type source layer formed on the semiconductor layer and disposed on one side of the gate electrode;
A semiconductor device comprising: a second conductivity type drain layer formed on the semiconductor layer and disposed on the other side of the gate electrode.   The semiconductor device according to claim 1, wherein the first conductivity type impurity introduction layer is formed at least at an end portion of the semiconductor layer where the gate electrode intersects.   3. The semiconductor device according to claim 1, wherein the first conductivity type impurity introduction layer has an impurity concentration substantially constant in a depth direction of the semiconductor layer. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate via the first groove;
Forming a second groove exposing a part of the first semiconductor layer from the second semiconductor layer;
Forming the cavity from which the first semiconductor layer has been removed by selectively etching the first semiconductor layer through the second groove below the second semiconductor layer;
Forming a first conductivity type impurity introduction layer on the side wall of the second semiconductor layer by implanting a first conductivity type impurity obliquely into the side wall of the second semiconductor layer through the second groove;
Forming a buried oxide film buried in the cavity;
Forming a gate electrode disposed on the second semiconductor layer;
Forming a second conductivity type source layer disposed on one side of the gate electrode and a second conductivity type drain layer disposed on the other side of the gate electrode on the second semiconductor layer. A method of manufacturing a semiconductor device. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a first groove through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate via the first groove;
Forming a second groove exposing a part of the first semiconductor layer from the second semiconductor layer;
Forming a cavity from which the first semiconductor layer is removed under the second semiconductor layer by selectively etching the first semiconductor layer through the second groove;
Forming a buried oxide film buried in the cavity;
A first conductivity type impurity introduction layer is formed on the side wall of the second semiconductor layer by implanting obliquely ion implantation of the first conductivity type impurity on the side wall of the second semiconductor layer on the buried oxide film through the second groove. And a process of
Forming a gate electrode disposed on the second semiconductor layer;
Forming a second conductivity type source layer disposed on one side of the gate electrode and a second conductivity type drain layer disposed on the other side of the gate electrode on the second semiconductor layer. A method of manufacturing a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor substrate and the second semiconductor layer are Si, and the first semiconductor layer is SiGe.   The method for manufacturing a semiconductor device according to claim 4, wherein the second groove and the gate electrode are orthogonal to each other.

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