JP2007129250A - Semiconductor device - Google Patents

Abstract

【Task】
Provided is a semiconductor device having a plurality of basic units including memory cells and logic cells on the same semiconductor substrate, which can be easily manufactured and can be highly integrated.
[Solution]
The semiconductor device is a semiconductor device formed on a semiconductor substrate and having a plurality of identical or symmetric unit structures including memory elements and logic elements, each unit structure being formed in a first active region A logic element series-connected transistor having a DRAM cell, a second / third gate electrode and a source / drain region having a silicide layer formed in the second active region, and a pair of the source / drain regions The first and second signal lines connected to the gate, the third signal line connected to the second gate electrode, and the storage electrode of the DRAM capacitor are formed below, and the storage electrode and the third gate electrode are connected. A conductive connecting member.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of basic units including memory cells and logic cells on the same semiconductor substrate.

  An associative memory (CAM, Content Addressable Memory) has been attracting attention in order to realize an advanced and high-speed information processing system. The CAM has a function that allows the logic cell to detect a match between the memory content stored in the memory cell and a signal supplied from the outside. The memory cell is usually composed of SRAM.

  Gillingham previously proposed a CAM that uses dynamic random access memory (DRAM) for the memory cells. According to this configuration, even when a complementary signal is stored, the basic unit memory cell can be composed of two transistors and two capacitors. However, how to construct this CAM efficiently is not yet established.

  An object of the present invention is to provide a semiconductor device having a plurality of basic units including memory cells and logic cells on the same semiconductor substrate, which can be easily manufactured and can be highly integrated.

  Another object of the present invention is to provide a semiconductor device capable of realizing a high-performance CAM.

According to one aspect of the present invention,
A semiconductor device having a semiconductor substrate and a plurality of unit structures formed on the semiconductor substrate, forming a memory element and a logic element, and having the same or symmetrical planar shape, wherein each unit structure is the semiconductor An isolation insulating region formed on a surface of the substrate and defining first and second active regions;
A first gate electrode formed across the first active region, and a pair of first source / drain formed on both sides of the first gate electrode in the first active region A transfer transistor having a region;
A word line connected to the first gate electrode;
A bit line connected to one of the pair of first source / drain regions;
Second and third gate electrodes formed across the second active region; and a connection node formed between the second and third gate electrodes in the second active region; A pair of second source / drain regions formed outside the second and third gate electrodes, the connection node, the pair of second source / drain regions, and a portion other than the partial region A serial connection transistor including a silicide electrode formed on the third gate electrode;
A first signal line connected to a silicide electrode on one of the pair of second source / drain regions;
A second signal line connected to a silicide electrode on the other of the pair of second source / drain regions;
A third signal line connected to the second gate electrode;
A storage electrode formed in a region including the other of the pair of first source / drain regions and at least part of the third gate electrode;
A capacitor dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the capacitor dielectric film;
A first conductive connection member formed below the storage electrode and connecting the storage electrode and the other of the pair of first source / drain regions;
A second conductive connection member formed below the storage electrode and connecting the storage electrode and the partial region of the third gate electrode;
A semiconductor device is provided.

  As described above, according to the present invention, a semiconductor device including a plurality of basic units including a memory element and a logic element having an efficient configuration is provided.

  The degree of CAM integration can be improved and the manufacturing process can be stabilized.

  FIGS. 1A and 1B show an equivalent circuit of a CAM proposed by Gillingham's previous proposal and its logic table. In FIG. 1A, U and / U indicate a unit structure of a repeating unit, and U and / U having a symmetric structure constitute one CAM unit (basic unit). A plurality of CAM units are arranged in a matrix.

  Complementary information is supplied to the bit lines BL and / BL of the memory cell MC. The transfer transistors Ta and Tb are on / off controlled by the signal of the same word line WL. Complementary information is written into the capacitors Ca and Cb via the transfer transistors Ta and Tb.

  The series connection of the transistors Pa and Qa and the series connection of Pb and Qb constitute the logic cell LC. One terminal of the series connection (one source / drain electrode of Qa and Qb) is connected to the ground line GND. The other source / drain electrodes of the transistors Pa and Pb connected in series to the transistors Qa and Qb are connected to the same match line ML.

  The potentials of the storage electrodes of the capacitors Ca and Cb are applied to the gate electrodes of the transistors Qa and Qb of the logic circuit.

  Therefore, on / off of the transistors Qa and Qb of the logic circuit is controlled by the potentials of the storage electrodes of the capacitors Ca and Cb. The gate electrodes of the transistors Pa and Pb are connected to the data bus lines DB and / DB, respectively.

  Note that as shown in FIG. 1C, the arrangement of the transistor P (Pa, Pb) and the transistor Q (Qa, Qb) may be exchanged.

  When the match line ML is precharged and an input signal and its complementary signal are applied to the data bus lines DB and / DB, one of the transistors Pa and Pb is turned on and the other is turned off. If the transistor Qa or Qb connected in series to the turned-on transistor Pa or Pb is turned on, the potential of the precharged match line ML is discharged to the ground line, and the potential of the match line ML changes.

  Even if the transistor Pa or Pb is turned on, if the transistor Qa or Qb connected in series is turned off, the match line ML is not discharged, and the potential of the match line ML is kept in a precharged state. Therefore, the potential change of the match line ML is controlled by a series connection connected to the high state memory (Ca or Cb).

  The bit lines BL and / BL connected to the memory cell MC are connected to the bit line driving circuit BLD, and the word line WL is connected to the word line driving circuit WLD. The data bus lines DB and / DB are connected to the data bus line driving circuit DBD, and the match line ML is connected to the match line driving circuit MLD. Note that the data bus line driving circuit DBD may be a terminal itself for inputting an external signal, or may be a buffer circuit for temporarily storing the external signal.

  FIG. 1B shows a logical function of the unit CAM cell shown in FIG. The column of DRAM indicates the charge state of the memory cell MC, more specifically, the DRAM capacitor Ca or Cb. When the capacitor Ca is charged to a high potential, it is in a high (H) state, and when it is charged to a low potential, it is in a low (L) state.

  The capacitor Cb stores a signal complementary to the capacitor Ca. When DRAM, more specifically, capacitor Ca is in a high (H) state, transistor Qa is on and transistor Qb is off. Accordingly, the potential of the match line ML is discharged to the ground line only when the other transistor Pa connected in series to the turned-on transistor Qa is turned on (the database line DB is high). That is, when the potential of the data bus line DB is high (H), the match line ML is low (L).

  When DRAM is low, capacitor Cb stores a high high potential and transistor Qb is turned on. Accordingly, only when the transistor Pb connected in series to the transistor Qb is on (the database line / DB is high), the potential of the match line ML is discharged and becomes a low (L) state. In other cases, the potential of the match line ML is kept high (H). When both of the two sets of DRAMs are in the L state, ML is held at H regardless of DB. This is called don't care. This circuit can also realize this. FIG. 1B collectively shows this logical operation.

  In FIG. 1A, the repeating units U and / U are shown in a symmetric configuration. Even in an actual semiconductor device, it is preferable that the repeating units U and / U are formed in the same or symmetrical configuration.

  2A and 2B show examples of arrangement of components in the repeating unit U shown in FIG. FIG. 2A shows the shape of the active region defined by the isolation insulating region formed on the surface of the semiconductor substrate and the shape of the gate electrode (signal line) traversing the active region. A field insulating film FOX for element isolation is formed on the surface of the semiconductor substrate to constitute an isolation insulating region. The field insulating film FOX can be formed by a silicon oxide film formed by LOCOS (local oxidation of silicon) or STI (shallow trench isolation).

  Regions where the field insulating film FOX is not formed become active regions ARM and ARL. The active region ARM is an active region for forming a memory element, and the active region ARL is an active region for forming a logic element. In the figure, the active region ARM extends in the horizontal direction, and the active region ARL extends in the vertical direction beyond the repeating unit.

  After forming a gate insulating film (silicon oxide film, etc.) on the active region, a polycrystalline silicon layer is deposited and patterned to form the gate electrodes G1, G2, the word line WL that also serves as the gate electrode, and the data bus line DB To do. A salicide process is performed on the transistor in the logic element region to form a silicide layer on the gate electrode and the source / drain region.

  In the figure, the word line WL extends in the vertical direction across the active region ARM, and on the active region ARL, there is a separated gate electrode G1 and a gate electrode G2 branched from the data bus line DB that is long in the vertical direction. It is formed in the horizontal direction. The separated gate electrode G1 extends on the same straight line as the memory element active region ARM, and forms a contact portion having an enlarged width on the field insulating film FOX.

  In FIG. 2B, after forming a gate electrode or the like, the upper electrode is covered with a first insulating film, a contact hole is provided at a necessary portion, and a conductive material such as polycrystalline silicon is formed on the first insulating film. A state in which a signal line is formed is shown. The signal line forms an electrical contact at a position indicated by X in the lower active region. A ground line GND and a match line ML extend in the horizontal direction and are connected to both ends of the logic element active region ARL. The bit line BL is formed between the ground line GND and the match line ML, and is connected to one source / drain region of the memory element active region ARM.

  The region on the left side of the bit line contact belongs to the repeat unit on the left side. That is, two repeating units adjacent in the horizontal direction are configured symmetrically, and one bit line contact common to the two repeating units is formed.

  After covering the signal lines GND, BL, and ML with the second insulating layer, a contact hole is formed to expose the other source / drain region of the active region for the memory element and the contact portion of the separated gate electrode G1. The storage electrode SN of the capacitor indicated by a broken line is formed on the second insulating layer by filling the contact hole. The storage electrode SN is connected to the other source / drain region of the memory element transistor and the separated gate electrode G1 of the logic element, and electrically connects both. Further, the repeating unit U of FIG. 1A is formed by forming the capacitor dielectric film and the counter electrode.

FIG. 2C shows an example of the arrangement of repeating units in the substrate plane. The repeating units U ₁₁ and U ₁₂ have a symmetrical configuration with respect to the boundary line, and together constitute one CAM cell. The same applies to the repeating units U ₁₃ and U ₁₄ . The repeating units U ₁₂ and U ₁₃ may be symmetrical or the same. Note that the repeating units U ₁₁ and U ₁₂ may have the same configuration.

Repeat units U ₁₁ , U ₁₂ ,. . . And repeating units U ₂₁ , U ₂₂ ,. . . Is vertically symmetric with respect to its boundary line. Repeat units U ₃₁ , U _32,. . . Are repeating units U ₂₁ , U ₂₂ ,. . . May be symmetrical or the same. The repeating units U ₁₁ , U ₁₂ ,. . . And repeating units U ₂₁ , U ₂₂ ,. . . And the same configuration.

  FIG. 3 shows a cross-sectional structure taken along one-dot chain line III-III in FIG.

  For example, a trench for element isolation is formed on the surface of the silicon substrate 1 on which necessary wells are formed, a silicon oxide film is deposited, and the surface is flattened by chemical mechanical polishing (CMP) or the like, thereby isolating elements by STI. A field insulating region (FOX) 2 is formed. A gate oxide film 3 is formed on the active region surface defined in the field insulating region 2. A polycrystalline silicon layer is deposited on the gate oxide film 3 and patterned to form a gate electrode (including a signal line such as a word line) 5.

  After the gate electrode 5 is formed, an unnecessary portion is covered with a resist pattern as necessary, an n-type impurity is implanted into the semiconductor substrate 1, and a low concentration source / drain region 7a for a logic element and a source / drain for a memory element Region 8 is formed. If separate ion implantation is performed, an optimum impurity concentration can be adopted as a transistor for a logic element and a memory element.

  A CVD oxide film 11 is formed on the silicon substrate 1 by chemical vapor deposition (CVD) so as to cover the gate electrode 5. The memory element region is covered with a resist pattern, and the CVD oxide film 11 is anisotropically etched. The CVD oxide film on the flat surface is removed, and the side spacer 11a is left on the side wall of the gate electrode 5. In this state, high concentration ion implantation is performed to form a high concentration source / drain region 7b of the logic element transistor.

  The logic element high-concentration source / drain region 7b has a higher impurity concentration than the memory element source / drain region 8b.

  The resist pattern is removed, and a metal layer capable of silicide reaction such as Co is deposited on the entire surface of the silicon substrate 1. By performing heat treatment, a silicide reaction between the metal layer and the underlying silicon occurs, and silicide layers 25 and 26 are formed on the upper surface of the gate electrode 5 and the surface of the high concentration source / drain region 7b. Unreacted metal layer is removed. The logic element transistor has a low resistance due to the high-concentration source / drain regions and the silicide layer, and facilitates high-speed operation. High retention characteristics are maintained by not creating these in the memory element transistor. Note that the silicidation of the memory cell portion also deteriorates the retention, but it is also possible to produce an inexpensive product with a small number of processes.

  A silicon oxide film 12 having a planarizing function is formed on the silicon substrate 1 so as to cover the CVD oxide film 11. Reflow, CMP, etc. can also be used. After the planarized silicon oxide film 12 is formed, a contact hole 13 penetrating the oxide films 12 and 11 is formed using a resist mask. A conductive layer 14 such as polycrystalline silicon is deposited on the insulating film 12 to fill the contact hole, and a ground line GND (not shown), a bit line BL, and a match line ML are formed by patterning.

  An insulating layer 15 such as borophosphosilicate glass (BPSG) is deposited to cover the wiring 14, and a contact hole 16 for connecting the storage electrode of the capacitor is formed through the insulating layers 15, 12, and 11 using a resist mask. To do. A storage electrode 17 is formed by depositing and patterning a conductive layer such as a polycrystalline silicon layer on the insulating layer 15 in which the contact hole 16 is formed. Polycrystalline silicon also fills the contact holes 16 back.

  Connection portions CTM and CTL are continuously formed on the lower surface of the storage electrode 17. The connection portion CTM connects the lower surface of the storage electrode SN and one source / drain region 8 of the memory element. The connection part CTL connects the lower surface of the storage electrode SN and the gate electrode 5 (G1) for the logic element. Thereafter, a capacitor dielectric film 18 is formed on the entire surface, and a cell plate (counter) electrode 19 is formed thereon.

  In this way, the repeating unit U is formed. Other repeating units are also formed with the same or symmetric configuration.

  4A to 4E are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG.

  As shown in FIG. 4A, an element isolation field insulating film (FOX) 2 is formed on the surface of the silicon substrate 1. For example, a silicon nitride film pattern is formed on a region to be an active region via a buffer oxide film, and local oxidation (LOCOS) is performed to form a field oxide film. Alternatively, a resist pattern is formed on the silicon substrate 1 and an element isolation groove is formed by etching. Subsequently, a silicon oxide film is deposited so as to fill the trench, and the surface is planarized by CMP or the like to form shallow trench isolation (STL).

  After the field insulating film 2 is formed, an impurity for adjusting the threshold value of the transistor is ion-implanted as necessary. The memory element region and the logic element region may be separated by a resist pattern, and separate ion implantation may be performed. In this case, it is desirable to increase the operation speed of the logic element so that the memory element improves the off characteristic. After performing ion implantation for threshold adjustment, a gate oxide film 3 is formed by thermal oxidation or the like on the active region defined by the field insulating film 2 and exposing the silicon surface.

  As shown in FIG. 4B, a polycrystalline silicon layer 5 is deposited on the entire surface of the semiconductor substrate. When creating a CMOS structure, a resist mask is formed that opens a region for forming an n-channel MOS transistor, P ions as n-type impurities are ion-implanted, and a resist mask that opens a region for forming a p-channel MOS transistor is formed. And B ions which are p-type impurities are implanted. By this ion implantation, the gate electrode of the n-channel MOS transistor becomes n-type, and a surface channel MOS transistor is formed.

  Thereafter, a resist mask having a gate electrode pattern is formed on the polycrystalline silicon layer 5, and the gate electrode (including signal lines) 5 is patterned.

  Next, a resist mask 23 that covers the memory element region is formed, and As ions that are n-type impurities are implanted into the logic element region. By this ion implantation, the low concentration source / drain region 7a of the logic element in the CAM region is ion implanted.

  As shown in FIG. 4C, a resist mask 24 covering the logic element region is formed on the surface of the semiconductor substrate. Using this resist mask 24 as a mask, As ions which are n-type impurities are implanted into the memory element region, and source / drain regions 8 are formed on both sides of the gate electrode 5.

  As shown in FIG. 4D, a silicon oxide film 11 is deposited over the entire surface of the silicon substrate by chemical vapor deposition (CVD) so as to cover the gate electrode 5. Note that a nitride film or an oxide film / nitride film stack may be formed instead of the oxide film. The memory element region is covered with a resist mask, and the silicon oxide film 11 in the logic element region is anisotropically etched. The silicon oxide film 11 on the flat surface is removed, and the silicon oxide film 11a is left only on the side wall of the gate electrode 5. This silicon oxide film 11 a becomes a side wall oxide film of the gate electrode 5.

  As shown in FIG. 4E, high concentration ion implantation is performed to form a high concentration source / drain region 7b of the transistor for the logic element. When a CMOS circuit is included, a resist mask that opens an n-channel transistor of a logic circuit is formed and ion implantation is performed. Thereafter, the resist mask is removed.

  Here, the ion implantation is controlled so that the source / drain region 8 of the MOS transistor in the memory region has an impurity concentration lower than that of the high concentration source / drain region 7b in the logic element region. By controlling the impurity concentration in this manner, the retention characteristic of the memory element can be improved and the operation characteristic of the logic element can be accelerated. Note that the ion implantation in FIGS. 4B and 4C may be performed in the same process.

  A Co film is formed on the entire surface of the silicon substrate by sputtering. Silicide reaction is caused by rapid thermal (RTA) to form silicide layers 25 and 26. Unreacted Co film is removed with aqua regia.

  As shown in FIG. 4F, a silicon oxide film 12 having a planarizing function is deposited on the silicon substrate 1 so as to cover the oxide film 11. For example, a borophosphosilicate glass (BPSG) film or a silicon oxide film using tetraethoxysilane (TEOS) is deposited.

  In order to flatten the surface, reflow or CMP may be performed. Further, a three-layer structure can be adopted as the interlayer insulating film instead of the two-layer structure. In this case, a stacked layer of a silicon oxide film, a silicon nitride film, a silicon oxide film, or the like can be used instead of the two-layer silicon oxide film.

  As shown in FIG. 4F, a contact hole 13 penetrating the silicon oxide films 12 and 11 is formed using a resist mask. A conductive layer such as a polycrystalline silicon layer doped with P and a WSi film is grown so as to fill the contact hole, thereby forming a wiring layer. Thereafter, a resist mask is formed on the wiring layer and patterned to obtain the wiring 14. The left wiring 14 in the figure constitutes the bit line BL, and the right wiring 14 in the figure constitutes the match line ML.

  Note that a single-layer conductive layer such as a polycrystalline silicon layer can be used as the wiring layer, or three or more layers such as a Ti layer, a TiN layer, and a W layer can be used. The wiring should just have desired electroconductivity.

  Thereafter, the insulating layer 15 (FIG. 3) is formed on the insulating layer 12 so as to cover the wiring 14. After the contact hole for capacitor contact is formed, a conductive layer such as polycrystalline silicon is formed on the insulating layer 15 and patterned to form storage electrodes and connection terminals. Further, a capacitor dielectric film and a cell plate electrode are formed to form a CAM cell.

  In the configuration of FIG. 2, separate contact holes are formed on one source / drain region of the memory element and one gate electrode of the logic element. Instead of this configuration, a single contact hole can be formed.

  FIG. 5 shows a configuration in which one source / drain region of a memory element and one gate electrode of a logic element are connected using a single contact hole. A contact hole 16 is formed in the insulating film above the end of the active region ARM of the memory element and the contact part of the gate electrode G1 of the logic element, and the contact hole 16 is embedded to form the connection terminal CTJ. The The connection terminal CTJ electrically connects one source / drain region of the memory element, the storage electrode, and one gate gate electrode G1 of the logic element. The other points are the same as the configuration of FIG.

  FIG. 6 shows a cross-sectional configuration along the line VI-VI in FIG. The contact hole 16 also serves as the two contact holes 16 shown in FIG. 3, and has a wide cross-sectional area. At the bottom of the contact hole 16, one source / drain region 8 of the memory element and the gate electrode G1 of the logic element are exposed. The connection terminal CTJ is formed by filling the contact hole 16 and electrically connects the source / drain region 8 and the gate electrode G1. The other points are the same as the configuration of FIG.

  FIG. 7 shows a configuration in which a plug is used as a part of the connection terminal. The silicide layer is formed on the source / drain region of the logic element MOS transistor, but not on the gate electrode.

  As shown in the figure, a field insulating film 2 and a gate insulating film 3 are formed on a semiconductor substrate 1 as in the previous embodiment. A gate electrode 5 is formed on the gate insulating film 3. The upper surface and side surfaces of the gate electrode 5 are covered with a silicon nitride film 11a. A silicon oxide film 11b is formed on the substrate 1 so as to cover the silicon nitride film. The silicon nitride film 11a and the silicon oxide film 11b are collectively referred to as a first insulating film 11.

  In the logic element region, the source / drain region 7 of the logic element transistor has an LDD structure including a low impurity concentration region 7a and a high impurity concentration region 7b, and a silicide layer 26 formed thereon. In order to create the LDD structure, the silicon nitride film 11a is removed from the source / drain regions by forming side spacers on the side walls of the gate electrode 5.

  A silicon nitride film having the same shape as the gate electrode is previously formed on the upper surface of the gate electrode. Even if the silicon nitride film on the flat surface is etched by anisotropic etching for forming the side spacer and the source / drain regions are exposed, the silicon nitride film remains on the upper surface of the gate electrode. That is, the upper surface and side surfaces of the gate electrode are kept covered with the silicon nitride film. In this anisotropic etching, the insulating film 11a in the logic element region is etched, and its thickness is smaller than that of the insulating film 11a in the memory element region.

  By performing the salicide process in this state, a silicide layer is formed on the high concentration source / drain region of the logic element transistor. Since the gate electrode 5 is covered with the silicon nitride film 12a, no silicide layer is formed. After the salicide process, a silicon oxide film 11b is formed on the silicon substrate 1 so as to cover the silicon nitride film 11a.

  A contact hole is formed on the source / drain region 8 of the memory element so as to penetrate the first insulating film 11 and expose the silicon nitride film on the side surface of the gate electrode. Conductive plugs 31 and 32 made of crystalline silicon are formed.

  A second insulating film 12 is deposited on the first insulating film 11, and a contact hole reaching the plug 31 on one source / drain region 8 of the memory element and one source / drain region 7 of the logic element. 13 is formed. A conductive layer 14 that fills the contact hole from the surface of the second insulating layer 12 is formed, and a bit line BL and a match line ML are formed.

  A third insulating layer 15 is formed on the substrate so as to cover the wiring 14. A contact hole 16 is formed from the surface of the third insulating layer 15 to reach the plug 32 on one source / drain region 8 of the memory element and the separated gate electrode G1 of the logic element. Region 17 is formed, and storage electrode SN and connection terminals CTM and CTL are formed. A capacitor dielectric film 18 and a cell plate electrode 19 are formed covering the storage electrode to form a CAM cell.

  At this time, the conductive layer 17 forming the storage node SN of the capacitor only needs to reach the upper surface of the plug 32 in the memory element region, and the connection terminal can be formed more stably. In the etching for forming the contact hole, the upper surface of the plug 32 may be dug as indicated by a broken line.

  Even in the case of using a plug, the source / drain region 8 of the memory element and the gate electrode G1 of the logic element can be connected by one connection terminal, as in the configuration of FIG.

  FIG. 8 shows a configuration example in this case. The plugs 31 and 32 have the same configuration as that of the embodiment of FIG. The upper surface of the plug 32 has a step formed by an etching process. A contact hole straddling the plug 32 and the gate electrode G1 is formed, and the connection terminal CTJ is formed by filling the contact hole. The common connection terminal CTJ electrically connects the storage electrode 17, the plug 32, and the gate electrode G. The other points are the same as in FIG.

  9A to 9E show a manufacturing process for manufacturing the CAM structure shown in FIGS. 7 and 8, taking the case of FIG. 8 as an example.

  As shown in FIG. 9A, the field insulating film 2 and the gate oxide film 3 are formed on the surface of the silicon substrate 1 as in the above-described embodiment. After the gate oxide film 3 is formed, a stack of a polycrystalline silicon layer 5 and a silicon nitride layer 6 is deposited on the silicon substrate surface. A resist mask is formed on the surface of the silicon nitride layer 6, and the polycrystalline silicon layer 5 and the silicon nitride layer 6 are patterned into the same pattern. Thereafter, the resist mask is removed.

  As shown in FIG. 9B, separate ion implantation is performed on the memory element region and the logic element region using a resist mask. Low concentration source / drain regions 7a are formed in the logic element region, and source / drain regions 8 are formed in the memory element region. Thereafter, a silicon nitride film 11a is deposited on the surface of the silicon substrate, the memory element region is covered with a resist mask, and anisotropic etching is performed.

  In the logic element region, the silicon nitride film 11 a on the source / drain region 7 is removed, and a side spacer is left on the side wall of the gate electrode 5. The silicon nitride film 11a is integrated with the underlying silicon nitride film 6, and the upper and side surfaces of the gate electrode are covered with the silicon nitride film. For convenience of illustration, these silicon nitride films 6 and 11a are collectively indicated by 11a. At the boundary between the logic element region and the memory element region, a step is formed in the silicon nitride film 11a by the amount etched by anisotropic etching.

  As shown in FIG. 9C, n-type impurities such as As are further ion-implanted into the logic element region in which the side spacers are formed. When a CMOS structure is manufactured, a resist mask is used, and separate ion implantation is performed on the n-channel MOS region and the p-channel MOS region. Thereafter, the resist mask is removed. In this manner, source / drain regions having an LDD structure having a higher impurity concentration than the source / drain regions of the memory element region are formed in the logic element region. The source / drain regions 8 in the memory element region are kept at a low impurity concentration, and the retention characteristics of the memory are kept high.

  After the high concentration source / drain regions are formed, a Co film is formed on the silicon substrate 1 by sputtering. A heat treatment using RTA is performed to cause a salicide reaction between the Co film and the exposed Si surface, thereby forming a silicide layer 26. Unreacted Co film is removed with aqua regia.

  As shown in FIG. 9D, another insulating film 11b is formed on the surface of the silicon substrate. For example, a stack of a silicon nitride film and a BPSG film is formed and reflowed to form a flat surface. Instead of the silicon nitride film, a laminate such as a CVD silicon oxide film or a laminate of a silicon oxide film and a silicon nitride film may be used. Further, instead of reflowing or subsequent to reflowing, CMP may be performed and further planarization may be performed.

  A resist mask is formed on the insulating layer 11b, and contact holes that expose the source / drain regions 8 of the memory element region are formed. In this contact hole forming step, the silicon nitride film covering the gate electrode realizes a self-aligned contact step. Thereafter, the resist mask is removed, a polycrystalline silicon layer doped with an n-type impurity such as P is deposited, and the conductive layers on the insulating film 11b are removed by CMP or the like, thereby forming plugs 31 and 32.

  As shown in FIG. 9E, an insulating film 12 such as a silicon oxide film is further formed on the insulating film 11b, and a contact hole 13 is formed using a resist mask. A polycrystalline silicon layer or a stacked layer of a polycrystalline silicon layer and a WSi layer is formed on the insulating film 12 in which the contact holes 13 are formed, and is patterned using a resist mask. In this way, the wiring 14 is formed.

  Further, an interlayer insulating film 15 (FIGS. 7 and 8) such as a silicon oxide film or a BPSG layer is deposited, and the surface is flattened by performing reflow. Further, CMP may be performed. Contact holes are formed using a resist mask. Depending on the shape of the resist mask, the structures of FIGS. 7 and 8 can be selectively formed.

  A polycrystalline silicon layer is deposited so as to fill the contact hole. The polycrystalline silicon layer is patterned to form storage electrodes SN and connection terminals CT (CTM, CTL, CTJ). Subsequently, a storage capacitor structure is formed by depositing the capacitor insulating film 18, depositing the polysilicon layer 19, and patterning. If necessary, the CAM device is completed by forming an insulating layer such as BPSG, reflow, CMP, contact hole formation, and wiring layer formation.

  Note that the configuration within the CAM repeating unit is not limited to that shown in FIGS.

  FIG. 10 shows a modification of the planar arrangement. Compared with the structure of FIG. 2B, the positions of the gate electrode G1 separated from the logic element and the gate electrode G2 connected to the data bus line DB are exchanged. An equivalent circuit is shown in FIG. The word line WL is curved so as to surround the bit line contact. Further, the active region ARM of the memory element includes both end regions parallel to the signal lines GND, BL, and ML, and a region extending obliquely therebetween. It is desirable that the word line WL and the active region ARM are substantially orthogonal.

  Further, as in the embodiment of FIG. 5, one source / drain region of the active region ARM and the gate electrode G1 separated from the logic element are connected by a connection terminal CTJ formed in a single contact hole. The other points are the same as in the embodiment of FIG.

  FIGS. 11A and 11B show another modification. FIG. 11A shows a planar arrangement, and FIG. 11B shows a cross-sectional configuration. Similar to the configuration example of FIG. 10, the active region ARM for the memory element has a bent shape, and the word line WL has a curved shape in a region surrounding the bit line contact region. The separated gate electrode G1 in the logic element region is disposed in a region between the ground line GND and the bit line BL. The gate electrode G2 connected to the data bus line DB is disposed in a region between the bit line BL and the match line ML.

  The contact region of the gate electrode G1 is spaced from the right end of the memory element active region ARM upward in FIG. 11A, and is disposed in a region between the bit line BL and the ground line GND beyond the bit line BL. Yes. By disposing the right end of the memory element active region ARM and the separated gate electrode G1 in different regions, it is possible to effectively use the horizontal dimension in the drawing. The arrangement of the separated gate electrode G1 and the gate electrode G2 connected to the data bus line DB is the same as in the case of FIG. An equivalent circuit is shown in FIG.

  As shown in FIGS. 11A and 11B, the connection terminal CTM for the memory element and the connection terminal CTL for the logic element are arranged with the bit line BL interposed therebetween, as shown in FIG. 11A. Is arranged. The other points are the same as the configurations of FIGS.

  FIG. 12 shows still another configuration example. In this configuration example, the active region ARM for the memory element and the active region ARL for the logic element both have a shape extending in the lateral direction, and further have a portion protruding upward for the contact.

  The word line WL that also serves as the gate electrode of the memory element, the separated gate electrode G1 for the logic element, and the data bus line DB that also serves as the gate electrode G2 all have a shape extending in the vertical direction. The word line WL has a curved shape in a region surrounding the bit line contact region.

  Further, the bit line BL and the match line ML are formed extending in the horizontal direction in the same wiring layer above the gate electrode, and the storage electrode SN and the ground line GND are formed by the upper conductive layer. One source / drain region of the memory element and the separated gate electrode G1 of the logic element are connected by a single connection terminal CTJ. In addition, although the case where the ground line GND is extended in the horizontal direction has been shown, it may be extended in the vertical direction. An equivalent circuit is shown in FIG.

  FIG. 13 shows still another configuration. In this configuration, the active region ARM of the memory element region has a shape extending in the lateral direction and a contact portion protruding upward. The active region ARL of the logic element region has a shape extending in the vertical direction. The word line WL in the memory element region has a curved shape so as to surround the bit line contact in the bit line contact region.

  The gate electrode of the logic element region extends in the lateral direction. The data bus line DB is formed of a metal wiring layer above the gate electrode. One source / drain region of the memory element region and the contact region of the gate electrode G1 separated from the logic element region are arranged apart in the vertical direction with the bit line interposed therebetween. An equivalent circuit is shown in FIG. The match line ML and the ground line GND are formed of a metal wiring layer different from the bit line BL. In this case, the plugs PM and PG may be formed in the contact region with the same wiring layer as the data bus line DB. With this configuration, the wiring of the logic circuit has a low resistance, and high-speed operation is promoted.

  FIG. 14 shows still another configuration example. In this configuration, the active region ARM of the memory element and the active region ARL of the logic element each have the same planar shape as that of the configuration of FIG. 13, but their relative relationship is changed. In the upper part of the figure, the memory element active region ARM extends in the lateral direction and has a contact region protruding downward. The word line WL extends linearly in the vertical direction.

  A gate electrode G2 connected to a separated gate electrode G1 and an upper database line DB through a contact hole is formed to extend in the horizontal direction so as to cross the logic element active region ARL extending in the vertical direction. ing.

  The data bus line DB is formed of the same upper conductive layer as the ground line GND and the bit line BL. These signal lines GND, BL, DB are arranged extending in the horizontal direction. The match line ML is formed of the same conductive layer as the gate electrode, and is arranged extending in the vertical direction in parallel with the word line WL. The match line ML is connected to one source / drain region of the logic element region by a connection terminal CM formed of the same conductive layer as the signal lines GND, BL, DB.

  Compared with FIG. 13, the arrangement of the data bus line DB and the match line ML is exchanged. The configuration of the connection terminals CTM and CTL via the storage electrode is the same as that shown in FIG.

  FIG. 15 shows still another configuration. A bit line contact region of the memory element active region ARM is formed to protrude upward, and a bit line BL is disposed immediately below the ground line GND. Compared with the configuration of FIG. 14, the bit line BL is moved above the memory element active region ARM. Accordingly, the contact hole of the memory element active region ARM is also moved upward.

  16 to 24 show a manufacturing process of a CAM semiconductor device according to another embodiment of the present invention.

  16A and 16B show a state in which an active region is defined on a semiconductor substrate and a gate electrode is manufactured on the active region via a gate oxide film. FIG. 16A shows a plan view, and FIG. 16B shows a cross-sectional view.

  As shown in FIG. 16B, an isolation insulating region 2 such as silicon oxide is formed on the surface of the semiconductor substrate 1 by LOCOS or STI. The region where the isolation insulating region 2 is not formed and the surface of the semiconductor substrate 1 is exposed becomes the active region.

  Note that a well structure such as an n-type well 1n and a p-type well 1p is formed in the silicon substrate 1 as necessary. Since the left and right p-type wells 1p are separated, hot electrons generated during the operation of the logic transistor do not reach the DRAM cell and have excellent retention characteristics. However, by making both p-type wells the same well, the retention characteristics are deteriorated, but the cell area can be reduced as a whole by reducing the size.

  In the following drawings, the well structure is omitted for simplification. After forming a gate insulating film such as a silicon oxide film on the surface of the active region of the silicon substrate 1, a polycrystalline silicon layer is deposited and patterned to form a gate electrode 5 (including signal lines).

  After forming the gate electrode, impurities are ion-implanted into the active region using a resist mask as necessary. A source / drain region of the transistor for the memory element and a low concentration source / drain region of the transistor for the logic element are formed.

  In the plan view of FIG. 16A, a logic element active region ARL extending in the vertical direction is formed at the central portion, and a memory element active region ARM extending in the horizontal direction is formed on both sides thereof. A gate electrode 5 is formed on the logic element active region ARL. The gate electrode 5 traverses the active region in the lateral direction. The memory element active region ARM crosses the active region in the vertical direction. A gate electrode extending as a wiring layer on the isolation insulating region is formed. In the figure, four repeating units U11, U12, U21, and U22 are shown. The repeating units U11 and U21 and the repeating units U12 and U22 have a symmetrical configuration, and the repeating units U11 and U12 and the repeating units U21 and U22 have a vertically symmetrical configuration.

  FIGS. 17A, 17B, and 17C show a process of forming an insulating film such as silicon oxide on the silicon substrate 1 so as to cover the gate electrode, and performing a salicide reaction after removing a part thereof.

  As shown in FIG. 17A, a silicon oxide film 11 is deposited on the entire surface of the silicon substrate so as to cover the gate electrode. On this silicon oxide film 11, a mask M1 such as a photoresist is formed. The mask M1 covers the memory element region and exposes the logic element region. In this state, the silicon oxide film 11 is anisotropically etched. In the area covered with the mask M1, the silicon oxide film 11 remains as it is. In the logic element region exposed from the opening of the mask M1, the silicon oxide film 11 on the flat surface is removed, and the side wall spacer 11a remains only on the side wall of the gate electrode.

  FIG. 17C shows a side wall spacer 11 a formed on the side wall of the gate electrode 5.

  After the side wall spacer 11A is formed, ion implantation for forming a high concentration source / drain region is performed on the transistor in the logic element region. The transistor in the logic element region is a transistor having an LDD structure. Thereafter, the mask M1 is removed.

In the case of forming a CMOS semiconductor device, the mask M1 is removed after the side spacers are formed. Next, a photoresist is applied to form a photoresist pattern that opens the NMOS portion of the logic element region. N-type impurities are ion-implanted at a high concentration to form n ⁺ -type source / drain regions. Next, the photoresist pattern is removed, a new photoresist is applied, and a photoresist pattern opening the PMOS portion is formed. By implanting BF ₂ ions at a high concentration, p ⁺ type source / drain regions are formed. Thereafter, the photoresist pattern is removed.

  Thereafter, a Co film is formed on the entire surface of the silicon substrate by sputtering. After the Co film is formed, heat treatment is performed by RTA or the like to cause a silicide reaction between the Co film and the underlying silicon surface. In this way, the silicide film 25 is formed on the surface of the gate electrode 5. Note that a silicide film is also formed on the surface of the logic element active region ARL shown in FIG.

  Note that a nitride film can be used instead of the oxide film as a film for forming the sidewall spacer.

  As shown in FIG. 18B, an insulating film 12 such as BPSG is formed as an interlayer insulating film over the entire surface of the substrate 1 so as to cover the silicon oxide film 11 and the silicide layer 25. A resist layer is applied on the surface of the insulating film 12 to form a mask M2 having an opening for forming a contact hole.

  FIG. 18A is a plan view showing an opening portion of the mask M. FIG. The mask M2 has an opening 13a in the bit line contact portion in the memory element region.

  FIG. 18C shows a state in which an opening 13 is formed in the insulating film 12 using the mask M2.

  Note that after the insulating film 12 is formed, the surface is preferably planarized by reflow, CMP, or the like.

  As shown in FIG. 19B, a conductive layer made of a polycrystalline silicon layer and a WSi layer is formed on the insulating film 12 so as to fill the opening 13, and patterned to form a bit line BL or the like. A wiring layer 14 is formed. The bit line extends over a connection node of logic transistors connected in series. Therefore, a sufficiently large distance from the source / drain contact hole of the logic element to be formed later can be ensured. This is a key point for realizing high-speed operation by forming wirings such as ML and DB with a low-resistance metal wiring such as Al.

  FIG. 19A shows a planar pattern of the formed bit lines 14a and 14b. As shown in FIGS. 19B and 19C, after the bit line 14 is formed, an insulating film 15 serving as another interlayer insulating film is deposited on the insulating film 12 so as to cover the bit line 14. A mask such as a photoresist is formed on the insulating film 15, and the contact hole 16 of the capacitor is etched.

  As shown in FIG. 19C, a contact hole 16a reaching the source / drain of the memory cell transistor and a contact hole 16b reaching the gate electrode of the logic element are formed at positions facing each other across the bit line 14. Yes. With the configuration in which the contact hole is formed across the bit line, the lateral cell size is reduced. Even after the insulating layer 15 is formed, it is desirable to perform planarization by reflow, CMP, or the like.

  As shown in FIG. 20B, a storage capacitor electrode 17 is formed by depositing and patterning a conductive film such as polycrystalline silicon so as to fill the contact holes 16a and 16b.

  As shown in FIG. 20A, the storage capacitor electrode 17 covers the main part of the memory cell transistor and has a rectangular shape. Although a pillar type storage capacitor electrode is shown, other shapes such as a cylinder type may be employed. Further, a large number of hemispherical protrusions may be formed on the surface to increase the surface area.

  As shown in FIG. 21B, after forming a capacitor dielectric film covering the storage capacitor electrode 17, a conductive layer to be a cell plate electrode is formed and patterned to form a cell plate electrode 19.

  As shown in FIG. 21A, the cell plate electrode 19 substantially covers the entire memory element region. Note that the cell plate electrode 19 extends outside the illustrated region and is maintained at the same potential (for example, Vcc / 2 potential).

  As shown in FIG. 22, an insulating film 40 serving as an interlayer insulating film is formed on the entire surface of the silicon substrate so as to cover the cell plate electrode 19, and contact holes 41 and 42 are opened using a resist mask or the like.

  As shown in FIG. 23, a metal wiring layer is formed on a silicon substrate so as to embed a contact hole, and patterning is performed, whereby database lines 44a and 44b and extraction electrodes 45, 46, and 47 in source / drain regions of logic element transistors are formed. Create Here, the electrodes 45 and 47 are arranged so as to extend in the direction in which the electrodes adjacent to the left and right approach, and the electrode 46 is extended in the direction in which the electrodes adjacent to the left and right move away.

  With this arrangement, the match line ML and the ground wiring GND can be wired in the same direction on the same wiring layer. Further, by forming the database line DB by the first layer (lower layer) wiring and forming the match line ML and the ground wiring GND by the second layer (upper layer) wiring, the arrangement of the contact holes 41 and 42 can be simplified. The area of the logic circuit is reduced.

  As can be seen from the contact hole arrangement in FIG. 22, the contact holes 42 are arranged on both sides of the contact hole 41, and how these wirings are formed determines the area of the cell. The above configuration is optimal from these viewpoints.

  It is preferable to further form a cell plate contact hole and a word line lead contact hole, and simultaneously form the cell plate electrode contact power supply wiring 44c and the stack electrode 44d for pulling out the word line WL. For example, as shown in the figure, power supply wirings 44c that contact the cell plate are provided at the upper and lower ends of the cell block. Further, a stack electrode 44d that contacts the word line is provided between the cell blocks. The power supply wiring that contacts the cell plate can also be formed in the same wiring layer as the bit line.

  Thereafter, an insulating film 48 to be an interlayer insulating film is formed on the entire surface. The insulating film 48 is preferably planarized by reflow, CMP, or the like. A photoresist pattern is formed on the insulating film 48 to form a contact hole 49.

  As shown in FIG. 24A, an upper metal wiring layer is formed so as to embed a contact hole, and patterning is performed to form wirings 51a, 51b (collectively referred to as 51), 52a, 52b (collectively referred to as 51). Collectively referred to as 52). The wirings 51a and 51b are, for example, ground wirings, and the 52a and 52b are, for example, match lines. At the same time, word line backing wirings 53a and 53b for backing the word line through the lower layer stack electrode 44d are formed. The word line is a wiring of polycrystalline silicon or polycide extending in the vertical direction in the figure, and has a relatively high resistance. For example, the resistance value can be greatly reduced by connecting the backing metal wiring between the cell blocks.

  FIG. 24B shows a planar layout of wirings formed at a level above the gate electrode (word line). First, bit lines BL (14a, 14B) are formed in the horizontal direction in the drawing, and database lines 44a, 44b (and cell plate power supply wiring 44c) formed of a metal wiring layer so as to overlap the bit lines BL are formed thereon. It is formed extending in the horizontal direction. In the uppermost layer, a match line ML and a ground line GND (and a word line backing wiring) are formed in a direction substantially orthogonal to the bit line BL and the data bus line DB.

  Since the logic element region is connected to the match line ML, the data bus line DB, and the ground line GND formed by the metal wiring layer, high-speed operation is easy.

  Although the embodiment in which one CAM cell is formed by two DRAMs and four n-channel transistors has been described above, the number of DRAM cells can be reduced.

  FIG. 25A is an equivalent circuit diagram of a CAM cell according to another embodiment of the present invention.

  A memory cell MC is configured by the memory cell transistor MM and the capacitor C. Two sets of series-connected transistors are connected between the match line ML and the ground line GND. Each series connection transistor is constituted by series connection of p-channel transistors MP1 and MP2 and n-channel transistors MN1 and MN2. The database line DB is connected to the gate electrodes of the p-channel transistor MP1 and the n-channel transistor MN2.

  The storage electrode of the memory cell is connected to the gate electrodes of the p-channel transistor MP2 and the n-channel transistor MN1. That is, each series-connected transistor is formed of a CMOS transistor, one of which is controlled by the potential of the data bus line DB, and the other is controlled by the accumulated potential of the capacitor C. Bit line BL is connected to the other source / drain region of transistor MM of the memory cell.

  In the CAM cell of FIG. 1A, the memory cell MC is composed of two DRAM cells, whereas in FIG. 25A, it is composed of one DRAM cell. In FIG. 1A, two data bus lines and bit lines are used, respectively. In FIG. 25A, one data bus line DB and bit line BL are used.

  FIG. 25B is a table showing the logical operation of the CAM cell in FIG. The column of DRAM indicates the potential of the storage electrode of the capacitor C, where H is a high potential and L is a low potential. The DB column indicates the potential of the data bus line DB, where H indicates a high potential and L indicates a low potential. The PMOS column shows the on / off state of the p-channel transistors MP1 / MP2. The NMOS column shows the on / off state of the n-channel transistors MN1 / MN2. The ML column indicates whether the match line ML precharged to a high potential maintains a high potential after a logic operation or discharges to a low potential.

  For example, when the DRAM is at a high potential (H), the n-channel transistor MN1 is on and the p-channel transistor MP2 is off. When the data bus line DB is at a high potential (H), the p-channel transistor MP1 is off and the n-channel transistor MN2 is on. Therefore, when both DRAM and DB are H, one of the transistors connected in series is turned off, and the match line ML is maintained at H.

  When the DRAM is L, the n-channel MN1 is turned off and the p-channel transistor MP2 is turned on. Therefore, the series connection of the p-channel transistor MP2 and the n-channel transistor MN2 is turned on, and the match line ML is discharged and becomes L.

  When the DRAM is kept at H and DB is set at L, the p-channel transistor MP1 is turned on and the n-channel transistor MN2 is turned off. Accordingly, the other series transistors MP1 and MN1 are both turned on, and the match line ML is discharged and becomes L.

  When the DRAM is L and the DB is also L, the reverse state is obtained when the DRAM is H and DB is H, and both the n-channel transistors MN1 and MN2 are turned off. Therefore, the match line ML is not discharged but kept at H. It is.

  Thus, the CAM cell in FIG. 25A also performs the same logical operation as the CAM cell shown in FIG. Hereinafter, a manufacturing process for creating the CAM cell shown in FIG. 25A will be described with reference to FIGS.

  As shown in FIG. 26A, an isolation insulating film 2 that defines active regions ARL1, ARL2, and ARM is formed on the surface of the silicon substrate 1 by LOCOS or STI. The active region ARL1 is an n-type well for a logic element, and is a region for forming a p-channel transistor. The active region ARL2 is a p-type well for a logic element, and is a region for forming an n-channel transistor. The active region ARM is a p-type well for creating a memory element transistor. After forming a gate oxide film on the surface of the active region, a polysilicon layer is deposited and patterned to form a gate electrode of each transistor. In the logic element region, gate electrodes G1 and G2 are formed. Each of the gate electrodes G1 and G2 has a portion crossing the n-type active region ARL1 and a portion crossing the p-type active region ARL2. In the memory element region, the word line WL also serving as a gate electrode crosses the p-type active region ARM in the lateral direction.

  After the interlayer insulating film covering the gate electrode is formed, the connection terminal CT1 for connecting the bit line BL and the gate electrode G1 of the logic element to one source / drain region of the memory transistor is formed by the second polycrystalline silicon layer. It is formed. A second interlayer insulating film is formed so as to cover the second polycrystalline silicon layer, and a storage electrode SN of the memory element is formed by the third polycrystalline silicon layer. A lower wiring layer is formed by these three polycrystalline silicon layers.

FIG. 26B illustrates a cross-sectional structure along the dashed-dotted line U-U in FIG. A deep n ⁺ -type buried layer W1 is formed on the surface portion of the silicon substrate 1, and an n-type well W2 is formed thereon. A p-type well W3 is formed in a partial region of the n-type well W2. An n-type well is formed in the region where the p-channel transistor is to be formed instead of the p-type well W3. An isolation insulating film 2 formed by STI is disposed on the surface portion of the silicon substrate 1, and a gate oxide film 3 is formed on the surface of the active region defined by the isolation insulating film 2.

  A polycrystalline silicon layer 5 serving as a gate electrode is formed on the gate oxide film 3, and source / drain regions 8 formed by ion implantation of n-type impurities are formed on both sides of the polycrystalline silicon layer 5. In the logic element region, source / drain regions corresponding to the respective conductivity types are formed on both sides of each gate electrode. A first interlayer insulating film 11 is formed to cover the gate electrode. The interlayer insulating film 11 is formed of two insulating layers. In the logic element region, the lower insulating layer is subjected to anisotropic etching, and sidewall spacers are formed on both sides of the gate electrode. After the sidewall spacers are formed, ion implantation is further performed to form high concentration source / drain regions.

  Contact hole 13 is formed in first interlayer insulating film 11, and a polycrystalline silicon layer is deposited so as to fill contact hole 13. The polycrystalline silicon layer is patterned to form the polycrystalline silicon wiring 14 constituting the connection terminal CT1 and the bit line BL.

  A second interlayer insulating film 15 is formed covering the polycrystalline silicon wiring 14. A contact hole 16 reaching the one source / drain region of the memory element transistor is formed from the surface of the second interlayer insulating film, and a polycrystalline silicon layer is deposited so as to fill the contact hole 16. The polycrystalline silicon layer is patterned to form a memory element storage electrode 17.

  The case where the connection terminal CT1 connects the gate electrode 5 (G1) and the source / drain region 8 and the storage electrode 17 of the capacitor extends downward to contact the source / drain region 8 has been described. Similarly, the storage electrode, the gate electrode 5 (G), and the source / drain region 8 may be connected by one or two connection terminals.

  As shown in FIG. 27, a third interlayer insulating film is formed on the second interlayer insulating film 15 so as to cover the storage electrode, and a first metal wiring is formed thereon. The first metal wiring includes a database line DB, interconnection wirings CT2 and CT3 for connecting the p-channel transistor and the n-channel transistor, plugs PG1 and PG2 for connecting to the upper wiring layer, and a backing word line WLB in the memory element region. including. After forming the first metal wiring, a fourth interlayer insulating film is further formed, and a second metal wiring is formed thereon. The second metal wiring includes a ground line GND and a match line ML extending in the vertical direction in the drawing.

  FIG. 28 shows a cross-sectional structure taken along line XX of FIG. The logic element active region ARL2 is formed of a p-well W4. A silicide layer 25 is formed on the upper surface of the polycrystalline silicon gate electrode 5. An LDD structure having a low concentration source / drain region 7a and a high concentration source / drain region 7b is formed on both sides of the gate electrode 5, and a silicide layer 26 is further formed on the surface thereof. The first interlayer insulating film 11 includes a sidewall spacer 11a on the side wall of the gate electrode and an insulating layer 11b thereon.

  A second interlayer insulating film 15 is formed on the first interlayer insulating film 11, and after a memory element capacitor is formed, a third interlayer insulating film 21 is formed. After the contact hole is formed in the third interlayer insulating film 21, the first metal wiring 22 is formed. In the illustrated configuration, the first metal wiring 22 includes interconnection wirings CT1 and CT2 and a plug PG2.

  A fourth interlayer insulating film 23 is formed on the first metal wiring 22, and after the contact hole is formed, the second metal wiring 24 is formed. The ground metal wiring 24 is connected to the plug PG2. Note that the match line ML is also connected to the plug PG1 at a place other than the illustrated location.

  FIG. 29 shows a cross-sectional structure taken along line YY in FIG. The logic element active region ARL1 is formed of an n-type well W2, and the logic element active region ARL2 is formed of a p-type well W3 formed in the n-type well W2. The gate electrode formed on the n-type well W2 is formed of p-type polycrystalline silicon doped with a large amount of p-type impurities, and the logic element gate electrode 5 formed on the p-type well W3 is formed of n-type impurities. Is formed of n-type polycrystalline silicon doped with a large amount. Silicide layers 25 are formed on the surfaces of these silicon layers 5.

  In the memory element region, a capacitor dielectric film 18 and a cell plate electrode 19 are formed on the configuration of FIG. 26B, and a memory element capacitor is formed together with the storage electrode 17. A third interlayer insulating film 21 is formed so as to cover the capacitor, and a contact hole reaching the gate electrode G2 is formed. A first metal wiring 22 is formed on the third interlayer insulating film 21.

  The first metal wiring 22 includes a data bus line DB and a backing word line WLB reaching the gate electrode G2. A fourth interlayer insulating film 23 is formed so as to cover the first metal wiring 22, and a second metal wiring is formed as shown in FIG. Further, an interlayer insulating film and an upper wiring layer are formed as necessary, and the semiconductor device is completed.

  The CAM cell of this configuration is also easy to operate at high speed because the transistors constituting the logic elements are driven by a database line DB, a match line ML, a ground line GND, and a metal interconnection line formed of metal. The silicide layer on the gate electrode and the silicide layer on the source / drain regions also promote high speed operation.

  In addition, various arrangements can be employed depending on the peripheral circuit configuration and the like. Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

In addition, the following is disclosed about this invention.
[Supplementary Note 1] A semiconductor device having a semiconductor substrate and a plurality of unit structures formed on the semiconductor substrate, forming a memory element and a logic element, and having the same or symmetrical planar shape. An isolation insulating region having a structure formed on a surface of the semiconductor substrate and defining first and second active regions; a first gate electrode formed across the first active region; and A transfer transistor having a pair of first source / drain regions formed on both sides of the first gate electrode in the first active region; a word line connected to the first gate electrode; A bit line connected to one of the pair of first source / drain regions; second and third gate electrodes formed across the second active region; and the second active The second and third gates in the region. A connection node formed in the middle of the first electrode, a pair of second source / drain regions formed outside the second and third gate electrodes, the connection node and the pair of second electrodes A serial connection transistor including a silicide electrode formed on the source / drain region; a first signal line connected to the silicide electrode on one of the pair of second source / drain regions; A second signal line connected to the silicide electrode on the other of the second source / drain regions, a third signal line connected to the second gate electrode, and the pair of first source / drain regions A storage electrode formed in a region including the other of the drain region and at least part of the third gate electrode; a capacitor dielectric film formed on a surface of the storage electrode; and the capacitor dielectric film Shape A counter electrode, a first conductive connection member formed below the storage electrode and connecting the storage electrode and the other of the pair of first source / drain regions, and formed below the storage electrode And a second conductive connection member connecting the storage electrode and the third gate electrode.
[Appendix 2] The semiconductor device according to Appendix 1, which is a conductive connection member in which the first and second conductive connection members are integrated.
[Supplementary Note 3] The semiconductor device according to Supplementary Note 1, wherein the bit line is disposed between the first and second conductive connection members.
[Supplementary Note 4] The impurity concentration of the connection node formed in the second active region and the pair of second source / drain regions is determined by the pair of the first source / drain formed in the first active region. 4. The semiconductor device according to any one of appendices 1 to 3, wherein the concentration is higher than the impurity concentration of the drain region.
[Supplementary Note 5] The first connection member is formed of a conductive plug formed on the other of the pair of first source / drain regions and the conductive plug, and is made of the same material as the storage electrode. The semiconductor device according to any one of appendices 1 to 4, including the formed first storage electrode extension.
[Appendix 6] The semiconductor device according to Appendix 5, wherein the conductive plug has a step shape dug below the first storage electrode extension.
[Appendix 7] The semiconductor device according to any one of appendices 1 to 5, wherein the second connection member includes a second storage electrode extension formed of the same material as the storage electrode.
[Supplementary Note 8] Furthermore, the bit line driver for driving the bit line, the word line driver for driving the word line, and the potential of the first signal line formed in a region outside the plurality of unit structures. The semiconductor device according to any one of appendices 1 to 7, further comprising: a match line driver that precharges the second signal line and detects a voltage after the precharge; and a data bus driver that drives the third signal line. .
[Supplementary Note 9] The third gate electrode includes an intrinsic gate electrode portion formed on the second active region via a gate insulating film and a contact formed on the isolation insulating region and having an enlarged width. The semiconductor device according to any one of appendices 1 to 8, wherein the second conductive connecting member is in contact with the contact portion.
[Supplementary Note 10] The semiconductor device according to Supplementary Note 9, wherein the third gate electrode extends on a straight line, and the first active region extends on the same straight line in the vicinity of the contact portion.
[Appendix 11] Two first sets of the word lines, the bit lines, and the first, second, and third signal lines are arranged in parallel with each other, and at least two of the remaining three second sets are arranged. 11. The semiconductor device according to any one of appendices 1 to 10, wherein the set is arranged in parallel to each other and crossing the first set.
[Appendix 12] The semiconductor device according to Appendix 11, wherein the first set is formed of a first conductive layer, and the second set is formed of a second conductive layer having a level different from that of the first conductive layer. .
[Supplementary Note 13] The semiconductor device according to Supplementary Note 12, wherein the storage electrode is formed of a third conductive layer having a level different from that of the first and second conductive layers.
[Supplementary Note 14] A semiconductor device having a semiconductor substrate and a plurality of unit structures formed on the semiconductor substrate, forming a memory element and a logic element, and having the same or symmetrical planar shape. An isolation insulating region having a structure formed on a surface of the semiconductor substrate and defining first and second active regions; a first gate electrode formed across the first active region; and A transfer transistor having a pair of first source / drain regions formed on both sides of the first gate electrode in the first active region; a word line connected to the first gate electrode; A bit line connected to one of the pair of first source / drain regions; second and third gate electrodes formed across the second active region; and the second active Within the region, the second and third gates A series connection transistor including a connection node formed in the middle of the gate electrode and a pair of second source / drain regions formed outside the second and third gate electrodes; Connected to one of the second source / drain regions and connected to the first signal line formed of the first type metal wiring and the other of the pair of second source / drain regions, The second signal line formed of the first type metal wiring in the same layer as the signal line of the second and the second type metal wiring connected to the second gate electrode and different from the first type metal wiring A storage electrode formed in a region including the other of the pair of first source / drain regions and at least part of the third gate electrode; and the storage electrode A capacitor dielectric film formed on the surface of the capacitor, and the capacitor A counter electrode formed on the dielectric film; and a first conductive connection member formed below the storage electrode and connecting the storage electrode and the other of the pair of first source / drain regions. A semiconductor device comprising a second conductive connection member formed below the storage electrode and connecting the storage electrode and the third gate electrode.
[Supplementary Note 15] The semiconductor device according to Supplementary Note 14, wherein the series-connected transistor includes a silicide electrode formed on the connection node and the pair of second source / drain regions.
[Supplementary Note 16] The semiconductor device according to Supplementary Note 14, wherein the bit line is formed of a third type wiring below the second type metal wiring.
[Supplementary Note 17] The semiconductor device according to Supplementary Note 16, wherein the bit line and the third signal line are arranged to overlap each other in plan view.
[Appendix 18] A semiconductor device having a plurality of identical or symmetrical unit structures formed on a semiconductor substrate and including a memory element and a logic element, each unit structure being formed in a first active region, A DRAM cell having a first transistor and a capacitor having a storage electrode, and a second cell having a second and third gate electrodes and silicided source / drain electrodes formed in the second active region. A semiconductor device comprising: a logic element having a third transistor connected in series; and a conductive connecting member formed below the storage electrode of the DRAM capacitor and connecting the storage electrode and the third gate electrode.
[Supplementary Note 19] A data bus line to which an input signal is applied, a match line to be precharged, a connection line, a memory cell having an insulated gate transistor capacitor, and each of the match line and the ground line. And having a first and a second series connection including a series connection of a p-channel transistor and an n-channel transistor, and a gate electrode of the first series-connected n-channel transistor and a second series connection A gate electrode of a p-channel transistor is connected to the storage electrode of the capacitor, and a gate electrode of a first series-connected p-channel transistor and a gate electrode of a second series-connected n-channel transistor are connected to the data bus line. A semiconductor device including a CAM cell having connected logic cells.
[Supplementary note 20] The semiconductor device according to supplementary note 19, wherein the data bus line, the match line, and the ground line are formed of metal wiring.
[Supplementary note 21] The semiconductor device according to supplementary note 20, wherein the first and second series connections include a metal wiring that connects the n-channel transistor and the p-channel transistor.

It is a top view of CAM, a logic table, and an equivalent circuit. 2 is a plan view showing a CAM repeating unit according to an embodiment of the present invention. It is sectional drawing which shows the cross-sectional structure of the structure of FIG. FIG. 4 is a cross-sectional view of a semiconductor substrate showing a manufacturing process for manufacturing the configuration of FIG. 3. It is a top view which shows the plane structure by the other Example of this invention. It is sectional drawing which shows the cross-sectional structure of the structure of FIG. It is sectional drawing which shows the cross-sectional structure of the semiconductor device by another Example. It is sectional drawing which shows the structure of the semiconductor device by another Example. It is sectional drawing of the semiconductor substrate which shows the manufacturing process for manufacturing the structure of FIG. It is a top view which shows the other example of a plane structure. It is the top view and sectional drawing which show the other example of a plane structure. It is a top view which shows the other example of a plane structure. It is a top view which shows the other example of a plane structure. It is a top view which shows the other example of a plane structure. It is a top view which shows the other example of a plane structure. It is the top view and sectional drawing for demonstrating the manufacturing method of the semiconductor device by another Example of this invention. It is the top view and sectional drawing for demonstrating the manufacturing method of the semiconductor device by another Example of this invention. It is the top view and sectional drawing for demonstrating the manufacturing method of the semiconductor device by another Example of this invention. It is the top view and sectional drawing for demonstrating the manufacturing method of the semiconductor device by another Example of this invention. It is the top view and sectional drawing for demonstrating the manufacturing method of the semiconductor device by another Example of this invention. It is the top view and sectional drawing for demonstrating the manufacturing method of the semiconductor device by another Example of this invention. It is a top view for demonstrating the manufacturing method of the semiconductor device by another Example of this invention. It is a top view for demonstrating the manufacturing method of the semiconductor device by another Example of this invention. It is the top view for demonstrating the manufacturing method of the semiconductor device by another Example of this invention, and a top view which shows electrode arrangement | positioning. 6 is an equivalent circuit diagram and a logic table of a CAM according to another embodiment of the present invention. FIG. 26 is a plan view and a cross-sectional view for explaining a method of manufacturing the CAM of FIG. It is a top view for demonstrating the manufacturing method of CAM of FIG. It is sectional drawing for demonstrating the manufacturing method of CAM of FIG. It is sectional drawing for demonstrating the manufacturing method of CAM of FIG.

Explanation of symbols

WL Word line DM Data bus line ML Match line GND Ground line BL Bit line CTM Memory element connection terminal CTL Logic element connection terminal CTJ Connection terminal SN Storage node (storage electrode)
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Field insulating film 3 Gate insulating film 5 Gate electrode 6 Silicon nitride layer 7, 8 Source / drain region 11 Insulating layer 11a Silicon nitride film 11b Silicon oxide film 12 Insulating layer 13, 16 Contact hole 14 Wiring layer 15 Insulating layer 17 Storage electrode 18 Capacitor dielectric film 19 Counter electrode (cell plate electrode)

Claims (10)

A semiconductor device having a semiconductor substrate and a plurality of unit structures formed on the semiconductor substrate, forming a memory element and a logic element, and having the same or symmetrical planar shape, wherein each unit structure is the semiconductor An isolation insulating region formed on a surface of the substrate and defining first and second active regions;
A first gate electrode formed across the first active region, and a pair of first source / drain formed on both sides of the first gate electrode in the first active region A transfer transistor having a region;
A word line connected to the first gate electrode;
A bit line connected to one of the pair of first source / drain regions;
Second and third gate electrodes formed across the second active region; and a connection node formed between the second and third gate electrodes in the second active region; A pair of second source / drain regions formed outside the second and third gate electrodes, the connection node, the pair of second source / drain regions, and a portion other than the partial region A serial connection transistor including a silicide electrode formed on the third gate electrode;
A first signal line connected to a silicide electrode on one of the pair of second source / drain regions;
A second signal line connected to a silicide electrode on the other of the pair of second source / drain regions;
A third signal line connected to the second gate electrode;
A storage electrode formed in a region including the other of the pair of first source / drain regions and at least part of the third gate electrode;
A capacitor dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the capacitor dielectric film;
A first conductive connection member formed below the storage electrode and connecting the storage electrode and the other of the pair of first source / drain regions;
A second conductive connection member formed below the storage electrode and connecting the storage electrode and the partial region of the third gate electrode;
A semiconductor device.   The semiconductor device according to claim 1, wherein the first and second conductive connecting members are integrated conductive connecting members.   The semiconductor device according to claim 1, wherein the bit line is disposed between the first and second conductive connection members.   The first conductive connection member is formed on the conductive plug formed on the other of the pair of first source / drain regions and on the conductive plug, and is formed of the same material as the storage electrode. 4. The semiconductor device according to claim 1, further comprising a first storage electrode extension.   In addition, the bit line driver for driving the bit line, the word line driver for driving the word line, and the second signal with respect to the potential of the first signal line, formed in a region outside the plurality of unit structures 5. The semiconductor device according to claim 1, further comprising: a match line driver that precharges a signal line and detects a voltage after precharge; and a data bus driver that drives the third signal line.   The third gate electrode extends on a straight line, and has an intrinsic gate electrode portion formed on the second active region via a gate insulating film and an expanded width formed on the isolation insulating region. The first active region extends in the same line as the third gate electrode in the vicinity of the contact portion, and the second conductive connecting member is disposed on the contact portion. The semiconductor device of any one of Claims 1-5 which contacts.   Two first sets of the word lines, the bit lines, and the first, second, and third signal lines are arranged in parallel to each other as a whole, and at least two second sets of the remaining three are set as a whole. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged in parallel with each other and intersecting the first set. A semiconductor device having a semiconductor substrate and a plurality of unit structures formed on the semiconductor substrate, forming a memory element and a logic element, and having the same or symmetrical planar shape, wherein each unit structure is the semiconductor An isolation insulating region formed on a surface of the substrate and defining first and second active regions;
A first gate electrode formed across the first active region, and a pair of first source / drain formed on both sides of the first gate electrode in the first active region A transfer transistor having a region;
A word line connected to the first gate electrode;
Second and third gate electrodes formed across the second active region; and a connection node formed between the second and third gate electrodes in the second active region; A series-connected transistor including a pair of second source / drain regions formed outside the second and third gate electrodes;
A first signal line connected to one of the pair of second source / drain regions and formed of a first metal wiring;
A second signal line connected to the other of the pair of second source / drain regions and formed of a first metal wiring in the same layer as the first signal line;
A third signal line connected to the second gate electrode and formed of a second metal wiring different from the first metal wiring;
Connected to one of the pair of first source / drain regions, formed of a third wiring below the second metal wiring, and disposed so as to overlap the third signal line in plan view The bit line being
A storage electrode formed in a region including the other of the pair of first source / drain regions and at least part of the third gate electrode;
A capacitor dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the capacitor dielectric film;
A first conductive connection member formed below the storage electrode and connecting the storage electrode and the other of the pair of first source / drain regions;
A second conductive connection member formed below the storage electrode and connecting the storage electrode and the third gate electrode;
A semiconductor device. A semiconductor device having a semiconductor substrate and a plurality of unit structures formed on the semiconductor substrate, forming a memory element and a logic element, and having the same or symmetrical planar shape, wherein each unit structure is the semiconductor An isolation insulating region formed on a surface of the substrate and defining first and second active regions;
A first gate electrode formed across the first active region, and a pair of first source / drain formed on both sides of the first gate electrode in the first active region A transfer transistor having a region;
A word line connected to the first gate electrode;
A bit line connected to one of the pair of first source / drain regions;
Second and third gate electrodes formed across the second active region;
A connection node formed between the second and third gate electrodes in the second active region, and a pair of second source / sources formed outside the second and third gate electrodes A series-connected transistor including a drain region;
A match line connected to one of the pair of second source / drain regions and formed of a first metal wiring;
A ground line connected to the other of the pair of second source / drain regions and formed of a first metal wiring in the same layer as the match line;
A data bus line connected to the second gate electrode and formed of a second metal wiring different from the first metal wiring;
A storage electrode formed in a region including the other of the pair of first source / drain regions and at least part of the third gate electrode;
A capacitor dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the capacitor dielectric film;
A first conductive connection member formed below the storage electrode and connecting the storage electrode and the other of the pair of first source / drain regions;
A second conductive connection member formed below the storage electrode and connecting the storage electrode and the third gate electrode;
A semiconductor device. A semiconductor device formed on a semiconductor substrate and having a plurality of identical or symmetric unit structures including a memory element and a logic element, each unit structure comprising:
A DRAM cell formed in a first active region and having a first transistor and a capacitor with a storage electrode;
A logic element having second and third series-connected transistors formed in the second active region and having second and third gate electrodes and silicided source / drain electrodes;
A conductive connecting member formed below the storage electrode of the DRAM capacitor and connecting the storage electrode and the third gate electrode;
And the third gate electrode is silicided in a region other than a partial region, and the conductive connection member connects the storage electrode and the partial region of the third gate electrode.

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