JP2007241799A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide precise data transfer processing to a memory device regardless of whether memory devices are set to a normal operation mode or a power saving mode. <P>SOLUTION: The memory devices MD0 to MD3 are provided with respective termination resistors r0 to r3. A memory controller 1 shifts each memory device individually from the normal operation mode to the power saving mode. The memory controller 1 generates a control signal for turning on/off each termination resistor individually, and outputs it to a memory device to be controlled. According to whether the memory device is shifted to the power saving mode, the controller 1 changes output timing of the control signal to the memory device to keep the memory device to be on in a period of transferring data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory controller that controls a DDR2-SDRAM.

  In recent years, a DDR (Double Data Rate) -SDRAM (Synchronous DRAM) capable of reading and writing data both at the rising edge and the falling edge of a clock signal has been widely used as a storage device such as a personal computer or an embedded device. . In a memory system using a DDR-SDRAM, a memory module including a plurality of memory devices can be inserted into each of a plurality of slots, and the memory capacity can be freely increased or decreased. In the memory system using the DDR-SDRAM, each memory device is individually set to the power saving mode by monitoring the transaction for each memory device and setting the memory device that has not been accessed for a certain period of time to the power saving mode. Detailed power management is performed.

  In recent years, DDR2-SDRAM, which can be accessed at a higher speed than DDR-SDRAM, has become widespread. Similar to the DDR-SDRAM, this DDR2-SDRAM is set to the power saving mode for each memory device, and fine power management is possible. Here, in the DDR2-SDRAM, a termination resistor for impedance matching at the termination of a transmission line such as a data bus is built in each memory device.

  In the DDR2-SDRAM memory system, each memory device is provided with a dedicated control terminal called ODT, and a control signal for turning on or off the memory device is input to the control terminal, and the memory device is turned on or off. The When the memory device is turned off, the impedance value is set to infinity, and when the memory device is turned on, the impedance is set to a predetermined value such as 75Ω.

  In the DDR2-SDRAM, when data transfer processing for writing or reading data to a certain memory device connected to the slot 1 is executed, it is necessary to turn on the termination resistance of any memory device connected to the slot 2. is there.

Patent Document 1 discloses a clock frequency supplied to a memory after issuing a self-refresh command to a memory that has been idle for a predetermined time for the purpose of reducing the power consumption of the memory. A reduced memory drive system is disclosed.
JP 2005-115906 A

  However, in the DDR2-SDRAM, the delay time from when the memory device receives the on / off control signal to when it is actually turned on or off is set when the memory device is set in the normal operation mode and in the power saving mode. The specification is different from when In the conventional memory controller, the output timing of the control signal has not been changed depending on whether the normal operation mode or the power saving mode is set. For this reason, there is a difference between the timing at which the termination resistor is turned on and the timing at which the memory device performs data transfer processing. There is a problem that the data transfer timing does not match the on / off timing of the termination resistor, and accurate data transfer processing cannot be realized for the memory device. It was.

  In addition, the memory drive system disclosed in Patent Document 1 does not take into account any adjustment regarding the timing of turning on or off the termination resistor in accordance with the normal operation mode and the power saving mode, and there is a problem that the above-described deviation occurs. .

  An object of the present invention is to provide a memory controller that can realize accurate data transfer processing for a memory device regardless of whether the memory device is set in a normal operation mode or a power saving mode. .

  A memory controller according to the present invention is a memory controller that controls a plurality of memory devices composed of DDR2-SDRAMs, each of the plurality of memory devices having a terminating resistor, and each memory device is changed from a normal operation mode to a power saving mode. Power saving control means for individually transferring, data transfer means for executing data transfer processing for reading data from or writing data to the memory device, and control signals for individually turning on / off each termination resistor And a termination resistance control means for outputting to the memory device to be controlled, the termination resistance control means depending on whether or not the memory device is shifted to the power saving mode by the power saving control means. Changing the output timing of the control signal to the memory device Ri, during the data transfer time by the data transfer unit, and wherein the turning on the memory device.

  According to this configuration, the termination resistance control unit is set in the power saving mode or the normal operation mode so that the termination resistor to be controlled is turned on during the time when the data transfer unit performs data transfer to a memory device. The output timing of the control signal is changed accordingly. That is, the difference between the delay time until the memory device actually turns on for the control signal in the power saving mode and the delay time until the memory device actually turns on for the control signal in the normal operation mode. In addition, since the output timing of the control signal is adjusted so that the termination resistor is turned on during the data transfer time, the termination resistor is prevented from being turned off during the data transfer time, thereby realizing accurate data transfer. be able to.

  Further, in the above configuration, in a state in which data transfer processing is being executed for a certain memory device by the data transfer unit, the power saving control unit shifts the memory device to the power saving mode by the power saving control unit. When the request is issued, the power saving transition request is suspended until the data transfer process for the memory device is completed, and after the data transfer process for the memory device is completed, the memory device is shifted to the power saving mode. It is preferable to further include a power transfer holding means.

  According to this configuration, even if a power saving transition request for shifting the memory device to the power saving mode is issued during execution of data transfer processing for a certain memory device, the memory device immediately enters the power saving mode. After the data transfer process is completed without being shifted, the power saving mode is entered. Therefore, the termination resistor is prevented from being turned off during the data transfer process, and accurate data transfer can be realized.

  In the above configuration, when the transaction for the memory device occurs while the power saving transition holding unit holds the power saving transition request for a certain memory device, the power saving transition holding unit may discard the power saving transition request. preferable.

  According to this configuration, when a transaction occurs while the power saving transition request is suspended, the power saving transition request is discarded and the transaction is executed, so that the access time to the memory device can be increased. Can do.

  According to the memory controller of the present invention, it is possible to prevent the termination resistor from being turned off during the data transfer time regardless of whether the memory device is set in the normal operation mode or the power saving mode. Can be realized.

  Hereinafter, a memory controller according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a memory system to which a memory controller 1 according to the present embodiment is applied. The memory system is connected to a CPU 100, a ROM 200, and the like included in a device such as an image forming apparatus to which the memory system is applied via a bus line. The memory system shown in FIG. 1 includes a memory controller 1, an SDRAM I / F 2, and four memory devices MD0 to MD3. The memory devices MD0 to MD3 are constituted by memory chips of DDR2-SDRAM, and various data are written and read out through the SDRAM I / F 2 under the control of the memory controller 1. The memory devices MD0 and D1 are mounted on the memory module M1 made of DIMM, and the memory devices MD2 and D3 are mounted on the memory module M2 made of DIMM.

  The memory module M1 is connected to one DIMM slot (hereinafter referred to as “slot 1”) of two DIMM (Dual Inline Memory Module) slots provided on a circuit board (not shown). It is connected to the other DIMM slot (hereinafter referred to as “slot 2”).

  Note that the number of memory modules is not limited to two, and one or three or more memory modules may be employed. Further, the number of memory devices included in one memory module is not limited to two, and may be three or more.

  The SDRAM I / F 2 buffers the data to be written under the control of the memory controller 1, writes the data to the memory devices MD0 to MD3, and reads and buffers the data to be read from the memory devices MD0 to MD3. Output to the memory controller 1.

  Each of the memory devices MD0 to MD3 includes termination resistors r0 to r3. Termination resistors r0 to r3 are provided at the terminations of transmission lines such as data buses in the memory devices MD0 to MD3 to achieve impedance matching.

  FIG. 2 is a block diagram showing a detailed configuration of the memory controller 1 shown in FIG. The memory controller 1 includes a device manager 11, a command dispatcher 12, a command generation unit 13, a queue buffer 14, a refresh unit 15, an arbiter 16, a strobe generation unit 17, a host I / F 18, an OPBI / F 19, and a clock generation unit 20. ing.

  The device manager 11 outputs to the arbiter 16 a power saving transition request command for setting any one of the memory devices MD0 to MD3 to the power saving mode. The device manager 11 accepts a state transition command from the command dispatcher 12 and sends various requests for transitioning the states of the memory devices MD0 to MD3 and the memory banks constituting the memory devices MD0 to MD3 to the command dispatcher. 12 is output.

  The command dispatcher 12 receives various requests output from the device manager 11, dispatches these requests, and outputs a command issue request for generating a command for the dispatched request to the command generation unit 13. Further, the command dispatcher 12 reads the ROW command request, the ROW address designation request, the COL command request, and the COL address designation request output from the queue buffer 14, dispatches these requests, and outputs them to the command generation unit 13.

  The command generation unit 13 receives a command issuance request, a ROW command request, a COL command request, a ROW address designation request, a COL address designation request, and the like output from the command dispatcher 12, and generates a control command for controlling the memory device. And output to the SDRAM I / F 2 or the strobe generation unit 17. The command generation unit 13 outputs a control command to the SDRAM I / F 2 and simultaneously outputs a data transfer trigger to the strobe generation unit 17.

  In addition, the command generation unit 13 transmits and receives each signal of MCB_b, Ras_b, CAS_b, MWE_b, BA, MA, and CKE to and from the SDRAM I / F2. The MCB_b signal is 4-bit data, and is transmitted / received by four parallel lines connected to the SDRAM I / F2. The BA signal is 2-bit data and is transmitted / received through two parallel lines connected to the SDRAM I / F 2. The MA signal is 2-bit data and is transmitted / received by two parallel lines connected to the SDRAM I / F 2. The CKE signal is a signal for selecting any one of the memory devices MD0 to MD3, and is transmitted and received by four lines connected in parallel to each of the memory devices MD0 to MD3.

  The refresh unit 15 outputs a refresh request to the arbiter 16. The host I / F 18 receives a memory access request from the CPU 100 provided in the image forming apparatus to which the present memory system is applied, and outputs it to the arbiter 16. The host I / F 18 outputs the data read from the memory devices MD0 to MD3 by the strobe generation unit 17 to the CPU 100. Further, the host I / F 18 receives data to be written to the memory devices MD0 to MD3 from the ROM 200 or the like and outputs the data to the strobe generation unit 17.

  The OPBI / F receives a direct command request from the CPU 100 or the like and outputs it to the arbiter 16.

  The arbiter 16 receives a refresh request from the refresh unit 15, a memory access request from the host I / F 18, and a direct command request from the OPBI / F 18, and registers these requests as transactions in the queue buffer 14. The queue buffer 14 stores transactions generated by the arbiter 16.

  In accordance with the data transfer trigger from the command generation unit 13, the strobe generation unit 17 writes data to a memory device that is a data writing target and reads data from the memory device that is a data reading target. The strobe generation unit 17 transmits and receives each signal of DQOUT, DQIN, DQSOUT, DQSIN, DM, DQDRIVE_H_b, DQDRIVE_L_b, ODT, and ODTCON to and from SDRAMIF2. The DQOUT signal indicates 128-bit data to be written, and is transmitted / received through 128 parallel lines connected to the SDRAM I / F2.

  The DQIN signal indicates 128-bit data to be read, and is transmitted / received through 128 parallel lines connected to the SDRAM I / F2.

  The ODT signal is a signal that designates one of the termination resistors r0 to r3 and turns on or off the designated termination resistor. The ODTCON signal is a signal for turning on or off the termination resistor rs included in the SDRAM I / F 2.

  In the present embodiment, the device manager 11 and the command dispatcher 12 correspond to an example of a power saving control unit, the strobe generation unit 17 corresponds to an example of a data transfer unit, and the command generation unit 13 and the strobe generation unit 17 The command generation unit 13 corresponds to an example of a termination resistance control unit, and the command generation unit 13 corresponds to an example of a power saving transition holding unit.

  Next, the operation when the memory controller 1 sets the memory device to the power saving mode will be briefly described. The device manager 11 monitors the state of the memory devices MD0 to MD3, and sets the memory device that has passed a predetermined time from the last access time to the power saving mode. The power saving transition request generated by the device manager 11 is output to the arbiter 16, and the arbiter 16 registers the output power saving transition request as a transaction in the queue buffer 14. The command dispatcher 12 reads the power saving transition request from the queue buffer 14 and outputs it to the command generation unit 13. The command dispatcher 12 reads the power saving transition request from the queue buffer 14 and outputs a command issuance request for issuing the power saving transition request command to the command generation unit 13.

  The command generation unit 13 that has received the command issue request outputs a signal for setting the device designated by the power saving transition request among the memory devices MD0 to MD3 to the SDRAM I / F2. The command generation unit 13 specifies the memory device for setting the power saving mode by the CKE signal, and also specifies by the CKE signal using the four signals of the MCS_b signal, the RAS_b signal, the CAS_b signal, and the MWE_b signal. Set the selected memory device to the power saving mode.

  FIG. 3 shows a timing chart when data is read from the memory device MD0 by turning on the termination resistor r1 of the memory device MD2 after turning on the termination resistor r0 of the memory device MD0 and reading data from the memory device MD2. Yes. In FIG. 3, “CK” indicates a clock generated by the clock generation unit 20. “CdCommand” indicates a command issuance request output by the command dispatcher 12, and includes “cdDevice” and “cdODTtarget”. “CdDevice” indicates a memory device to be read or written. “CdODTtarget” indicates a termination resistor that is turned on or off. “ODT_trigger_dev” indicates a data transfer trigger output by the command generation unit 13 and includes “ODT target”. “ODT target” indicates a termination resistor that is turned on or off. “ODT_trigger_con” indicates a signal for determining the rising timing of “ODTCON”, which is a signal for turning on or off the termination resistor rs included in the SDRAM I / F 2. “ODTCON” indicates a signal for turning on or off the termination resistor rs.

  “CommandRank” indicates the priority of command issue requests. “ODT state s” indicates a state in which the termination resistor rs is turned on or off, and a square portion indicates an on state. “ODT state 0” indicates a state in which the termination resistor r2 is turned on or off, and a square portion indicates an on state. “ODT state 0” indicates a state in which the termination resistor r0 is turned on or off, and a square portion indicates an on state. “ODT state 2” indicates a state in which the termination resistor r2 is turned on or off, and a square portion indicates an on state. “Rank0” indicates the memory device MD0, and “Rank2” indicates the memory device MD2.

  First, at time T0, the command dispatcher 12 outputs a command issue request C1 of “ACT, r0” to the command generation unit 13 in order to set the memory device MD0 to the normal operation mode. Thereby, the memory device MD0 is set to the normal operation mode. At time T2, the command dispatcher 12 outputs a command issue request C2 of “ACT, r2” to the command generation unit 13 in order to set the memory device MD2 to the normal operation mode. Thereby, D2 is set to the normal operation mode.

  At time T4, the command dispatcher 12 outputs a command issue request C3 of “READA, r0, r2” to the command generation unit 13 in order to turn on the termination resistor r0 and read data from the memory device MD2.

  At time T6, the command generation unit 13 outputs a data transfer trigger O1 of “r2” to the strobe generation unit 17 to turn on the termination resistor r2 in accordance with the command issuance request C3, and the strobe generation unit 17 To turn on, ODT2 is set to TI1 high level for a predetermined time. Here, the time TI1 is a predetermined time for turning on the terminal resistance of the memory device set in the normal operation mode, and corresponds to the length of three cycles of the clock CK.

  As a result, the terminating resistor r2 is turned on when a certain delay time tAOND has elapsed from time T8, which is the rising time of the clock CK next to time T7 when ODT2 becomes high level, and ODT2 becomes low level. It turns off when a certain delay time tAOFD has elapsed from time T11, which is the rising time of the next clock CK after time T10. Here, the time when the termination resistor r0 is turned on is defined as time TI2. The command generator 13 reads out the DQ signal including the data Q0 to Q3 from the memory device MD0 during the time when the termination resistor r2 is on.

  At time T7, the command dispatcher 12 turns on the termination resistor r0 and outputs a command issue request C4 of “READA, r2, r0” to the command generation unit 13 in order to read data from the memory device MD0.

  At time T10, the command generation unit 13 outputs a data transfer trigger O2 of “r0” to the strobe generation unit 17 to turn on the termination resistor r0 in accordance with the command issue request C4, and the strobe generation unit 17 outputs the termination resistance r0. In order to turn on, ODT0 is set to high level for a time TI1. Similarly to the termination resistor r2, the termination resistor r0 is turned on for a time TI2 according to ODT0. The command generator 13 reads the DQ signal including the data Q0 to Q3 from the memory device MD2 during the time when the termination resistor r0 is on.

  It should be noted that the hatched region during the time when the termination resistor r0 and the termination resistor r2 are on indicates that both the termination resistor r0 and the termination resistor r2 are both on and are in an overlapping state. Yes. In this overlapping state, data Q0 to Q3 are not read.

  As described above, when the strobe generation unit 17 receives the data transfer trigger O1, the memory device MD0 is set at the time T10 when the delay time tAOND, which is the time during which the termination resistor r2 is turned on, has elapsed after setting ODT2 to the high level. Starts reading data Q0 to Q3. Then, the reading of the data Q0 to Q3 is completed after the delay time tAOFD, which is the time when the termination resistor r0 is turned off, after the ODT2 is set to the low level. For this reason, the timing at which the memory device MD2 is turned on coincides with the timing at which the data D0 to D3 is read, and accurate data transfer can be realized.

  FIG. 4 shows a timing chart when the termination resistance r0 of the memory device MD0 is turned on and data is written to the memory device MD2, and then the termination resistance r2 of the memory device MD2 is turned on and data is written to the memory device MD0. Yes.

  At time T0, the command dispatcher 12 outputs a command issue request C1 of “ACT, r0” to the command generation unit 13 in order to set the memory device MD0 to the normal operation mode. Thereby, the memory device MD0 is set to the normal operation mode. At time T2, the command dispatcher 12 outputs a command issue request C2 of “ACT, r2” to the command generation unit 13 in order to set the memory device MD2 to the normal operation mode. Thereby, D2 is set to the normal operation mode.

  At time T4, the command dispatcher 12 outputs a command issue request C3 of “WRITE, r0, r2” to the command generation unit 13 in order to turn on the termination resistor r0 and write data to the memory device MD2.

  At time T5, the command generation unit 13 outputs a data transfer trigger O1 of “r2” to the strobe generation unit 17 to turn on the termination resistor r2 in accordance with the command issuance request C3, and the strobe generation unit 17 In order to turn on, the ODT2 signal is set to the TI1 high level for a predetermined time. The strobe generator 17 outputs a DQ signal including data D0 to D3 to the memory device MD0 and writes the data D0 to D3 during the time when the termination resistor r2 is on.

  At time T7, the command dispatcher 12 outputs a command issue request C4 of “WRITE, r2, r0” to the command generator 13 in order to turn on the termination resistor r0 and write data to the memory device MD0.

  At time T10, the command generation unit 13 outputs a data transfer trigger O2 of “r0” to the strobe generation unit 17 to turn on the termination resistor r0 in accordance with the command issue request C4, and the strobe generation unit 17 outputs the termination resistance r0. In order to turn on, ODT0 is set to high level for a time TI1. The strobe generator 17 outputs a DQ signal including data D0 to D3 to the memory device MD2 and writes the data D0 to D3 during the time when the termination resistor r0 is on.

  It should be noted that the hatched region during the time when the termination resistor r0 and the termination resistor r2 are on indicates that both the termination resistor r0 and the termination resistor r2 are both on and are in an overlapping state. Yes.

  As described above, when the strobe generation unit 17 receives the data transfer trigger O1, the memory device MD0 is set at the time T9 when the delay time tAOND, which is the time for which the termination resistor r2 is turned on, has elapsed after the ODT2 is set to the high level. Starts writing data D0 to D3. Then, the writing of the data D0 to D3 is completed after the delay time tAOFD, which is the time when the termination resistor r0 is turned off, after the ODT2 is set to the low level. For this reason, the timing at which the memory device MD2 is turned on coincides with the timing at which the data D0 to D3 are written, and accurate data transfer can be realized.

  FIG. 5 shows a timing chart when data is written to the memory device MD0 by turning on the termination resistor r2 of the memory device MD2 after turning on the termination resistor r0 of the memory device MD0 and reading data from the memory device MD2. Yes.

  At time T0, the command dispatcher 12 outputs a command issue request C1 of “ACT, r0” to the command generation unit 13 in order to set the memory device MD0 to the normal operation mode. Thereby, the memory device MD0 is set to the normal operation mode. At time T2, the command dispatcher 12 outputs a command issue request C2 of “ACT, r2” to the command generation unit 13 in order to set the memory device MD2 to the normal operation mode. Thereby, the memory device MD2 is set to the normal operation mode.

  At time T4, the command dispatcher 12 outputs a command issue request C3 of “READA, r0, r2” to the command generation unit 13 in order to turn on the termination resistor r0 and read data from the memory device MD2.

  At time T6, the command generation unit 13 outputs a data transfer trigger O1 of “r2” to the strobe generation unit 17 to turn on the termination resistor r2 in accordance with the command issuance request C3, and the strobe generation unit 17 To turn on, ODT2 is set to TI1 high level for a predetermined time. The strobe generation unit 17 reads out a DQ signal including data Q0 to Q3 from the memory device MD0 during the time when the termination resistor r2 is on.

  At time T8, the command dispatcher 12 outputs a command issue request C4 of “WRITE, r2, r0” to the command generation unit 13 to turn on the termination resistor r0 and write data to the memory device MD0.

  At time T9, the command generation unit 13 outputs a data transfer trigger O2 of “r0” to the strobe generation unit 17 to turn on the termination resistor r0 in accordance with the command issue request C4, and the strobe generation unit 17 outputs the termination resistance r0. In order to turn on, ODT0 is set to high level for a time TI1. The strobe generator 17 outputs a DQ signal including data D0 to D3 to the memory device MD2 and writes the data D0 to D3 during the time when the termination resistor r0 is on.

  As described above, when the strobe generation unit 17 receives the data transfer trigger O1, the memory device MD0 is set at the time T10 when the delay time tAOND, which is the time during which the termination resistor r2 is turned on, has elapsed after setting ODT2 to the high level. Starts reading data Q0 to Q3. Then, the reading of the data Q0 to Q3 is completed until a delay time tAOFD that is a time from when the ODT2 is set to the low level to when the termination resistor r0 is turned off elapses. Therefore, the timing at which the memory device MD2 is turned on coincides with the read timing of the data Q0 to Q3, and accurate data transfer can be realized.

  FIG. 6 shows a timing chart when data is written to the memory device MD2 by turning on the termination resistor r0 of the memory device MD0 and then data is read from the memory device MD0 by turning on the termination resistor r2 of the memory device MD2. Yes.

  First, at time T0, the command dispatcher 12 outputs a command issue request C1 of “ACT, r0” to the command generation unit 13 in order to set the memory device MD0 to the normal operation mode. Thereby, the memory device MD0 is set to the normal operation mode. At time T2, the command dispatcher 12 outputs a command issue request C2 of “ACT, r2” to the command generation unit 13 in order to set the memory device MD2 to the normal operation mode. Thereby, D2 is set to the normal operation mode.

  At time T4, the command dispatcher 12 outputs a command issue request C3 of “WRITE, r0, r2” to the command generation unit 13 in order to turn on the termination resistor r0 and write data to the memory device MD2.

  At time T6, the command generation unit 13 outputs a data transfer trigger O1 of “r2” to the strobe generation unit 17 to turn on the termination resistor r2 in accordance with the command issuance request C3, and the strobe generation unit 17 To turn on, ODT2 is set to TI1 high level for a predetermined time. The strobe generator 17 outputs a DQ signal including data D0 to D3 to the memory device MD0 and writes the data D0 to D3 at the time TI2 when the termination resistor r2 is on.

  At time T8, the command dispatcher 12 outputs a command issue request C4 of “READA, r2, r0” to the command generation unit 13 in order to turn on the termination resistor r0 and read data from the memory device MD0.

  At time T9, the command generation unit 13 outputs a data transfer trigger O2 of “r0” to the strobe generation unit 17 to turn on the termination resistor r0 in accordance with the command issue request C4, and the strobe generation unit 17 outputs the termination resistance r0. In order to turn on, ODT0 is set to high level for a time TI1. The strobe generation unit 17 reads a DQ signal including data Q0 to Q3 from the memory device MD2 at the time TI2 when the termination resistor r0 is on.

  As described above, when the strobe generation unit 17 receives the data transfer trigger O1, the memory device MD0 is set at the time T9 when the delay time tAOND, which is the time for which the termination resistor r2 is turned on, has elapsed after the ODT2 is set to the high level. Starts writing data D0 to D3. Then, the writing of the data D0 to D3 is completed after the delay time tAOFD, which is the time when the termination resistor r0 is turned off, after the ODT2 is set to the low level. For this reason, the timing at which the memory device MD2 is turned on coincides with the timing at which the data D0 to D3 are written, and accurate data transfer can be realized.

  FIG. 7 shows a timing chart when data is read from the memory device MD2 by turning on the termination resistor r0 of the memory device MD0 set in the power saving mode. In this timing chart, it is assumed that the memory device MD0 is set to the power saving mode before the time T0.

  First, at time T0, the command dispatcher 12 outputs a command issue request C1 of “ACT, r2” to the command generation unit 13 in order to set the memory device MD2 to the normal operation mode. Thereby, the memory device MD2 is set to the normal operation mode.

  At time T4, the command dispatcher 12 outputs a command issue request C2 of “READA, r2, r0” to the command generation unit 13 in order to turn on the termination resistor r0 and read data from the memory device MD2.

  At time T7, the command generation unit 13 outputs a data transfer trigger O1 of “r0” to the strobe generation unit 17 to turn on the termination resistance r0 in accordance with the command issuance request C2, and the strobe generation unit 17 outputs the termination resistance r0. In order to turn on, ODT0 is set to TI3 high level for a predetermined time. The strobe generation unit 17 reads a DQ signal including data Q0 to Q3 from the memory device MD0 during the time (TI1 + tOAFD) when the termination resistor r2 is on.

  Here, the time TI3 is a time obtained by adding a predetermined time (TI1 + tAOFD) to a predetermined delay time tAONPD (max) from the rising time of ODT0. Note that TI1 indicates the time during which the memory device MD0 is turned on when the memory device MD0 is set in the normal operation mode, and has the same value as the time TI1 illustrated in FIGS. In addition, tAOFD is given in consideration that the timing of actually turning on or off with respect to ODT0 in the memory device MD0 set in the power saving mode is delayed compared to the case where it is set in the normal operation mode. Margin.

  As a result, the memory device MD0 is turned on at any timing from when the ODT0 rises until the delay time tAONPD (max) elapses, and after the ODT0 becomes low level, the predetermined delay time tAOFPD (max) Turns off at any timing until the elapses. Therefore, the time during which the memory device MD0 is on may be shorter than the time TI4, but is on for at least the time (TI1 + tAOFD). Then, the strobe generation unit 17 reads the DQ signal including the data Q0 to Q3 from the memory device MD2 at time (TI1 + tOAFD).

  As described above, when the memory device MD0 is set in the power saving mode, the timing when the memory device MD0 is actually turned on or off with respect to ODT0 is delayed as compared with the case where the memory device MD0 is set in the normal operation mode. Considering that the delay times tAONPD and tAOFPD are unstable, the high and low timings of ODT0 are determined so that the memory device MD0 is turned on for at least the time (TI1 + tOAFD). The strobe generation unit 17 starts reading data Q0 to Q3 when tAONPD (max), which is a time during which the termination resistor r0 is reliably turned on, has elapsed since the reception of the data transfer trigger O1. The reading of the data Q0 to Q3 is completed before the time T14, which is the shortest time at which r0 is turned off, elapses. Therefore, when the data Q0 to Q3 are read from the memory device MD2, it is always possible to turn on the termination resistor r0, and the data Q0 to Q3 can be accurately read from the memory device MD2.

  FIG. 8 shows a timing chart when data is written to the memory device MD2 by turning on the termination resistor r0 of the memory device MD0 set in the power saving mode. In this timing chart, it is assumed that the memory device MD0 is set to the power saving mode before the time T0.

  First, at time T0, the command dispatcher 12 outputs a command issue request C1 of “ACT, r2” to the command generation unit 13 in order to set the memory device MD2 to the normal operation mode. Thereby, the memory device MD2 is set to the normal operation mode.

  At time T4, the command dispatcher 12 outputs a command issue request C2 of “WRITE, r2, r0” to the command generation unit 13 in order to turn on the termination resistor r0 and write data to the memory device MD2.

  At time T6, the command generation unit 13 outputs a data transfer trigger O1 of “r0” to the strobe generation unit 17 to turn on the termination resistor r0 according to the command issuance request C2, and the strobe generation unit 17 outputs the termination resistor r0. In order to turn on, ODT0 is set to TI3 high level for a predetermined time. The strobe generation unit 17 reads a DQ signal including data D0 to D3 from the memory device MD0 during the time (TI1 + tOAFD) when the termination resistor r2 is on.

  As described above, when the memory device MD0 is set in the power saving mode, the timing when the memory device MD0 is actually turned on or off with respect to ODT0 is delayed as compared with the case where the memory device MD0 is set in the normal operation mode. Considering that the delay times tAONPD and tAOFPD are unstable, the high and low timings of ODT0 are determined so that the memory device MD0 is turned on for at least the time (TI1 + tOAFD). The strobe generator 17 starts writing data D0 to D3 when tAONPD (max), which is the time for which the termination resistor r0 is reliably turned on, has elapsed since the data transfer trigger O1 is received. The writing of the data D0 to D3 is completed before the time T14, which is the shortest time at which r0 is turned off, elapses. Therefore, when the data D0 to D3 are written to the memory device MD2, the termination resistor r0 can be always turned on, and the data D0 to D3 can be accurately written to the memory device MD2.

  FIG. 9 shows that the command dispatcher 12 turns on the termination resistor r0 of the memory device MD0 set in the normal operation mode and outputs a command issuance request for reading data from the memory device MD0, and then saves power to the memory device MD0. It is a timing chart which shows a process when the command issue request | requirement set to a mode generate | occur | produces.

  First, at time T7, the command dispatcher 12 outputs a command issue request C1 of “READA, r2, r0” for turning on the termination resistor r0 of the memory device MD0 and reading data from the memory device MD0 to the command generation unit 13. To do. At time T8, the command dispatcher 12 outputs a command issuance request for setting the memory device MD0 to the power saving mode to the command generation unit 13. At this time, the command generation unit 13 outputs the command issuance request C1, and since this processing has not been completed, the command for setting the memory device MD0 to the power saving mode without setting the memory device MD0 to the power saving mode. Hold the issue request.

  At time T10, the command generation unit 13 outputs a data transfer trigger O1 of “r0” to the strobe generation unit 17 to turn on the termination resistance r0 according to the command issue request C1, and the strobe generation unit 17 outputs the termination resistance r2. In order to turn on, the ODT2 signal is set to TI1 high level for a predetermined time, and the terminating resistor r0 is turned on. The strobe generation unit 17 reads out a DQ signal including data Q0 to Q3 from the memory device MD0 during the time when the termination resistor r2 is on.

  At time T17, the command generation unit 13 sets CKE0 to low level and sets the memory device MD0 to the power saving mode when a predetermined time TI6 has elapsed since ODT0 became low level. Here, as the time TI6, a predetermined value from when the ODT0 becomes the low level to when the termination resistor r0 is actually turned off is adopted. Therefore, the termination resistor r0 is not turned off during reading of the data Q0 to Q3 to the memory device MD2, and the data Q0 to Q3 can be read correctly.

  Here, the command generation unit 13 issues a command issuance request such as writing or reading data to the memory device MD0 during the time when the command issuance request for setting the memory device MD0 to the power saving mode is suspended. If received, that is, if a new transaction occurs during the hold for the memory device that is pending the transition to the power saving mode, the command generating unit 13 sets the pending power saving mode. Command issuance request is discarded.

  As described above, according to the memory controller 1 of the present embodiment, the timing for turning on or off the memory device depending on whether each memory device is set in the power saving mode or the normal operation mode. Therefore, data can be read or written while the termination resistor is on, and the data transfer process can be performed accurately.

1 is a block diagram of a memory system to which a memory controller 1 according to the present embodiment is applied. FIG. 2 is a block diagram showing a detailed configuration of a memory controller 1 shown in FIG. 1. A timing chart is shown when data is read from the memory device MD0 by turning on the termination resistor r1 of the memory device MD2 after turning on the termination resistor r0 of the memory device MD0 and reading data from the memory device MD2. A timing chart is shown when data is written to the memory device MD0 by turning on the termination resistor r2 of the memory device MD2 after turning on the termination resistor r0 of the memory device MD0 and writing data to the memory device MD2. A timing chart is shown when data is written to the memory device MD0 by turning on the termination resistor r2 of the memory device MD2 after turning on the termination resistor r0 of the memory device MD0 and reading data from the memory device MD2. A timing chart is shown when data is written to the memory device MD2 by turning on the termination resistor r0 of the memory device MD0 and then data is read from the memory device MD0 by turning on the termination resistor r2 of the memory device MD2. A timing chart when data is read from the memory device MD2 by turning on the termination resistor r0 of the memory device MD0 set in the power saving mode is shown. 4 shows a timing chart when data is written to the memory device MD2 by turning on the termination resistor r0 of the memory device MD0 set in the power saving mode. After the command dispatcher 12 turns on the termination resistor r0 of the memory device MD0 set in the normal operation mode and outputs a command issue request for reading data from the memory device MD0, the memory device MD0 is set in the power saving mode. It is a timing chart which shows a process when a command issue request generate | occur | produces.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory controller 11 Device manager 12 Command dispatcher 13 Command generation part 14 Queue buffer 15 Refresh part 16 Arbiter 17 Strobe generation part 20 Clock generation part MD0-MD3 Memory device host I / F 18
M1 memory module M2 memory module O1 data transfer trigger O2 data transfer trigger Q0 to Q3 data r0 to r3, rs termination resistance

Claims (3)

A memory controller for controlling a plurality of memory devices composed of DDR2-SDRAMs,
Each of the plurality of memory devices includes a termination resistor;
Power saving control means for individually shifting each memory device from the normal operation mode to the power saving mode;
Data transfer means for executing data transfer processing for reading data from the memory device or writing data to the memory device;
A termination resistance control means for generating a control signal for individually turning on and off each termination resistor and outputting it to a memory device to be controlled;
The termination resistance control means changes the data transfer timing by changing the output timing of the control signal to the memory device according to whether the memory device is shifted to the power saving mode by the power saving control means. A memory controller, wherein the memory device is turned on during a data transfer time by the means.   When a power saving transition request is issued by the power saving control means to shift the memory device to a power saving mode in a state where data transfer processing is being executed for a certain memory device by the data transferring means. And a power saving transition holding means for holding the power saving transition request until the data transfer processing for the memory device is completed, and after the data transfer processing for the memory device is completed, shifting the memory device to a power saving mode. The memory controller according to claim 1, further comprising:   3. The power saving transition holding unit discards the power saving transition request when a transaction for the memory device occurs while holding a power saving transition request for a certain memory device. The memory controller described.

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