JP2007251022A - Semiconductor device and test method thereof - Google Patents

Abstract

A probe test is performed on at least a plurality of semiconductor chips in a lump in a state of a semiconductor wafer on which each semiconductor chip is formed with a test apparatus having a very simple configuration.
Each of the second electrode pads is divided into the number of installed second electrode pads so that the probe is brought into contact with each other accurately and reliably at the time of collective inspection. It is formed in a size that occupies the maximum. That is, if the number of installations is nine, the back surface 1b is divided into nine regions R so that each divided region R occupies as much as possible.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device including a semiconductor chip and a test method thereof.

  Usually, a semiconductor device forms a plurality of semiconductor chips having various semiconductor elements by a technique such as lithography on a semiconductor wafer, cuts and separates individual semiconductor chips from the semiconductor wafer in a cutting process called dicing, It is completed through a wire bonding process, a packaging process for resin-sealing a semiconductor chip, and the like.

  When a semiconductor device is manufactured through the above steps, various tests are performed on the semiconductor chip. Among these tests, the test of examining the application state of the power supply and input / output signals necessary for device operation and the stress test to apply load voltage are provided with the probe (probe electrode) of the test equipment on the surface of the semiconductor chip. It is carried out by contacting a predetermined electrode pad and applying a predetermined current (probe test).

JP 2004-288911 A

In order to achieve simplified inspection and higher efficiency, the needle contact test using the above test equipment can be performed on at least a plurality of semiconductor chips in a state of a semiconductor wafer on which each semiconductor chip is formed. desired.
In order to realize this batch inspection, for example, a special circuit is mounted on the semiconductor chip, and among the many electrode pads provided on the surface of the semiconductor chip, the electrode pads that perform the minimum power supply and input / output are narrowed down and compared. It is conceivable to perform a probe test using only a small number of electrode pads.

  However, recently, in order to meet the demand for miniaturization and high integration of semiconductor elements, it is necessary to form electrode pads provided on a semiconductor chip with an increasingly smaller size, and the interval between adjacent electrode pads must be reduced. I don't get it. Therefore, even if the electrode pad for probe test is narrowed down using a special circuit, the test apparatus does not have such a high accuracy as to accurately perform the collective inspection. Of course, the formation of a large electrode pad for this collective inspection is contrary to the above-mentioned demand for miniaturization and high integration, and cannot be employed.

  In this regard, Patent Document 1 discloses two types of probe electrodes with different arrangement pitches as a test apparatus applied to a burn-in test that is performed in order to remove defects that have not yet appeared in a semiconductor chip. A configuration provided is disclosed. However, there is currently a search for a method for reliably performing a probe test including a simple burn-in test without making such a large apparatus change.

  The present invention has been made in view of the above-described problems, and at least a plurality of semiconductor chips are collectively collected in a state of a semiconductor wafer in which each semiconductor chip is formed accurately and reliably by a test apparatus having a very simple configuration. It is an object of the present invention to provide a semiconductor device that can perform a probe test and realizes simplification, shortening of time, and high efficiency of the inspection, and a test method thereof.

  The semiconductor device of the present invention is a semiconductor device including a semiconductor chip, and the semiconductor chip is provided with a plurality of first electrode pads on the front surface and a plurality of second electrode pads on the back surface. In addition, the second electrode pad is formed to have a size that occupies the maximum area of each region obtained by dividing the back surface into the number of the second electrode pads.

  In the semiconductor device testing method of the present invention, a plurality of first electrode pads are provided on the front surface, and a plurality of second electrode pads are provided on the back surface, and the second electrode pad covers the back surface. With respect to a semiconductor wafer provided with a plurality of semiconductor chips formed to the maximum size to occupy each area divided by the number of installed second electrode pads, in the state of the semiconductor wafer, A test probe is brought into contact with each of the second electrode pads, and the test of each semiconductor chip is performed collectively on the plurality of semiconductor chips.

  According to the present invention, it becomes possible to perform a probe test collectively for at least a plurality of semiconductor chips in a state of a semiconductor wafer on which each semiconductor chip is formed accurately and reliably by a test apparatus having a very simple configuration. Simplification of inspection, shorter time, and higher efficiency can be realized.

-Basic outline of the present invention-
The present inventor is to satisfy both conflicting demands, that is, a demand for miniaturization and high integration of semiconductor elements and a demand for batch inspection of each semiconductor chip in the state of a semiconductor wafer using a probe. Regular electrode pads (first electrode pads) are arranged on the surface of the semiconductor chip at fine and narrow intervals, while being used for a probe test that can supply power and input / output signals to the back surface of the semiconductor chip. The present inventors have conceived a configuration in which an electrode pad (second electrode pad) is provided.

  Here, the second electrode pad occupies as much as possible each region obtained by dividing the back surface of the semiconductor chip into the number of installed second electrode pads in order to bring the probe into contact with each other accurately and reliably at the time of collective inspection. Form in size. That is, if the number of installations is nine, the back surface is divided into nine regions, and the size of each divided region is maximized.

Specifically, the area of the second electrode pad is S _P , and the area occupied by each divided region is S _R.
0.95S _R ≦ S _P <S _R
As the area S _P to meet, arranging a respective second electrode pads.

In the state of the semiconductor wafer in which each semiconductor chip is thus formed, a probe card is installed on the back surface of the semiconductor wafer (the back surface of each semiconductor chip). Here, each probe corresponding to the second electrode pad is disposed on the probe card. Since the second electrode pad is formed as large as possible as described above, the corresponding probe can be easily and surely brought into contact with the second electrode pad, and an accurate simultaneous inspection can be performed. Is realized. Here, if 0.95S _R ≦ S _P , sufficiently reliable contact is possible.

(Specific embodiment to which the present invention is applied)
FIG. 1 is a plan view showing a schematic configuration of each semiconductor chip which is a component of the semiconductor device according to the present embodiment, wherein (a) shows the front surface and (b) shows the back surface.

  The semiconductor chip 1 internally includes a so-called BIST (Built In Self Test) circuit necessary for wafer level inspection and batch inspection. The BIST circuit is an inspection circuit incorporated in advance in a semiconductor element in order to perform inspection efficiently.

  As shown in FIG. 1A, the surface 1a of the semiconductor chip 1 is provided with a plurality of first electrode pads 2 which are regular external connection terminals and are connected to internal wirings.

  On the other hand, as shown in FIG. 1B, the surface 1b of the semiconductor chip 1 has a small number of second electrode pads 3 used for a probe test capable of supplying power and input / output signals, for example, nine here. Is provided.

  Each second electrode pad 3 maximizes each area obtained by dividing the back surface 1b of the semiconductor chip 1 into the number of installed second electrode pads 3 so that the probe is brought into contact with each other accurately and reliably at the time of collective inspection. It is formed in the size to occupy. That is, if the number of installations is nine, the back surface 1b is divided into nine regions R so that each divided region R occupies as much as possible.

Specifically, the area of the second electrode pad 3 is S _P , and the area occupied by each divided region R is S _R.
0.95S _R ≦ S _P <S _R (1)
As the area S _P to meet, arranging a respective second electrode pads 3. In this embodiment, for example, S _P = 0.96S _R. Here, if the area of the second electrode pad 3 is 95% or more of the area of the region R, the probe of the test apparatus is surely brought into contact with the corresponding second electrode pad 3 in the collective inspection described later. Can do.

Here, as shown in FIG. 2, regarding the size of the second electrode pad 3, the distance between the adjacent second electrode pads 3 is the width S of the scribe line when the semiconductor chip 1 is cut out from the semiconductor wafer. It may be formed in a size equivalent to _W , for example, about 100 μm. Of course, the size of the second electrode pad 3 may be determined so as to satisfy both the condition that the separation distance is equal to the width W of the scribe line and the expression (1).

  The second electrode pad 3 may be configured to be used only for the probe test. In the present embodiment, the case where the second electrode pad 3 is used as an external connection terminal to which power and input / output signals are supplied is illustrated.

For example, FIG. 3 schematically shows a semiconductor device in which the semiconductor chip 1 is wire bonded to the stage 11.
Thus, the semiconductor chip 1 is fixed to the stage 11 on the back surface 1b via a sheet (not shown), and each first electrode pad 2 disposed on the front surface 1a is connected to the terminal 12 of the stage 11 and the bonding wire. 13 is electrically connected. Here, the 2nd electrode pad 3 arrange | positioned by the back surface 1b is electrically connected with the predetermined | prescribed terminal 12 through the extraction conductive part formed, for example in the sheet | seat.

Hereinafter, the collective inspection of the semiconductor chip 1 will be described.
4A and 4B are schematic views showing a semiconductor wafer provided with a plurality of the semiconductor chips 1 and a probe card applied to the semiconductor wafer. FIG. 4A is a plan view of the semiconductor wafer, and FIG. 4B is a probe card. (C) is sectional drawing along the broken line II of a probe card.

As shown in FIG. 4A, the semiconductor wafer 10 is in a state in which each semiconductor chip 1 is formed.
As shown in FIG. 4B, the probe card 21 is provided with a probe mechanism 22 corresponding to each semiconductor chip 1. Each probe mechanism 22 is provided with a plurality of probe electrodes 23 so as to correspond to the second electrode pads 3 disposed on the back surface 1 b of each semiconductor chip 1. In FIG. 4B, each probe mechanism 22 constituted by three probe electrodes 23 corresponding to each back surface 1b is illustrated.

  As shown in FIG. 4C, each probe electrode 23 has an extremely fine and minute probe because each second electrode pad 3 on the back surface 1b is formed as large as possible. The contact pin can be made of a so-called pogo pin that is a relatively large and inexpensive contact pin. FIG. 4C shows a pogo pin array in which probe electrodes 23 are arranged. The probe 22, which is a pogo pin, is configured such that the tip 23 a is elastically urged against the second electrode pad 3 by an elastic member 23 b such as a spring when the probe 22 is in contact with the second electrode pad 3. . Thus, by applying pogo pins as the probe electrodes 23, the probe card 21 can be easily provided at a low cost corresponding to the semiconductor wafer 10.

FIG. 5 is a schematic diagram showing a schematic configuration of the test apparatus.
The test apparatus includes a wafer stage 31 on which the semiconductor wafer 10 is placed and fixed with the back surface 1b facing upward, and a probe card 21 corresponding to the semiconductor wafer 10 when configured to be moved up and down by a lifting mechanism (not shown). It is prepared for.

  The test head 32 takes in the power supply for the sample that applies a voltage from the second electrode pad 3 to each semiconductor chip 1 of the semiconductor wafer 10 and the output from the second electrode pad 3 of each semiconductor chip 1 into the measurement unit. A so-called pin electronics (not shown) having an input section is incorporated.

  The probe card 21 is placed on the semiconductor wafer 10 so that the probe electrode 23 of each probe mechanism 22 contacts the second electrode pad 3 on the back surface of the corresponding semiconductor chip 1. In this state, the test head 32 supplies a power supply voltage from each probe electrode 23 to each semiconductor chip 1 via the second electrode pad 3 to transmit and receive input / output signals.

  In the present embodiment, since each second electrode pad 3 is formed as large as possible, the probe electrode 23 can be accurately and easily attached to the second electrode pad 3 corresponding to all the semiconductor chips 1. It can be made to contact. Therefore, by using this test apparatus, a probe test can be collectively performed on each semiconductor chip 1 in the state of the semiconductor wafer 10.

  In this case, instead of collectively performing the probe test on all the semiconductor chips 1 of the semiconductor wafer 10, it is possible to perform the probe test only on a part of the semiconductor chips 1.

  As described above, according to the present embodiment, at least a plurality of semiconductor chips 1 are collectively collected in the state of the semiconductor wafer 10 on which each semiconductor chip 1 is formed accurately and reliably by a test apparatus having a very simple configuration. Thus, a probe test can be performed, and the inspection can be simplified, shortened, and improved in efficiency.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) A semiconductor device including a semiconductor chip,
The semiconductor chip is provided with a plurality of first electrode pads on the front surface and a plurality of second electrode pads on the back surface,
2. The semiconductor device according to claim 1, wherein the second electrode pad is formed to have a size that occupies a maximum of each region obtained by dividing the back surface into the number of the second electrode pads.

(Supplementary Note 2) The area S _P of the second electrode pad is defined as S _R occupying the area occupied by each region.
0.95S _R ≦ S _P <S _R
The semiconductor device according to appendix 1, wherein the semiconductor device has a value satisfying

  (Supplementary note 3) The semiconductor device according to Supplementary note 1 or 2, wherein a distance between the adjacent second electrode pads is equal to a width of a scribe line when the semiconductor chip is cut out from the semiconductor wafer. .

  (Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the second electrode pad is a terminal to which a power supply and an input / output signal can be supplied.

(Supplementary Note 5) A plurality of first electrode pads are provided on the front surface and a plurality of second electrode pads are provided on the back surface, and the second electrode pads are provided on the back surface of the second electrodes. About a semiconductor wafer provided with a plurality of semiconductor chips formed in a size that occupies the maximum area of each area divided into the number of pads installed,
In the state of the semiconductor wafer, a test probe is brought into contact with each second electrode pad of each semiconductor chip, and a test of each semiconductor chip is performed collectively on each of the plurality of semiconductor chips. A test method for a semiconductor device.

  (Additional remark 6) The said test is collectively performed with respect to all said each semiconductor chip provided in the said semiconductor wafer, The test method of the semiconductor device of Additional remark 5 characterized by the above-mentioned.

(Supplementary Note 7) area S _P output said second electrode pads, the area occupied by the respective region as S _R,
0.95S _R ≦ S _P <S _R
The test method for a semiconductor device according to appendix 5 or 6, wherein the value is a value satisfying

  (Supplementary note 8) Any one of Supplementary notes 5 to 7, wherein a distance between adjacent second electrode pads is equal to a width of a scribe line separating adjacent semiconductor chips. Semiconductor device testing method.

  (Supplementary note 9) The method for testing a semiconductor device according to any one of supplementary notes 5 to 8, wherein the second electrode pad is a terminal to which a power supply and an input / output signal can be supplied.

FIG. 4 is a plan view showing a schematic configuration of each semiconductor chip that is a component of the semiconductor device according to the present embodiment. It is a top view which shows each semiconductor chip schematic structure. It is a schematic perspective view which shows the mode of the semiconductor device by which the semiconductor chip was wire-bonded to the stage. It is a mimetic diagram showing a semiconductor wafer provided with a plurality of semiconductor chips, and a probe card applied to this semiconductor wafer. It is a schematic diagram which shows schematic structure of a test apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Front surface 1b Back surface 2 1st electrode pad 3 2nd electrode pad 10 Semiconductor wafer 11 Stage 12 Terminal 13 Bonding wire 21 Probe card 22 Probe mechanism 23 Probe electrode

Claims (5)

A semiconductor device including a semiconductor chip,
The semiconductor chip is provided with a plurality of first electrode pads on the front surface and a plurality of second electrode pads on the back surface,
2. The semiconductor device according to claim 1, wherein the second electrode pad is formed to have a size that occupies a maximum of each region obtained by dividing the back surface into the number of the second electrode pads. Area S _P output said second electrode pads, the area occupied by the respective region as S _R,
0.95S _R ≦ S _P <S _R
The semiconductor device according to claim 1, wherein the semiconductor device has a value satisfying A plurality of first electrode pads are provided on the front surface, and a plurality of second electrode pads are provided on the back surface. The number of the second electrode pads disposed on the back surface of the second electrode pad. About a semiconductor wafer provided with a plurality of semiconductor chips formed to the maximum size to occupy each area divided into
In the state of the semiconductor wafer, a test probe is brought into contact with each second electrode pad of each semiconductor chip, and a test of each semiconductor chip is performed collectively on each of the plurality of semiconductor chips. A test method for a semiconductor device.   4. The method for testing a semiconductor device according to claim 3, wherein the test is performed collectively for all the semiconductor chips provided on the semiconductor wafer. Area S _P output said second electrode pads, the area occupied by the respective region as S _R,
0.95S _R ≦ S _P <S _R
The semiconductor device testing method according to claim 3, wherein the semiconductor device test method satisfies the following condition.

Images