JP2007259025A - DLL circuit - Google Patents

Abstract

[PROBLEMS] To provide a pseudo lock prevention circuit capable of automatically resetting and locking normally even when an abnormal operation such as a source clock stop of a delay locked loop circuit (DLL circuit) or a source clock frequency change during operation is performed. The purpose is to do.
1 is a charge pump circuit, 2 is a phase delay circuit, 3 is a phase comparator, 4 is a phase control circuit, 5 is a reset circuit, 8 is a charge pump voltage comparison circuit, and 9 is a pseudo lock reference voltage generation circuit. is there. Since the required voltage due to the lock frequency is determined by the voltage of the charge pump of 1, the charge pump voltage is monitored by the charge pump voltage comparison circuit of 8, and is generated by the pseudo lock reference voltage generation circuit of 9 for each frequency. The pseudo lock, the source clock stop, and the source clock frequency fluctuation are recognized by comparing with the changing pseudo lock determination voltage level and the source clock stop determination voltage level.
[Selection] Figure 9

Description

  The present invention relates to a clock generation technique in a DLL (Delay Locked Loop) circuit, and more particularly to automatic initialization of an internal circuit state during abnormal operation such as prevention of pseudo lock of the DLL circuit and stoppage of the source clock or frequency fluctuation of the source clock. It relates to effective technology.

  The DLL circuit includes a phase delay circuit, a phase comparator, a charge pump, a loop filter, and the like, and works to delay the clock delay time by one cycle of the external clock regardless of process variations, power supply voltage, temperature, and the like. It is a feedback loop.

  A conventional DLL circuit is shown in FIG.

  In FIG. 1, 1 is a charge pump circuit, 2 is a phase delay circuit, 3 is a phase comparator, 4 is a phase control circuit, and 5 is a reset circuit. A source clock (signal A) input from the outside is delayed by the phase delay circuit 2 to create a signal delayed from the source clock (signal B). The phase of the signal A and the signal B of the previous cycle is compared by the phase comparator 3. When the phase of the signal A is advanced, UP is indicated. When the phase of the signal B is advanced, the signal DOWN (signal C ) Is output. The UP and DOWN signals at this time are when the delay amount of the phase delay circuit 2 becomes small when the charge pump voltage of 1 is high, and when the charge pump voltage is low, the delay amount of the phase delay circuit 2 When designed to be small, the polarities of UP and DOWN are reversed. When the UP signal is output from the phase comparator 3, the current from the constant current source is supplied and the phase information is accumulated as a voltage (signal D) while the UP signal is output to the charge pump circuit 1. When the DOWN signal is output from the phase comparator 3, current is drawn out by the constant current source while the DOWN signal is output from the charge pump circuit 1. The value of the voltage (signal D) of the charge pump circuit 1 is input to the phase control circuit 4 and the delay amount of the delay circuit 2 is controlled. When the phases of the signal A and the signal B are aligned, the UP and DOWN signals are not output, and the charging / discharging of the signal D is stopped. A state in which the charge / discharge of the signal D is stopped is called a DLL locked state.

  When the circuit is set to the initial state, the reset circuit 5 is controlled by inputting reset control (signal E) from the outside, and forced initialization is performed.

For example, Patent Document 1 is known as prior art document information relating to the invention of this application.
JP 2005-159822 A

  The DLL circuit is a circuit that locks the phase of an input signal of the source clock from the outside and a clock delayed by one period to obtain a signal having a necessary phase. FIG. 2 shows an example of the delay circuit, and FIG. 3 shows a state in which the phase of the input signal of the source clock and the clock of the N-stage output clock that is the final stage of the delay element are locked. As shown in the figure, each delay element outputs a delay from the source clock every time the period of the source clock input from the outside is divided by the number of delay elements. When the clock delayed by the phase delay circuit is largely delayed with respect to the source clock, as shown in FIG. 4, the phase that should originally be locked with the phase one cycle before is locked with the source clock two cycles before. Such a pseudo lock occurs. Furthermore, when the delay is greatly delayed by the delay circuit, a pseudo lock that causes a lock with the phase three cycles before and four cycles before is also generated.

  Also, when the source clock is stopped, as shown in FIG. 5, there is no source clock to be compared with the final stage output of the delay circuit after the stop, so the output signal from the phase comparator is always the phase A signal for delaying is output. For this reason, when the source clock is stopped, the DLL is unlocked and the phase is greatly delayed. For this reason, even when the clock is restarted again, the phase is not locked because it starts from the pseudo-lock state. Also, as shown in FIG. 6, when the delay means has a circuit that controls the amount of current constituting the delay circuit and changes the delay amount, the current is withered if the phase is set to be greatly delayed. Even when the input of the source clock is inputted, the clock is not propagated by the delay circuit, and there is a problem that the clock is not output from the final stage of the delay circuit.

  Further, in the case of a DLL circuit designed to be driven in a certain frequency range, there is a possibility that the frequency of the source clock changes during the operation of the DLL circuit. When the frequency of the source clock is changed, it is possible to lock to the frequency after the change when the frequency is slow. However, when the frequency is doubled or more, a pseudo lock is generated.

  Conventional means 2 in FIG. 7 shows a means for solving the pseudo lock.

  In FIG. 7, 1 is a charge pump circuit, 2 is a phase delay circuit, 3 is a phase comparator, 4 is a phase control circuit, 5 is a reset circuit, 6 is a delay detection circuit, and 7 is a false lock prevention circuit. The state of the signal output from each delay element of the two phase delay circuits differs between when the pseudo lock occurs and when the normal lock occurs. It is detected by using the delay detection circuit 6 that the state of the signal output from each delay element is a pseudo lock pattern, and it is determined whether the signal is in a normal lock state or a pseudo lock state. The result is input to the pseudo lock prevention circuit 7 and when a pseudo lock occurs, the UP and DOWN signals of the phase comparator 3 are controlled to control the charge pump voltage 1 and to lock normally. .

  However, the above-described conventional example 2 for preventing pseudo-locking also has four problems.

  First, when the source clock stops, there is no clock input to the third phase comparator, so that it is always out of the normal lock. At this time, since the state of the signal output from each delay element is different from the pattern of the pseudo lock signal that should be determined by the delay detection circuit 6, it is impossible to detect the pseudo lock. is there. Second, even when the frequency of the source clock changes, the state of the signal output from each delay element is different from the pseudo-lock signal pattern to be determined by the delay detection circuit 6. Therefore, it is impossible to detect that it is a pseudo lock. Third, during these abnormal operations, it is necessary to set the internal state to the initial state by giving an external reset signal. Further, since the configuration of the sixth delay detection circuit detects the pattern of each delay element output, the number of detection circuits is required as many as the number of delay elements. When the number of delay elements constituting the circuit is increased, the circuit scale of the delay detection circuit 6 increases accordingly.

  Therefore, the present invention includes a source clock stop and an automatic reset mechanism when the frequency of the source clock changes. An object of the present invention is to realize a pseudo lock prevention circuit of a DLL circuit with a small-scale circuit.

  To achieve this object, the present invention uniquely determines the lock frequency and the charge pump voltage, as shown in FIG. A method for confirming whether the lock is used is used. Pseudo-lock occurs when the internal delay clock is delayed from the source clock by two cycles or more. Therefore, the pseudo-lock determination reference voltage level is locked rather than the charge pump voltage that locks at half the frequency to be locked. What is necessary is just to set to the charge pump voltage side at the time of the frequency which should be. If you want to configure a DLL circuit that covers a certain frequency range, design the pseudo-lock determination reference voltage level to change according to the frequency, so that pseudo-lock can be determined regardless of the frequency of operation. Is possible. When it is determined that the pseudo lock has occurred, the UP and DOWN outputs of the phase comparator are forcibly inverted to guide the convergence to a desired voltage. Also, pseudo lock can be avoided by forcibly resetting to the initial value.

  When the source clock is stopped, the output signal from the phase comparator always outputs a signal that delays the phase. For this reason, since the charge pump voltage always changes in the direction of delaying the delay, the source clock stop determination reference voltage level has a margin slightly higher than the charge pump voltage at which the slowest frequency in the DLL specification should be locked. The charge pump voltage should be set to be locked. Since this voltage does not depend on the source clock frequency, it may be set to a constant voltage. When the charge pump voltage exceeds the source clock stop determination reference voltage and changes in a direction in which the delay amount becomes larger, the reset circuit is controlled to automatically wait for the source clock to be reinput.

  Further, when the frequency of the source clock is changed, the pseudo lock can be avoided by designing the pseudo lock determination reference voltage level so as to change according to the frequency.

  By comparing the pseudo lock determination reference voltage level or the source clock stop determination reference voltage with the charge pump voltage, it is determined that the pseudo lock, the source clock stop, and the source clock frequency fluctuation have occurred.

  In the DLL circuit, when a phase lock (pseudo lock) occurs at a location deviated from a necessary phase, the output of the phase comparator is forcibly output to reduce the delay of the delay circuit. And converge to the desired voltage. Also, pseudo lock can be avoided by forcibly resetting to the initial value.

  When the external source clock stops, the charge pump circuit is always fixed in the discharged (charged) state, and the charge pump voltage is below (exceeds) the clock stop determination voltage level. Then, it is possible to reset the circuit internal state to the initial state and automatically start the phase lock when the clock is restarted again.

  When the frequency of the external source clock is changed, the pseudo lock determination voltage is automatically changed, so that pseudo lock can be prevented.

  No need for external reset control during abnormal operation.

  The necessary circuits are only a charge pump voltage comparison circuit and a frequency variable pseudo lock determination voltage generation circuit, and the circuit scale is small. In addition, even if the number of delay elements is increased, the circuit scale does not increase.

  In the present invention, it is possible to prevent a false lock. Further, this DLL circuit can be automatically initialized when an abnormal state of the source clock stoppage or frequency change of the source clock occurs, and an external reset sequence is not required. In addition, since only one pseudo lock determination circuit is required for the charge pump unit, the circuit scale is small, and even when the number of delay elements in the phase delay circuit is increased, the circuit scale for preventing pseudo lock is increased. It will never grow.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 9 is a block diagram of a pseudo lock prevention DLL circuit according to an embodiment of the present invention.

  In FIG. 9, 1 is a charge pump circuit, 2 is a phase delay circuit, 3 is a phase comparator, 4 is a phase control circuit, 5 is a reset circuit, 8 is a charge pump voltage comparison circuit, and 9 is a pseudo lock reference voltage generation circuit. is there. A source clock (signal A) input from the outside is delayed by the phase delay circuit 2 to create a signal delayed from the source clock (signal B). The phase of the signal A and the signal B of the previous cycle is compared by the phase comparator 3. When the phase of the signal A is advanced, UP is indicated. When the phase of the signal B is advanced, the signal DOWN (signal C ) Is output. The UP and DOWN signals at this time are when the delay amount of the phase delay circuit 2 becomes small when the charge pump voltage of 1 is high, and when the charge pump voltage is low, the delay amount of the phase delay circuit 2 When designed to be small, the polarities of UP and DOWN are reversed. When the UP signal is output from the phase comparator 3, the current from the constant current source is supplied and the phase information is accumulated as a voltage (signal D) while the UP signal is output to the charge pump circuit 1. When the DOWN signal is output from the phase comparator 3, current is drawn out by the constant current source while the DOWN signal is output from the charge pump circuit 1. The value of the voltage (signal D) of the charge pump circuit 1 is input to the phase control circuit 4 and the delay amount of the delay circuit 2 is controlled. When the phases of the signal A and the signal B are aligned, the UP and DOWN signals are not output, and the charging / discharging of the signal D is stopped. Also, the signal D is compared with the output voltage of the pseudo lock reference voltage generation circuit 9 by the charge pump voltage comparison circuit 8. As shown in FIG. 8, since the lock frequency and the voltage of the charge pump are uniquely determined, it is possible to confirm whether the lock is normal lock or pseudo lock by monitoring the charge pump voltage. Since the pseudo lock is generated when the internal delay clock is delayed from the source clock by two cycles or more, the charge pump that locks the output voltage level of the pseudo lock determination reference voltage generation circuit when the frequency is half the frequency to be locked. What is necessary is just to set to the charge pump voltage side at the frequency which should be locked rather than a voltage. If you want to configure a DLL circuit that covers a certain frequency range, design the pseudo-lock determination reference voltage level to change according to the frequency, so that pseudo-lock can be determined regardless of the frequency of operation. Is possible. FIG. 10 shows a block diagram of a charge pump voltage comparison circuit in one embodiment of the present invention.

  1 is a charge pump circuit, 3 is a phase comparator, 10 is a comparator, 9 is a pseudo-lock reference voltage generation circuit, and 11 is a phase comparator control circuit.

  One charge pump circuit and nine pseudo-lock reference voltage generation circuits are connected to the inputs of ten comparators, respectively, and the voltages of 1 and 9 are compared. When the voltage of 1 is high, the output of the 10 comparator becomes L level. When the voltage of 9 exceeds the voltage of 1, the output of the 10 comparator becomes H level for the first time. The 10 comparator outputs are input to the 11 phase comparator control circuit, and the output of the phase comparator is forcibly output in the direction of advancing the phase of the delay clock.

  FIG. 11 shows a configuration diagram of the phase comparator control circuit.

  2 is a phase delay circuit, 3 is a phase comparator, 8 is a charge pump voltage comparison circuit, 12 is a D-FF circuit, 13 is an inverter, 14 is a NAND circuit, and 15 is an AND circuit.

  The charge pump voltage comparison circuit 8 is connected to a two-stage D-FF. The clock input of the D-FF is obtained by inverting the source clock with 13 inverters. The output of the first stage D-FF and the D-FF inverted output of the second stage are input to 14 NAND circuits. With this connection, a signal determined to have a pseudo lock voltage by the charge pump voltage comparison circuit can be made a signal that becomes L by the width of 1T of the source clock. The output of this NAND circuit is input to the source clock line which is input to the phase comparator 3 through 15 AND circuits. Thereby, when the charge pump voltage comparison circuit of 8 determines the pseudo lock voltage, the signal on the source clock side inputted to the phase comparator of 3 can be masked by 1T. This allows the phase comparator to transition from pseudo lock to normal lock. When an AND circuit is inserted only on the source clock side of the phase comparator 3, a signal delay occurs only on the source clock side. Therefore, an AND circuit of the same size is also inserted between the phase comparator 2 and the final phase of the phase 2. Insert and fix one side input to H. Thereby, the delay shift of the inserted AND circuit can be eliminated.

  Next, a detection circuit when the source clock is stopped will be described. FIG. 12 shows a configuration diagram of a charge pump voltage comparison circuit in one embodiment of the present invention to which a detection circuit in the case where the source clock is stopped is added.

  1 is a charge pump circuit, 3 is a phase comparator, 5 is a reset circuit, 10 is a comparator, 12 is a D-FF circuit, 9 is a pseudo lock reference voltage generation circuit, 15 is an AND circuit, and 16 is a delay element.

  One charge pump circuit and nine pseudo-lock reference voltage generation circuits are connected to the inputs of ten comparators, respectively, and the voltages of 1 and 9 are compared. When the voltage of 1 is high, the output of the 10 comparator is designed to be L level. When the voltage of 9 exceeds the voltage of 1, the output of the 10 comparator becomes H level for the first time. Although the comparator output of 10 is connected to the input of 12 D-FF circuits, since the source clock is stopped, the 12 D-FF circuits are not latched, and the output point F of the D-FF circuit is L, the point G of the inverted output remains H. The 10 comparator outputs are input to 16 delay elements. The comparator output H delayed by 16 is connected to the inputs of 15 AND circuits. When the point G and the point H become H at the same time, a reset signal is given to the reset circuit 5 to initialize the circuit inside.

  In the charge pump voltage comparison circuit according to one embodiment of the present invention to which a detection circuit when the source clock is stopped is added, the case where the source clock does not stop and a pseudo lock occurs will be described. When the voltage of 9 exceeds the voltage of 1, the output of the 10 comparator becomes H level for the first time. The comparator output of 10 is connected to the input of 12 D-FF circuits, and the output point F of the D-FF circuit is H. Further, the inverted output point G of the D-FF circuit is L. The 10 comparator outputs are input to 16 delay elements. The output of the comparator delayed by 16 is connected to the input of 15 AND circuits. When the 10 comparator circuit changes from L to H, the inverted output point G of the D-FF circuit changes from H to L, and the comparator output of the point H input to the AND changes from L to H. If the design does not share the H period, the reset circuit 5 does not function. In order not to share the period of H, 16 delay elements are installed. Since the outputs of the 12 D-FF circuits are synchronized with the source clock, the output of the D-FF circuit changes after a maximum of 1T after the output value of the 10 comparator changes. Therefore, the comparator output at the point H input to the 15 AND circuit needs to be slower than the changing point of the point G, so the case where the frequency is the slowest within the drive frequency with the 16 delay elements is considered. The delay of 1T is necessary. Since the output point F of the D-FF circuit is H, the pseudo lock detection signal is input to the phase comparator 3 and the output of the phase comparator is forcibly output in the direction of advancing the phase of the delay clock. . As described above, even in the charge pump voltage comparison circuit including the detection circuit when the source clock is stopped, the pseudo lock detection function operates without any problem.

  Further, as a second embodiment of the detection circuit when the source clock is stopped, the charge pump voltage comparison circuit 2 according to one embodiment of the present invention is added with the detection circuit when the source clock is stopped as shown in FIG. Indicates. The comparator output 10 in the above figure is directly connected to the reset circuit 5. It is possible to solve the problem by forcibly initializing the internal circuit when a pseudo lock occurs, when the source clock is stopped, when the source clock frequency is changed, or when any abnormal state is determined. .

  FIG. 14 is a block diagram showing a pseudo lock determination voltage generation circuit according to one embodiment of the present invention.

  Reference numeral 17 denotes a current mirror circuit, 18 denotes a frequency current variable circuit, and 19 denotes a constant voltage generation circuit.

  The current mirror circuit 17 is formed by connecting the gate and drain of the transistor Q1 and the gate of the transistor Q2 having the same size as Q1, and the connection point is connected to the 19 constant voltage generation circuit. In the frequency current variable circuit 18, a capacitor C 1 is installed between the constant voltage generation circuit 19 and the ground via the analog switch SW 1, and is connected from the constant voltage generation circuit 19 to the ground via the analog switch SW 2. . The analog switch SW3, analog SW4, and capacitor C2 are also connected to the constant voltage generation circuit 19 with the same configuration. The analog switch SW1 is turned on and off by a clock, and the constant voltage generation circuit 19 charges the capacitor C1 only when the analog switch SW1 is turned on. The analog switch SW2 is turned on and off by the inverted signal of the clock. When the analog switch SW1 is turned off, the analog SW2 is turned on and discharges the electric charge charged in the capacitor C1 to the ground. The analog switch SW3 is turned on and off by the inverted signal of the clock, and the charge is charged from the constant voltage generation circuit 19 to the capacitor C2 only when the analog switch SW3 is turned on. The analog switch SW4 is turned on and off by the inverted signal of the clock. When the analog switch SW3 is turned off, the analog SW4 is turned on, and the charge charged in the capacitor C2 is discharged to the ground. Since the current flowing through the frequency current variable circuit 18 changes depending on the time integration amount of charge and discharge of the capacitors C1 and C2, the current is variable depending on the frequency at which the analog switches SW1, SW2, SW3, and SW4 are turned on and off. To do. The clock connected to the analog switches SW1, SW2, SW3, and SW4 is generated from the DLL circuit external source clock, so that the current I1 corresponding to the frequency of the DLL circuit can be generated. The resistance R1 connected to the constant voltage generating circuit determines the current I2 flowing through R1 according to the voltage and resistance value of the constant voltage generating circuit. The total current I3 of the currents I1 and I2 flows through the resistor R2 by the current mirror circuit 17. The voltage generated at the output is determined by the resistance values of I3 and R2. An arbitrary output voltage that varies depending on the frequency can be obtained by the constants R1, R2, C1, and C2.

  Therefore, by using this pseudo lock determination voltage generation circuit, a pseudo lock prevention circuit corresponding to a DLL circuit having a certain frequency range can be formed, and the reference voltage changes even when the frequency of the source clock changes. Therefore, there is a pseudo lock preventing effect.

  In the DLL circuit, when a phase lock (pseudo lock) occurs at a location deviated from a necessary phase, the output of the phase comparator is forcibly output to reduce the delay of the delay circuit. And converge to the desired voltage. Also, pseudo lock can be avoided by forcibly resetting to the initial value.

  When the external source clock stops, the charge pump circuit is always fixed in the discharged (charged) state, and the charge pump voltage is below (exceeds) the clock stop determination voltage level. Then, it is possible to reset the circuit internal state to the initial state and automatically start the phase lock when the clock is restarted again.

  When the frequency of the external source clock is changed, the pseudo lock determination voltage is automatically changed, so that pseudo lock can be prevented.

  No need for external reset control during abnormal operation.

  The necessary circuits are only a charge pump voltage comparison circuit and a frequency variable pseudo lock determination voltage generation circuit, and the circuit scale is small. In addition, even if the number of delay elements is increased, the circuit scale does not increase.

Configuration diagram of conventional DLL circuit 1 is a configuration diagram of a phase delay circuit according to an embodiment of the present invention. Diagram showing normal lock of DLL circuit The figure which shows the pseudo lock (2 period lock) of a DLL circuit Diagram showing clock stop of DLL circuit 1 is a configuration diagram of a phase delay circuit with a current phase adjustment function according to an embodiment of the present invention. Configuration diagram of DLL circuit with pseudo lock prevention function of conventional example 2 The figure which shows the relationship between the lock frequency of a DLL circuit and a charge pump voltage 1 is a configuration diagram of a pseudo lock prevention DLL circuit according to an embodiment of the present invention. The block diagram of the charge pump voltage comparison circuit in one embodiment of this invention Configuration diagram of phase comparator control circuit The block diagram of the charge pump voltage comparison circuit which added the detection circuit when the source clock stopped in one embodiment of this invention Configuration diagram of charge pump voltage comparison circuit in one embodiment of the present invention (2) 1 is a configuration diagram of a pseudo lock determination voltage generation circuit according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Charge pump circuit 2 Phase delay circuit 3 Phase comparator 4 Phase control circuit 5 Reset circuit 6 Delay detection circuit 7 Pseudo lock prevention circuit 8 Charge pump voltage comparison circuit 9 Pseudo lock reference voltage generation circuit 10 Comparator 11 Phase comparator control circuit 12 D-FF circuit 13 Inverter 14 NAND circuit 15 AND circuit 16 Delay element 17 Current mirror circuit 18 Frequency current variable circuit 19 Constant voltage generation circuit

Claims (3)

A source clock input from the outside, a delay means for generating a clock obtained by delaying the source clock by a certain time by a delay element, a phase detection means for detecting a phase difference between the clock delayed by the delay means and the source clock, and Means for converting the phase difference detected by the phase detecting means into charge information and taking in and out charges corresponding to the phase difference; and voltage converting means for integrating the charges generated by the means for taking in and out the charges and converting them into a voltage. A DLL circuit having a delay amount control circuit for controlling the delay amount of the delay means from the voltage of the voltage conversion means, wherein the voltage value of the voltage conversion means is not in a voltage range exceeding a threshold voltage for determining abnormal operation. Voltage detection means for detecting whether or not the voltage detection means determines that the voltage threshold value for abnormal operation has been exceeded, and outputs a charge corresponding to the phase difference. Pseudo lock prevention DLL circuit Les forcibly control signal means for performing, characterized by having means for in a direction to reduce the amount of delay means for the delay. 2. The DLL circuit according to claim 1, further comprising means for setting an internal circuit to an initial state when it is determined by the voltage detection means that a voltage threshold value for abnormal operation has been exceeded. circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the threshold voltage of the abnormal operation of the voltage detecting means varies depending on the frequency of a source clock input from the outside. DLL circuit.

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