JP2007273727A - Alignment mark and method for forming the same, semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an alignment mark that is restrained in deterioration of positioning accuracy, even after passage of an epitaxial film deposition process and high-temperature annealing process. <P>SOLUTION: The alignment mark 14 is formed by a stepwise step difference pattern in a cross-sectional shape. The step difference pattern includes a first step difference pattern 11, formed by digging down a principal surface of a substrate 2; and a second step difference pattern 13, formed by further digging down the principal surface of the substrate 2, in continuation with the first step difference pattern 11 below the first step difference pattern 11 formed by digging down the principal surface of the substrate 2. A sidewall part 17 of the first step difference pattern 11 and a sidewall part 18 of the second step difference pattern 13 are formed at the same angle and is formed so as to have the same crystal orientation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an alignment mark used for alignment of a semiconductor substrate and a transfer mask.

  In a semiconductor device manufacturing process, a resist pattern transfer process, an etching process for processing a semiconductor substrate using the resist pattern as a mask, a semiconductor substrate cleaning process, a semiconductor substrate film forming process, and the like are repeatedly performed.

  A desired semiconductor device is manufactured on a semiconductor substrate (hereinafter sometimes simply referred to as “substrate”).

  An exposure apparatus is used for forming the resist pattern. The exposure apparatus irradiates the alignment mark formed on the semiconductor substrate with light, and optically detects the position of the alignment mark using an alignment signal waveform indicating the intensity change of the diffusely reflected light that returns.

  Then, the exposure apparatus performs exposure after aligning the semiconductor substrate and the transfer mask based on the detected position information of the alignment mark.

  In each transfer process, since the semiconductor substrate and the transfer mask can be aligned, a semiconductor device almost as designed can be manufactured even if many processes are repeated.

  Hereinafter, the difference between the position of the pattern to be transferred and the position of the actually transferred pattern is defined as the alignment error, and 3σ of the variation in the alignment error is defined as the alignment accuracy.

  A decrease in the alignment accuracy means that the value of the alignment accuracy is large, and that the alignment error of the transferred pattern position is statistically large. In order to manufacture a highly accurate semiconductor device, the smaller the value of alignment accuracy, the better.

  On the contrary, if the value of the alignment accuracy in the substrate or for each substrate is increased, it is not desirable because it causes a decrease in the yield of the semiconductor device.

  Originally, it is desirable that the alignment mark shape formed on the substrate (for example, the dimension of the alignment mark pattern or the step shape) does not change even after the semiconductor manufacturing process.

  However, the alignment mark shape may change depending on the semiconductor manufacturing process.

  As a result, the accuracy of alignment within the substrate or for each substrate is reduced, and in extreme cases, alignment may not be possible.

  For example, in Patent Document 1, the alignment mark step is buried in the epitaxial layer by the epitaxial film formation process, and further, the epitaxial layer on the alignment mark is planarized by the planarization process. Describes problems that are invisible.

  In order to solve this problem, a method of embedding the alignment mark with a transparent material before the epitaxial film forming process, or a layer having a different crystallinity or a layer having a different impurity by ion implantation or the like instead of a stepped shape. A method of forming is disclosed.

  Further, Patent Document 2 reports a problem that the pattern size of the alignment mark in the X-axis direction and that in the Y-axis direction are different after the epitaxial film forming process because the growth rate of the epitaxial layer varies depending on the crystal orientation.

  After the epitaxial film-forming process, the difference in signal waveform from the alignment mark in the X-axis direction and the Y-axis direction is caused by the difference in the pattern size of the alignment mark in the X-axis direction and the Y-axis direction. Can not be.

  In order to solve this problem, the alignment marks in the X-axis direction and the Y-axis direction after the epitaxial film-forming process are formed by correcting the pattern dimensions of the alignment marks in the X-axis direction and the Y-axis direction in advance. The pattern dimension difference is reduced.

JP 2005-1998 A JP 2000-252189 A

  However, the inventors of the present application have found that the angle of the side wall of the end portion of the alignment mark is different at both ends after the high temperature annealing step.

  Furthermore, it has been found that when an epitaxial layer is grown on the alignment mark, the film thickness of the epitaxial layer formed at the end of the alignment mark is different at both ends.

  If the angle of the alignment mark sidewall and the thickness of the epitaxial layer are different at both ends of the alignment mark, the symmetry of the alignment signal waveform when detecting the alignment mark is lost. As a result, the alignment accuracy in the transfer process is lowered.

  In view of applying the invention described in Patent Document 1, in the invention described in Patent Document 1, the alignment mark is embedded with a transparent material before the epitaxial film forming step.

  However, in the epitaxial film formation step of silicon carbide, the epitaxial layer is grown at a high growth temperature of about 1500 ° C. to 1600 ° C.

  Therefore, denaturation and evaporation of the permeable material are caused at the growth temperature of the epitaxial layer.

  As a result, when the invention described in Patent Document 1 is applied, it becomes difficult to detect the alignment mark after the epitaxial film forming step.

  Even if a method of forming alignment marks with layers having different crystallinity or different impurities by ion implantation or the like is applied, the implanted ions accelerated by the implantation apparatus are incident on the implantation point on the substrate surface and then the substrate. Spreads in the substrate while repeatedly colliding with the components. For this reason, the pattern boundary portion of the alignment mark becomes unclear and the alignment accuracy is lowered.

  If an epitaxial layer is grown on the alignment mark after the alignment mark is formed by ion implantation or the like, but the growth rate of the epitaxial layer due to the difference in crystallinity or impurities is low, the step corresponding to the alignment mark is sufficient. It is difficult to enlarge.

  Next, considering application of the invention described in Patent Document 2, in the invention described in Patent Document 2, since the growth rate of the epitaxial layer differs depending on the crystal orientation, the pattern size of the alignment mark is corrected in advance. ing.

  However, even if the invention described in Patent Document 2 is applied, the change in the sidewall angle of the alignment mark after the high-temperature annealing process cannot be corrected only by correcting the pattern dimensions. Furthermore, the change in the step shape of the alignment mark in the epitaxial film forming process cannot be corrected.

  Therefore, the problem that the alignment accuracy decreases due to a change in the step shape of the alignment mark cannot be solved.

  Accordingly, an object of the present invention is to provide an alignment mark that can suppress a decrease in alignment accuracy even after an epitaxial film forming step or a high temperature annealing step.

  The alignment mark according to claim 1 is an alignment mark used for alignment of a substrate and a transfer mask, and further includes a first step pattern formed by digging down the substrate main surface, and the first step pattern. A second step pattern formed by digging down the main surface of the substrate, and the inclination angle of the side wall portion of the first step pattern and the inclination angle of the side wall portion of the second step pattern are the same inclination angle. It is characterized by that.

  According to the alignment mark of the first aspect, since the side wall portion of the first step pattern and the side wall portion of the second step pattern have the same inclination angle, the side wall portion is etched by high-temperature heat treatment. Even after this, the inclination angle of the side wall can be made the same. Furthermore, according to the present invention, the sidewall surfaces of the first step pattern and the second step pattern are formed with the same crystal orientation, so that the thicknesses of the epitaxial layers grown on the sidewall portions can be made equal.

  Therefore, the signal waveforms from the first step pattern and the second step pattern can be held symmetrically even after the high-temperature heat treatment and the transfer step after epitaxial growth. As a result, a decrease in alignment accuracy can be suppressed.

<Embodiment 1>
<1. Configuration>
FIG. 1 is a cross-sectional view showing the configuration of the alignment mark 14 of the semiconductor device according to the first embodiment. The alignment mark 14 according to the first embodiment is formed on the semiconductor substrate (substrate) 2 and used for alignment of the substrate 2 and the transfer mask. As shown in FIG. 1, the alignment mark 14 is a step pattern in which the main surface of the substrate 2 is dug down and the cross-sectional shape is formed in a staircase shape. The alignment mark 14 includes a first step pattern 11 and a second step pattern 13.

  The second step pattern 13 is formed below the first step pattern 11 formed by digging the main surface of the substrate 2 and further digging the main surface of the substrate 2 continuously to the first step pattern 11. The inclination angle of the side wall portion 17 of the first step pattern 11 and the inclination angle of the side wall portion 18 of the second step pattern 13 are formed at the same inclination angle. Further, the crystal orientation of the surface of the side wall portion of the first step pattern 11 and the crystal orientation of the surface of the side wall portion of the second step pattern 13 are formed with the same crystal orientation.

<2. Forming method>
<2-1. Method of forming alignment mark 14>
Next, a method of forming the alignment mark 14 according to the first embodiment will be described with reference to FIGS. 2 to 4 are cross-sectional views showing a process of forming the alignment mark 14 according to the first embodiment. First, in the step shown in FIG. 2, the first resist pattern 10 is formed on the substrate 2 having an N conductivity type using an exposure apparatus. Next, in the step shown in FIG. 3, the first step pattern 11 having the side wall portions 17 is formed by etching the substrate 2 using the first resist pattern 10 as an etching mask.

  Next, in the step shown in FIG. 4, the second resist pattern 12 is formed on the substrate 2 so as to cover the side wall portion 17 of the first step pattern 11. Then, the second step pattern 13 is formed by etching the substrate 2 again using the second resist pattern 12 as a mask. At this time, the second step pattern 13 is formed at the same depth as the first step pattern 11 so that the side wall angle and the crystal orientation of the surface of the side wall portion are the same. The alignment mark 14 shown in FIG. 1 can be formed by the above manufacturing process.

  The first step pattern 11 and the second step pattern 13 can be formed by controlling the etching depth and the sidewall angle in the etching process. Further, in the first embodiment, the steps of the first step pattern 11 and the steps of the second step pattern 13 have the same depth, but may be different.

<2-2. Manufacturing Method of Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. First, the substrate 2 on which the alignment mark 14 is formed is prepared according to the above-described process. In the transfer step, the position of the alignment mark 14 is optically detected, thereby aligning the substrate 2 and the transfer mask to expose the resist pattern.

  The position of the alignment mark 14 is the center of gravity of the step portions 17 and 18 of the alignment mark 14. The barycentric positions of the stepped portions 17 and 18 may be obtained by optically detecting the respective positions, or may be detected using a light intensity distribution including irregularly reflected light from the stepped portions 17 and 18. That is, the substrate 2 and the transfer mask are aligned using the first step pattern 11 and the second step pattern 13 of the alignment mark 14 of the substrate 2.

  Then, by repeating the transfer process for aligning the substrate 2 and the transfer mask using the alignment mark 14, ion implantation, activation annealing, epitaxial growth film forming process, etc. are performed, and finally A semiconductor device with high alignment accuracy is completed.

<3. Effect>
<3-1. Conventional technology>
In order to compare the prior art and the invention according to the first embodiment, first, a conventional method of forming the alignment mark 3 will be described with reference to FIGS. 5 to 8 are cross-sectional views showing a conventional process of forming the alignment mark 3. First, in the transfer step shown in FIG. 5, the resist pattern 1 for forming the alignment mark 3 is transferred onto the semiconductor substrate 2 of N-type silicon carbide using an exposure apparatus.

  Next, in the etching step shown in FIG. 6, the alignment mark 3 composed of a step pattern is formed by etching the substrate 2 using the resist pattern 1 as an etching mask. The alignment mark 3 includes side wall parts 5 and 6. In the process after the alignment mark 3 is formed, the alignment mark 3 and the transfer mask are aligned to form a device structure with little alignment error on the substrate 2.

  Next, in an ion implantation step (not shown), a resist pattern is formed on the substrate 2 as a shield for ion implantation, and then ion implantation is performed. When transferring a resist pattern for ion implantation, the substrate 2 and the transfer mask are aligned by detecting diffusely reflected light from the alignment mark 3 in the exposure apparatus. Then, the ion implantation step is performed a plurality of times, and an N type conductivity implantation region and a P type ion implantation region are formed on the substrate 2.

  Next, in the activation annealing step shown in FIG. 7, after removing the resist pattern used for ion implantation, heat treatment is performed for 10 minutes at a temperature range of 1600 ° C. to 1800 ° C. to activate the implanted ions. To do. Next, in the step of forming epitaxial layer 9 shown in FIG. 8, silicon carbide epitaxial layer 9 is formed on silicon carbide semiconductor substrate 2 at a temperature range of 1500 ° C. to 1600 ° C. At this time, the epitaxial layer 9 is also formed on the alignment mark 3 having a step structure, and the unevenness 4 corresponding to the step structure of the alignment mark 3 is formed on the alignment mark 3.

  Next, in the processing step of the epitaxial layer 9 (not shown), the silicon carbide semiconductor substrate 2 on which the epitaxial layer 9 is formed is detected by optically detecting the unevenness 4 corresponding to the step of the alignment mark 3 in the exposure apparatus. Is aligned with the transfer mask. Then, a resist pattern is formed at a desired position, and the epitaxial layer 9 is processed using this resist pattern as an etching mask.

<3-2. Issues of conventional technology>
Next, a description will be given of a new problem found regarding a conventional method of aligning the substrate 2 and the transfer mask in the transfer process using the substrate 2 on which the epitaxial layer 9 is formed. When transfer is performed using the substrate 2 on which the epitaxial layer 9 is formed after the film formation process of the epitaxial layer 9, the position of the transfer pattern that is actually transferred becomes larger than the position of the transfer pattern that should be transferred originally. I understood it.

  As a result, the yield of semiconductor devices in the manufacturing process has been greatly reduced. The alignment error was larger than the alignment error of the substrate 2 on which the epitaxial layer 9 deposition process and the activation annealing process were not performed. Therefore, as a result of examining in detail the change in the shape of the alignment mark 3 for each manufacturing process, the step shape of the alignment mark 3 formed on the substrate 2 for the first time by the etching process is changed by the ion implantation process and the activation annealing process. It was.

Examining in more detail, it was found that the inclination angles of the side wall portions 5 and 6 of the alignment mark 3 are different at both ends of the step-shaped alignment mark 3. Specifically, as shown in FIG. 7, it was found that the inclination angle phi _B of the inclination angle phi _A and the side wall portion 6 of the side wall portion 5 is at a different angle. Further, when the epitaxial layer 9 is grown on the alignment mark 3, the film thickness 7 of the epitaxial layer 9 on the side wall 5 of the alignment mark 3 is different from the film thickness 8 of the epitaxial layer 9 on the side wall 6 of the alignment mark 3. I found out.

  This occurs because the etching rate and growth rate of silicon carbide differ depending on the crystal orientation of the surface of the substrate 2. That is, at the time of activation annealing, the substrate 2 becomes very high temperature, so that the silicon carbide on the surface is evaporated and etched. The etching rate of the substrate 2 varies depending on the crystal orientation. Further, the growth rate of silicon carbide during the formation of the epitaxial layer 9 also depends on the crystal orientation.

  For this reason, in the activation annealing step and the step of forming the epitaxial layer 9, in the conventional alignment mark 3 having step shapes with different crystal orientations at both ends of the step pattern, the side wall angles of the side wall portions 5 and 6 at both ends of the step pattern A difference occurs in the film thickness of the epitaxial layer 9. If the angles of the side wall portions 5 and 6 at both ends of the step pattern and the film thickness of the epitaxial layer 9 are different, the symmetry of the alignment signal waveform when the alignment mark 3 is detected is lost. As a result, there arises a problem that the alignment accuracy in the transfer process is lowered.

  In the alignment mark 14 according to the first embodiment, the crystal orientations of the side wall portion 17 of the first step pattern 11 and the side wall portion 18 of the second step pattern 13 are the same. Therefore, since the side wall portion 17 and the side wall portion 18 are etched into the same shape by the high temperature annealing, the angle formed by the side wall portions 17 and 18 is kept constant even after the high temperature annealing. As a result, even after high-temperature annealing, the signal waveform from the alignment mark 14 does not change, and alignment can be performed with high accuracy.

   Furthermore, according to the alignment mark 14 according to the first embodiment, since the crystal orientation of the substrate 2 in the side wall portion 17 of the first step pattern 11 and the side wall portion 18 of the second step pattern 13 is the same, the side wall portion 17. , 18 can be formed with an epitaxial layer having the same film thickness. As a result, the alignment of the epitaxial layer 9 can be performed with high accuracy.

  According to the method of forming the alignment mark 14 according to the first embodiment, it is possible to easily manufacture the alignment mark 14 having a stepped step pattern and the side walls 17 and 18 having the same angle and the same crystal orientation.

  Since the semiconductor device according to the first embodiment includes the alignment mark 14, it can be manufactured by a manufacturing method in which the alignment of the semiconductor substrate 2 and the transfer mask is accurately performed using the alignment mark 14 even after high-temperature annealing. .

  In the method of manufacturing a semiconductor device according to the first embodiment, the step of preparing the semiconductor substrate 2 including the alignment mark 14 and the alignment of the semiconductor substrate 2 and the transfer mask using the alignment mark 14 of the semiconductor substrate 2 are performed. Therefore, alignment can be performed with high accuracy even after high-temperature annealing or epitaxial film formation, and a semiconductor device with high overlay accuracy can be manufactured.

<Embodiment 2>
<1. Configuration>
FIG. 9 is a top view showing the configuration of the alignment mark 16 according to the second embodiment. FIG. 9 illustrates an alignment region 15 in the semiconductor device where the alignment mark 16 is formed. The alignment mark 16 according to the second embodiment is a two-dimensional alignment mark.

  As shown in FIG. 9, in the alignment mark 16 according to the second embodiment, the first step pattern 11 is formed in a cross shape in plan view. Then, in plan view, the second step pattern 13 is arranged at two locations so as to sandwich the cross-shaped center of the first step pattern 11 diagonally. Then, as shown in FIG. 9, alignment marks D, E, F, and G are formed by the first step pattern 11 and the second step pattern 13.

  In the cross-shaped first step pattern 11, alignment marks D and E are arranged symmetrically with respect to the Y axis, and alignment marks F and G are arranged symmetrically with respect to the X axis. The cross-sectional shapes of the alignment marks D, E, F, and G are formed in a step shape, and are formed in the same shape as that of FIG. For example, the shape of the cross section along line AA of the alignment mark E shown in FIG. 9 is formed in the same shape as FIG.

<2. Forming method>
<2-1. Method of forming alignment mark 16>
Next, a method for forming the alignment mark 16 according to the second embodiment will be described with reference to FIGS. 10 to 12 are top views showing the steps of forming the alignment mark 16 according to the second embodiment. First, as shown in FIG. 10, the first resist pattern 10 for forming the first step pattern 11 is formed in the alignment region 15 on the substrate. The first resist pattern 10 includes an opening 19.

  Next, in the process shown in FIG. 11, the first step pattern B is formed by etching using the first resist pattern 10 as a mask, and the first resist pattern 10 is removed. Next, in the step shown in FIG. 12, the second resist pattern 12 is formed so as to cover a part of the first step pattern B, and the substrate is etched to form a first step formed in a cross shape in plan view. The second step pattern 13 is formed so as to be disposed at two locations opposite to the pattern 11 so as to sandwich the center of the cross shape obliquely. Then, by removing the second resist pattern 12, the alignment mark 16 shown in FIG. 10 can be obtained.

<2-2. Manufacturing Method of Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. First, a substrate having alignment marks 16 in the alignment region 15 is prepared by the above-described forming method. Next, a resist pattern (not shown) is formed on the substrate as an ion implantation shield. When this resist pattern is transferred, the substrate and the transfer mask are aligned by detecting diffusely reflected light from the alignment mark 16 in the exposure apparatus.

  At this time, alignment mark F or G is used for alignment in the X-axis direction, and alignment mark D or E is used for alignment in the Y-axis direction. The ion implantation process is performed a plurality of times to form an N type conductivity implantation region and a P type implantation region on the substrate. Next, after removing the resist pattern, activation annealing is performed in a temperature range of 1600 ° C. to 1800 ° C. for 10 minutes.

  At this time, the substrate surface is evaporated and etched by the high-temperature activation annealing. As described in the first embodiment, the side wall portion 17 (see FIG. 1) of the first step pattern 11 and the second step pattern 13 Since the side wall portion 18 has the same crystal orientation, it is etched at the same speed.

  As a result, even when the inclination angles of the side wall portions 17 and 18 change between the first step pattern 11 and the second step pattern 13, both of them change in the same way. There is no difference between the inclination angles of the portions 17 and 18. Further, since the alignment mark 16 is not embedded with a transmissive material or the like, a problem such as evaporation of the embedded material does not occur.

  Next, an epitaxial layer of silicon carbide is formed on the semiconductor substrate at a temperature range of 1500 ° C. to 1600 ° C. At this time, an epitaxial layer is also formed on the alignment mark 16 having a step structure, and irregularities corresponding to the step structure are formed on the alignment mark 16. Since the side wall portion 17 of the first step pattern 11 and the side wall portion 18 of the second step pattern 13 have the same crystal orientation, the epitaxial layers grow at the same growth rate, and the epitaxial layers of the side wall portions 17 and 18 are grown. Are formed with the same film thickness. Since the alignment mark 16 has a step structure, it can be clearly observed optically even after the epitaxial layer is formed.

  Next, the exposure apparatus optically detects the unevenness corresponding to the step of the alignment mark 16, thereby aligning the silicon carbide substrate with the epitaxial layer and the transfer mask, and transferring the resist pattern to a desired position. To do. The epitaxial layer is processed by etching the resist pattern. The semiconductor device is completed by repeating the above steps.

<3. Effect>
According to the alignment mark 16 according to the second embodiment, a difference occurs between the side wall angles of the first step pattern 11 and the second step pattern 13 constituting the alignment mark 16 even after the activation annealing process and the epitaxial process. Therefore, an alignment signal waveform having better symmetry than the conventional one can be obtained. As a result, it is possible to obtain a significant effect of improving the alignment accuracy and suppressing the deterioration of the alignment accuracy, compared to the case where the conventional alignment mark is used.

  In addition, alignment in the exposure apparatus is usually performed in both the X-axis direction and the Y-axis direction. For example, in a cross-shaped alignment mark, alignment in the Y-axis direction is performed using a long pattern in the X-axis direction, and alignment in the X-axis direction is performed using a long pattern in the Y-axis direction.

  Since the alignment mark 16 according to the second embodiment includes the alignment marks D and E, either the alignment mark D or the alignment mark E can be used as the alignment mark for alignment in the Y-axis direction. In addition, since the alignment mark 16 according to the second embodiment includes the alignment marks F and G, in the alignment in the X-axis direction, either the alignment mark F or the alignment mark G is used as the alignment mark. it can.

  As shown in FIG. 10, in the alignment mark 16, the alignment mark D and the alignment mark E have different crystal orientations in the side wall portion of the step pattern. Further, the alignment mark F and the alignment mark G have different crystal orientations of the side wall portions of the step pattern.

  Therefore, the alignment mark 16 according to the second embodiment can be aligned by selecting one of two types of step patterns having different crystal orientations in the alignment in the X-axis direction and the Y-axis direction. is there. As a result, in the transfer process after activation annealing or after epitaxial film formation, it is possible to perform alignment by selecting a step pattern having a crystal orientation that can provide higher alignment accuracy.

  In the conventional alignment mark forming method, it is impossible to simultaneously form a plurality of alignment marks having different crystal orientations of the step pattern. However, in the alignment mark forming method according to the second embodiment, two types of step patterns having different crystal orientations can be easily formed simultaneously in the X-axis direction and the Y-axis direction, respectively.

  Since the semiconductor device according to the fourth embodiment includes the alignment mark 16, it can be manufactured by a manufacturing method that uses the alignment mark 16 to accurately align the substrate and the transfer mask even after high-temperature annealing.

  According to the method for manufacturing a semiconductor device according to the second embodiment, alignment can be performed by selecting an alignment mark that provides high alignment accuracy from two types of alignment marks having different crystal orientations. In the second embodiment, it goes without saying that the offset amount of the alignment error and the intensity adjustment of the alignment signal intensity are performed at the time of alignment as in the conventional case.

3 is a cross-sectional view showing a configuration of an alignment mark according to Embodiment 1. FIG. FIG. 6 is a cross-sectional view showing an alignment mark forming process according to the first embodiment. FIG. 6 is a cross-sectional view showing an alignment mark forming process according to the first embodiment. FIG. 6 is a cross-sectional view showing an alignment mark forming process according to the first embodiment. It is sectional drawing which shows the formation process of the conventional alignment mark. It is sectional drawing which shows the formation process of the conventional alignment mark. It is sectional drawing which shows the formation process of the conventional alignment mark. It is sectional drawing which shows the formation process of the conventional alignment mark. 6 is a top view showing a configuration of an alignment mark according to Embodiment 2. FIG. FIG. 10 is a top view showing an alignment mark forming process according to the second embodiment. FIG. 10 is a top view showing an alignment mark forming process according to the second embodiment. FIG. 10 is a top view showing an alignment mark forming process according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Resist pattern, 2 Substrate, 3, 14, 16, D, E, F, G Alignment mark, 4 Concavity, convexity, 5, 6, 17, 18 Side wall part, 7, 8 Film thickness, 9 Epitaxial layer, 10 First resist Pattern, 11 first step pattern, 12 second resist pattern, 13 second step pattern, 14 alignment mark, 15 alignment region, 19 opening.

Claims (6)

An alignment mark used for alignment of a substrate and a transfer mask,
A first step pattern formed by digging down the substrate main surface;
A second step pattern formed by further digging the substrate main surface from the first step pattern;
With
The alignment mark, wherein an inclination angle of the side wall portion of the first step pattern and an inclination angle of the side wall portion of the second step pattern are the same inclination angle. The first step pattern is formed in a cross shape in plan view,
2. The alignment mark according to claim 1, wherein the second step pattern is disposed at two locations facing each other so as to obliquely sandwich the center of the cross shape of the first step pattern in plan view. . (A) forming a first step pattern on the substrate by forming a first resist pattern on the substrate and etching the substrate using the first resist pattern as a mask;
(B) A second resist pattern is formed on the substrate, and the substrate is etched using the second resist pattern as a mask, so that the substrate main surface is further dug down from the first step pattern. Forming a second step pattern;
A method of forming an alignment mark, comprising:   In the step (b), the second step is arranged so that the first step pattern has a cross shape in plan view, and is disposed at two positions facing each other so as to sandwich the center of the cross shape diagonally. The method of forming an alignment mark according to claim 3, further comprising a step of forming a pattern.   A semiconductor device comprising the alignment mark according to claim 1. A method of manufacturing a semiconductor device comprising the alignment mark according to claim 1 or 2,
(A) preparing a substrate including the alignment mark according to claim 1 or 2,
(B) aligning the substrate and the transfer mask using the first step pattern and the second step pattern of the alignment mark of the substrate;
A method for manufacturing a semiconductor device, comprising:

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