JP2007288729A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which is immune to in-phase noise that is an advantage of a differential input type VCO circuit and further, of which an input voltage range is wider than a single input. <P>SOLUTION: The present invention relates to a PLL circuit which comprises a differential input type VCO circuit a loop filter circuit and a phase detection circuit and is provided in a semiconductor integrated circuit, the PLL circuit being provided in the semiconductor integrated circuit including: the phase detection circuit for supplying a phase detected signal to the differential input type VCO circuit; the loop filter circuit to which an output of the phase detection circuit and one differential input of the differential input type VCO circuit are connected and which is provided between the output of the phase detection circuit and a ground; and a bias circuit for dummy output which supplies a bias voltage approximately equal with the phase detection circuit to another differential input of the differential input type VCO circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technology of a PLL circuit provided in an IC chip (semiconductor integrated circuit).

  In recent years, mobile devices and the like have become smaller and more functional, and the number of IC chips and external components to be mounted has increased, and the design time for laying out components tends to increase. For this reason, there is an increasing demand for reducing the number of externally attached IC chips as much as possible. In particular, since a PLL (Phase Locked Loop) circuit has a low-pass filter such as a loop filter, a capacitor element or a resistor element constituting the PLL circuit may not be provided in the IC chip and may be an external component.

  A general PLL circuit is shown in FIG. The phase detection circuit of the PLL circuit as shown in FIG. 4 includes resistance elements 41 to 44 and switches 45 and 46. The loop filter circuit includes a resistance element 47 and capacitance elements 48 and 49 outside the IC chip, and includes terminals 410 and 411 as external terminals of the IC chip.

  Further, a VCO (Voltage Controlled Oscillator) circuit 412 is provided. In this circuit, a reference signal (reference frequency) or a signal including the reference signal is input from a signal input terminal 413, and a reference voltage signal (DC voltage) is input from a reference signal terminal 414. The switches 45 and 46 are continuously turned on / off with a clock obtained by dividing the output signal of the VCO circuit 412. The VCO circuit 412 adopts a differential input type. By adopting such a differential configuration, it is possible to obtain noise-resistant characteristics.

  However, since the loop filter is a differential output, the two capacitance elements 48 and 49 and the one resistance element 47 are all externally attached, and two external terminals 410 and 411 are required. . Therefore, among the three external parts (two capacitive elements and one resistive element) shown in the prior art, the resistive element 47 is built in the IC chip, and the two capacitive elements are not built in the IC chip and are externally attached. Proposals have been made.

  According to Patent Document 1, the influence of noise from disturbances such as fluctuations in the ground and power supply at the time of startup by a transmission-side power amplifier that operates at a large current, and electromagnetic field interference received by electromagnetic waves radiated from an antenna. Countermeasures have been proposed. That is, it is a proposal for canceling the influence of common mode noise from a disturbance in which the oscillation carrier of the voltage controlled oscillator is strongly influenced by the operating environment.

According to Patent Document 2, when a low voltage power supply is operated and it is necessary to increase the sensitivity of frequency change with respect to the control voltage of the VCO in order to generate a high frequency output, noise is mixed in the control voltage. Proposals to reduce the effects of
JP 2000-332602 A JP 09-83357 A

  However, when the resistance element is incorporated in the IC chip to reduce the number of external parts, one of the capacitor element and the terminal of the loop filter circuit provided in the IC chip is connected. In addition, the other of the capacitive elements must be connected to a ground (GND) line wired on a board prepared by the user. That is, it becomes a single connection instead of the differential connection shown in FIG.

However, the differential input type VCO circuit is resistant to common-mode noise and has an advantage that the input voltage range is wider than that of a single connection input. Therefore, a circuit that makes full use of this advantage is required.
According to Patent Document 1, a PLL circuit is configured by a charge pump, a loop filter, and a voltage-controlled oscillator that can transfer input and output with a differential signal, and information transfer with a voltage signal with respect to a conventional ground potential is performed. Thus, differential signals can be passed, and it becomes possible to cancel the influence of noise in the same phase on the electromagnetic interference caused by the electromagnetic wave interference caused by the electromagnetic wave radiated from the antenna and the electromagnetic wave due to the ground or power supply potential change.

  According to Patent Document 2, a VCO that is resistant to noise and has high sensitivity can be used, and the in-phase component of noise in the phase comparison output is in the form of a balanced signal, so that it can be configured to be resistant to noise. . Further, a highly sensitive VCO can be used, and a PLL circuit suitable for a low power supply voltage can be configured.

However, the number of external parts cannot be reduced because a single connection is not possible.
The present invention has been made in view of the above circumstances, and is resistant to the common-mode noise that is an advantage of the differential input type VCO circuit without changing the proven differential input type VCO circuit, and further has an input voltage range. An object of the present invention is to provide a PLL circuit that is wider than a single input.

A PLL circuit provided in a semiconductor integrated circuit, comprising a differential input type VCO circuit, a loop filter circuit, and a phase detection circuit, which are one aspect of the present invention,
The phase detection circuit for supplying a phase-detected signal to the differential input type VCO circuit, the output of the phase detection circuit and one differential input of the differential input type VCO circuit are connected, and the phase detection circuit The loop filter circuit between the output and ground;
And a dummy output bias circuit for supplying substantially the same bias voltage as that of the phase detection circuit to the other differential input of the differential input type VCO circuit.

Preferably, the resistor element constituting the loop filter circuit is built in the semiconductor integrated circuit, and the first capacitor element and the second capacitor element are externally attached,
The resistor element and the first capacitor element are connected in series, and the second capacitor element is connected in parallel with the series connected circuit between the differential input of the differential input type VCO circuit and the ground. .

Preferably, the phase detection circuit may be a Gilbert cell system.
With the above configuration, a PLL circuit that is resistant to common-mode noise even with a single connection and has a wider input voltage range than a single input can be configured. Moreover, external parts can be reduced.

  According to the present invention, the configuration of the phase detection circuit and the loop filter circuit can reduce the external parts of the loop filter circuit. In addition, it is possible to construct a PLL circuit that is resistant to common-mode noise and has a wider input voltage range than a single connection without changing the conventional differential input type VCO circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Example 1
The circuit shown in FIG. 1 is a circuit showing the principle of the present invention. This circuit includes a phase detection circuit (such as a Gilbert cell), a loop filter circuit, and a VCO circuit 22. The detection unit includes an input unit, a Gilbert cell unit, and an output unit.

  The input unit is a current source 1, resistance elements 2 and 3, transistors 4 and 5 (P-channel, for example, PMOS: P-channel Metal-Oxide Semiconductor), transistors 6 and 7 (N-channel, for example, NMOS: N-channel Metal-Oxide Semiconductor) Consists of The input unit is connected to a power source voltage (VDD) connected to the current source 1, and the resistance elements 2 and 3 are connected to the other side of the current source 1. The other end of resistance element 2 is connected to the source of transistor 4. Further, the resistance element 3 and the source of the transistor 5 are connected. The drain of the transistor 4 is connected to the gate and drain of the transistor 6. The drain of the transistor 5 is connected to the gate and drain of the transistor 7. The sources of the transistors 6 and 7 are connected to the ground (GND).

  A signal (input signal) including a reference signal (reference frequency signal) is input to the gate of the transistor 4. A signal reference voltage signal (REF signal: DC reference voltage) is input to the gate of the transistor 5.

  The Gilbert cell section includes transistors (P channel, for example, PMOS: P-channel Metal-Oxide Semiconductor) 8 and 9, transistors (N channel, for example, NMOS: N-channel Metal-Oxide Semiconductor) 10, 11, 12, 13, 14, 15 And a dummy output bias circuit 16. The gate of the transistor 14 is connected to the gate of the transistor 6 to form a current mirror circuit. The gate of the transistor 15 is connected to the gate of the transistor 7 to form a current mirror circuit. The sources of the transistors 14 and 15 are grounded to the ground (GND). The gate of the transistor 8 is connected to the drain. The gate of the transistor 9 is connected to the drain. The sources of the transistors 8 and 9 are connected to the power supply voltage (VDD).

  Next, the source of the transistor 10, the drain of the transistor 8, and the source of the transistor 12 are connected. The source of the transistor 11, the drain of the transistor 9, and the source of the transistor 13 are connected.

  The gate of the transistor 10 and the gate of the transistor 13 are connected and connected to the VCO circuit 22 (CK). The gate of the transistor 11 and the gate of the transistor 12 are connected and connected to the VCO circuit 22 (XCK: inverted output of CK). The CK signal and the XCK signal shown in FIG. 1 are continuously turned on and off with a clock generated by dividing the output of the VCO circuit 22.

Then, the phase comparison is performed between the reference signal (reference frequency signal) input from the input unit and CK and XCK input from the VCO circuit 22, and the result is transferred to the output unit.
Here, in order to operate this circuit at a low voltage, folding is performed using the transistors 6, 7, 14, and 15. If there is a margin in the supply voltage (VDD), there is no need to turn back.

  The output unit includes transistors 17 and 19, (P-channel, for example, PMOS: P-channel Metal-Oxide Semiconductor) resistance elements 19 and 20, and a resistance element 21. The transistor 17 and the resistance element 18 are connected in series between the power supply voltage (VDD) and the ground (GND). A current mirror bias voltage (for the Gilbert cell unit) is supplied from the gate of the transistor 17 to the drain of the transistor 9 in the Gilbert cell unit.

  The transistor 19 and the resistance element 20 are connected in series between the power supply voltage (VDD) and the ground (GND). The gate of the transistor 19 is connected to the dummy output bias circuit 16 to supply a current mirror bias voltage (for the dummy output bias circuit 16). The dummy output bias circuit 16 will be described later.

Since this circuit is operated at a low voltage, the output section is also folded. If there is a margin in the supply voltage (VDD), there is no need to turn back.
The loop filter section is composed of terminals 23 and 24, and external capacitor elements 25 (first capacitor elements) and 26 (second capacitor elements). The resistance element 21 is built in the IC chip. The external capacitor elements 25 and 26 are connected to a ground (GND) wired on a board prepared by the user. Here, the ground has the same potential when connected to the ground in the IC chip. A VCO circuit 22 is connected downstream of the loop filter unit. The loop filter unit receives the phase comparison result output from the output unit and outputs the control voltage of the VCO circuit 22.

  Although the VCO circuit 22 is not described in detail here, it is a differential input type VCO circuit 22. However, since the loop filter circuit is single-connected, the output of the output unit for the Gilbert cell unit is connected to the gate of the differential circuit transistor constituting the input unit of the VCO circuit 22 via the loop filter circuit unit. Further, the transistor 19 of the output section for the dummy output bias circuit 16 and the resistance element 20 are connected to the gate of the transistor of the other differential circuit constituting the input section of the VCO circuit 22.

Next, the dummy output bias circuit 16 constitutes a circuit that consumes substantially the same current as the current consumed by the input unit, the Gilbert cell unit, and the output unit described above.
As described above, the phase detection circuit is a single output of the Gilbert cell unit, and the loop filter circuit is single-connected. On the other hand, the differential input of the VCO circuit 22 can be connected to the output of the loop filter circuit and the output of the dummy output bias circuit 16 for generating a dummy voltage, thereby reducing the number of external components. It is strong against common-mode noise, which is an advantage of the VCO circuit, and can make the input range wider than a single connection.
(Example 2)
Next, a more detailed configuration of the dummy output bias circuit 16 described in the first embodiment will be described. The dummy output bias circuit 16 shown in FIG. 2 includes a current source 201, a transistor (NMOS) 202, transistors (PMOS) 203 and 204, and transistors (NMOS) 205, 206, 207, 208, 209, and 2010. The gates of the transistors 209 and 2010 are connected to the gate of the transistor 202. The sources of the transistors 209 and 2010 are grounded to the ground (GND). The gate of the transistor 203 is connected to the drain. The gate of the transistor 204 is connected to the drain. The sources of the transistors 203 and 204 are connected to the power supply voltage (VDD).

  Next, the source of the transistor 205, the drain of the transistor 203, and the source of the transistor 207 are connected. The source of the transistor 206, the drain of the transistor 204, and the source of the transistor 208 are connected. The transistor 19 is connected to the input of the VCO circuit 22.

  The gate of the transistor 205 and the gate of the transistor 208 are connected and connected to the VCO circuit 22 (CK). The gate of the transistor 206 and the gate of the transistor 207 are connected and connected to the VCO circuit 22 (XCK). The CK signal and the XCK signal shown in FIG. 1 are continuously turned on and off with a clock generated by dividing the output of the VCO circuit 22.

The dummy output bias circuit 16 includes a circuit including the current source 201 and the transistor 202, and the same circuit as the Gilbert cell unit described in the first embodiment.
Unlike the current I1 of the current source 1, the current I2 of the current source 201 outputs a constant current that does not vary. The current I1 of the current source 1 changes in relation to the input signal. However, as for the output current I2 of the current source 201, even if the transistors 205 and 208 and the transistors 206 and 207 are switched between CK and XCK, the input current is supplied through the transistor 202, so that the current does not change.

  Further, when the size of each of the transistors 6 and 7 is M = 1, the size of the transistor 202 of the dummy output bias circuit 16 is M = 2. Transistors 209 and 2010 are each set to M = 1. That is, the sizes of the transistors 14 and 15 are also M = 1. In addition, the size and configuration of the Gilbert cell unit having the transistors 8 to 13 and the Gilbert cell unit having the transistors 203 to 208 are the same.

In this way, by connecting the output of the loop filter unit and the output of the circuit that generates the dummy voltage, external components can be reduced, and it is strong against common-mode noise, which is an advantage of the differential input type VCO circuit, and has an input range. Wider than a single connection.
(Example 3)
Next, the dummy output bias circuit 16 that does not depend on manufacturing variations even when manufacturing variations exist will be described. When substantially the same circuit is arranged in the input unit and the Gilbert cell unit described in the second embodiment, the PLL circuit cannot be locked to a desired frequency if there is a manufacturing variation. This is because the output of the dummy output bias circuit 16 has a rectangular ripple waveform due to the offset of the Gilbert cell portion of the dummy output bias circuit 16, and the PLL circuit cannot be locked to a predetermined frequency. That is, when the transistors 205 to 208 (FIG. 2) are switched between CK and XCK, there is usually no manufacturing variation, so that substantially the same constant current flows from each transistor. However, if each transistor has manufacturing variations, each transistor has a different current. As a result, a rectangular ripple waveform results.

  Therefore, the dummy output bias circuit 16 according to the first embodiment includes a current source 301, a transistor (PMOS) 303, and transistors (NMOS) 302 and 304 as shown in FIG. One of the current sources 301 is connected to the power supply voltage (VDD), and the other is connected to the gate and source of the transistor 302. The transistor 304 is also connected to the gate. The source of the transistor 303 is connected to the power supply voltage (VDD). The gate and drain are connected to the drain of transistor 304. The connection point is connected to the gate of the transistor 19. The sources of the transistors 302 and 304 are connected to the ground (GND).

  The output current I1 of the current source 1 is shunted to I1 / 2 in the transistors 6 and 7, respectively. Further, the currents flowing through the transistors 8 and 9 are also I1 / 2. Therefore, the current flowing through the transistor 17 is also I1 / 2. If the current I2 of the current source 301 is the same as I1, the size of the transistor 302 is M = 2, and the size of the transistor 304 is M = 1, I1 / 2 = I2 / 2 supplied to the transistor 19 is obtained. . This shows that the dummy output bias circuit shown in this example may be used.

  In this way, by connecting the output of the loop filter unit and the output of the circuit that generates the dummy voltage, external components can be reduced, and it is strong against common-mode noise, which is an advantage of the differential input type VCO circuit, and has an input range. Can be wider than a single connection. Furthermore, the number of parts in the IC chip can be reduced.

  The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

1 is a diagram illustrating a PLL circuit according to a first embodiment. FIG. 6 is a diagram illustrating a PLL circuit according to a second embodiment. FIG. 10 is a diagram illustrating a PLL circuit according to a third embodiment. It is a figure which shows the conventional PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Current source 2, 3, 18, 20, 21 ... Resistance element 4, 5, 8, 9, 17, 19 ... P channel transistor 6, 7, 10-15 ... N channel transistor 16 ... Dummy output bias circuit 22 ... VCO circuits 23, 24 ... terminal 25 ... first capacitor element 26 ... second capacitor element 201 ... current sources 203, 204 ... P channel transistors 202, 205-2010 ... N channel transistor 301 ... current source 303 ... P channel transistor 302 204-2010 ... N-channel transistors

Claims (3)

A PLL circuit including a differential input type VCO circuit, a loop filter circuit, and a phase detection circuit, and provided in a semiconductor integrated circuit,
The phase detection circuit for supplying a phase detected signal to the differential input type VCO circuit;
Connecting the output of the phase detection circuit and one differential input of the differential input type VCO circuit, the loop filter circuit provided between the output of the phase detection circuit and the ground;
A dummy output bias circuit for supplying substantially the same bias voltage as that of the phase detection circuit to the other differential input of the differential input type VCO circuit;
A PLL circuit provided in a semiconductor integrated circuit. The resistor element constituting the loop filter circuit is built in the semiconductor integrated circuit, and the first capacitor element and the second capacitor element are externally attached,
The resistor element and the first capacitor element are connected in series, and the second capacitor element is connected in parallel with the series-connected circuit between the differential input of the differential input type VCO circuit and a ground. A PLL circuit provided in the semiconductor integrated circuit according to claim 1.   2. The PLL circuit provided in the semiconductor integrated circuit according to claim 1, wherein the phase detection circuit is a Gilbert cell system.

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