JP2007219816A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of performing a onnection control between processors by a standard OS. <P>SOLUTION: This multiprocessor system is provided with: a master processor 31A having an interrupt function; at least one slave processor 31B-31C having the interrupt function; a shared memory 35; and a shared bus 34. A program for making the master and slave execute processing is stored in a shared memory, and the master executes the OS, and transmits thread processing to be executed by the slave to the slave in the form of functions, and the slave loads the thread processing program from the shared memory, and notifies the end of the execution. This multiprocessor system is also provided with an inter-processor connection circuit 32 and a bus arbitration circuit 33. The thread transmission notification in the salve and the thread processing end in the master are operated by using the interrupt function. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system in which one of a plurality of processors operates as a master processor and the remaining processors operate as slave processors.

  2. Description of the Related Art Conventionally, in a computer system, a processing speed is improved by providing a plurality of processors and proceeding in parallel.

  FIG. 1A shows a schematic configuration of a coprocessor type multiprocessor having a main (master) processor 11 constituted by a normal CPU and coprocessors 12A to 12C operating under the control of the master processor 11. FIG. Only the master processor 11 executes the processing of the operating system (OS) stored in the main memory 13, and each of the coprocessors 12A to 12C is not appropriate to be performed by the master processor 11 such as floating point arithmetic or input / output processing. Execute the process. When the master processor 11 causes any of the coprocessors 12 </ b> A to 12 </ b> C to perform processing, the master processor 11 sends a command designating execution of the processing to the corresponding coprocessor via the command / data transfer bus 14. Each coprocessor decodes the command sent on the command / data transfer bus 14 and receives the necessary data. In FIG. 1A, the coprocessors 12A to 12C cannot directly access the main memory 13, but a coprocessor that performs input / output processing or the like can directly access the main memory 13 via the same bus as the master processor. It is configured as follows.

  The processing performed by each coprocessor is fixed, and each coprocessor is configured to execute specific processing at high speed. For example, a coprocessor that performs floating point arithmetic performs only floating point arithmetic processing, and a coprocessor that performs input / output processing performs only input / output processing. A coprocessor has a large amount of processing, but is used for a process that repeats a specific process, so that a processing sequence is often defined by hardware. However, when a coprocessor that executes a complicated process that requires a program is used, a program memory may be provided in each coprocessor. In this case, a non-volatile memory such as a ROM is often used as the program memory. However, a volatile memory such as an SRAM or a DRAM may be used, and the program PG may be loaded from the main memory 13 by a DMA operation when the system starts up. is there. Although the program PG may be loaded from the main memory 13 to the coprocessor via the master processor and the command / data bus 14, it is directly loaded when the coprocessor is directly connected to the main memory 13. . In any case, after the system is started, the program stored in the program memory of the coprocessor is not rewritten.

  The coprocessor that has completed the process specified by the command reports the end of the process to the master processor 11. This process completion report may be made via the command / data bus 14, but as shown, the process completion may be reported to the master processor 11 by an interrupt process.

  As in the conventional example shown in FIG. 1A, a SMP (Symmetric Multi-Processor) in which a plurality of the same processors and a shared memory are combined, instead of combining coprocessors specialized to perform specific processing. ) Type multiprocessor system has also been proposed. FIG. 1B is a diagram showing a schematic configuration of an SMP multiprocessor system.

  All the processors 21 </ b> A to 21 </ b> D have an equivalent relationship, and are connected to the shared memory 23 via the shared bus and bus arbitration circuit 22. The processors 21A to 21D respectively execute programs PG0 to PG3 that are predetermined to be executed by each processor under the OS arranged in the shared memory 23. The contention of access to the shared memory 23 that occurs during execution of the OS and program in each processor is arbitrated by the shared bus and bus arbitration circuit 22, and synchronization and communication between the processors may be part of the OS area in the shared memory 23 or in advance. This is done through a defined shared area. The interrupt function in each processor is used for controlling input / output devices belonging to each processor. Accordingly, the program activation of each processor is performed by an interrupt from the input / output device and a semaphore in a part of the OS area in the shared memory 23 or a predetermined shared area.

  In the configuration shown in FIG. 1B, there is a case where tasks are dynamically allocated according to the addition situation without fixing the program executed by each processor. Further, a configuration in which the configuration of the coprocessor system of FIG. 1A is added to the multiprocessor configuration of FIG.

  The present invention is directed to a configuration as shown in FIG. 1B in which the processing content executed by each processor is not fixed.

U.S. Pat. No. 5,003466 US Pat. No. 5,361,362

  In a conventional multiprocessor system, an operating system (OS) is strongly involved in assigning processes (threads (small programs)) to a plurality of processors. A standard OS widely used in ordinary computer systems is non-multi compatible that does not support multi-processor systems. Therefore, in the conventional multiprocessor system shown in FIG. 1B, it is necessary to use a multi-dedicated OS. However, since the multi-dedicated OS is complicated and large-scale, it is not suitable for mounting on consumer portable information devices.

  In addition, in the conventional multiprocessor system of FIG. 1B, since all the processors need to execute the processing of the OS, the memory size increases and the program is distributed to a plurality of processors and executed. Programming is also required, and software productivity is low.

  In addition, since the multi-compatible OS is not compatible with the standard OS, there is a problem in that existing software for the standard OS cannot be used.

  The present invention has been made in view of the above problems, and is directed to a multiprocessor system in which connection control between processors can be performed for a portable information device for consumer use by a simple standard OS currently widely used. The purpose is realization.

  In the multiprocessor system of the present invention, a plurality of processors as shown in FIG. 1B access a shared memory, and each processor loads an OS and a program stored in the shared memory to perform an operation. This is a multiprocessor system whose processing content is not fixed. In order to achieve the above object, the multiprocessor system of the present invention has one of a plurality of processors operating as a master processor, the other processors operating as slave processors, and only the master processor executes OS processing. Then, the master processor assigns thread processing to the slave processor by a function, and the activation request between the master processor and the slave processor and the notification of the end of processing are performed using the interrupt function of each processor. Thereby, the conventional standard OS can be used as it is.

  That is, the multiprocessor system of the present invention includes a master processor having an interrupt function, at least one slave processor having an interrupt function, a shared memory, the master processor and the at least one slave processor, the shared memory A shared bus for accessing the computer, and a program for executing processing by the master processor and the at least one slave processor is stored in the shared memory, The operating system processing of the processor system is executed by the master processor, and the master processor has a thread processing function including data indicating a thread processing program to be executed by the at least one slave processor. The thread processing function activation request is transmitted to any one of the at least one slave processor. When the at least one slave processor receives the activation request, the thread processing function activation request is stored in the shared memory. Loads a thread processing program to perform processing, notifies the master processor of the end of the thread processing, transmits the start request from the master processor to the at least one slave processor, and the at least one slave An inter-processor connection circuit for notifying the completion of the thread processing from a processor to the master processor, and a bus arbitration circuit for arbitrating when the master processor and the at least one slave processor access the shared memory; And further comprising an interprocessor connection The thread processing function activation request transmission notification from the path to the at least one slave processor is performed using the interrupt function of the at least one slave processor, and the master processor The completion notification of the thread processing is performed using the interrupt function of the master processor.

  According to the present invention, a multiprocessor system can be configured using a standard OS.

  At least one slave processor can reduce power consumption by entering a sleep state after thread processing is completed, that is, when processing is not performed. Further, even in the master processor, the power consumption can be further reduced by waiting for thread processing in the slave processor after assigning the thread to the slave processor, that is, in the sleep state when no processing is performed.

  Since the processing contents of each processor are not fixed and are determined by the OS and the program stored in the shared memory, the master processor and at least one slave processor can have the same configuration or different configurations. However, in actually configuring the system, it is desirable to have the same configuration.

  Since high integration is being promoted, it is possible to provide a master processor and at least one slave processor on a single chip to have a multi-core configuration, and it is also possible to provide a shared memory on the same chip.

  According to the present invention, a multiprocessor system can be realized by using a standard OS that does not have a multi-function, and compatibility with the standard OS can be obtained, and a highly flexible scheduling function can be achieved only by management software in the master processor. Therefore, software productivity does not decrease.

  FIG. 2 is a block diagram showing the overall configuration of the multiprocessor system according to the embodiment of the present invention. As illustrated, the system includes five processors 31 </ b> A to 31 </ b> E, an interprocessor connection circuit 32, a bus arbitration circuit 33, a shared bus 34, and a shared memory 35. Each processor individually has a cache memory or the like, but is not shown here. Of the above components, the portion excluding the shared memory 35 is mounted on one chip, and is a multi-core chip. The shared memory 35 can be provided in the same chip. Conversely, any combination of the processors 31A to 31E, the processor connection circuit 32, and the bus arbitration circuit 33 can be mounted on a plurality of chips. .

  The processors 31A to 31E all have the same configuration and the same configuration as a normal microprocessor, and buses (address bus and data bus) 0 to 4 connected to the shared memory 35 via the shared bus 34, Bus control 0-4 (breq0-4, back0-4), interrupt signals (ireq0-4, iack0-4), peripheral devices, etc., which are signals for these buses to acquire the exclusive right of the shared bus 34 And a connection bus (ibus 0 to 4).

  One of the processors 31A to 31E (here, the processor 31A) operates as a master processor, and the other processors (here, the processors 31B to 31E) operate as slave processors. The master processor 31A activates thread (small program) processing to the slave processor groups 31B to 31E via the inter-processor connection circuit 32. When the thread processing ends, the slave processor groups 31B to 31E notify the master processor 31A of the end of the corresponding thread via the inter-processor connection circuit 32. During this time, the operating one of the processors 31A to 31E accesses the shared memory 35 via the shared bus 34 based on the arbitration of the bus arbitration circuit 33. Although thread processing can be assigned to a plurality of slave processors at the same time, in order to simplify the explanation, it will be described below that thread processing is assigned to the slave processor 31B.

  The master processor 31A sends desired data to the inter-processor connection circuit 32 via the connection bus ibus0, and the inter-processor connection circuit 32 converts this data into interrupt signals ireq1 to 4 (here, ireq1) and corresponds. The slave processor 31B is activated. The slave processor 31B that has received the interrupt signal notifies the master processor 31A of reception of activation from the master processor 31A via the inter-processor connection circuit 32 by the interrupt signal response signal iack1. Next, the slave processor 31B starts interrupt processing, reads information (program, data) related to thread processing to be executed from a predetermined address on the shared memory 35, and executes the assigned thread processing using this information. To do.

  Next, when the slave processor 31B finishes executing the thread processing, the slave processor 31B sends out certain data to the interprocessor connection circuit 32 via the connection bus ibus1, and the interprocessor connection circuit 32 interrupts this data. The signal is converted into the signal ireq0, and the master processor 31A is interrupted. Receiving this interrupt signal, the master processor 31A notifies the slave processor 31B of the completion reception in the master processor 31A via the inter-processor connection circuit 32 by the interrupt (reception response) signal iac0. Next, the master processor 31A performs an end process, for example, the start of the next thread process. Here, the case where thread processing is assigned to the slave processor 31B has been described as an example. However, when thread processing is assigned to the other slave processors 31C to 31E, the connection buses ibus 2 to 4 included in the respective slave processors are used. Process.

  During this time, the master processor 31A and the slave processors 31B to 31E, except for those waiting, share the shared bus occupation right via the bus arbitration circuit 34 by the bus control signals 0 to 4 (breq0 to 4, back0 to 4). In response to the arbitration, the buses 0 to 4 are connected to the shared bus 34 and sequentially access the shared memory 35 as necessary.

  FIG. 3 is a diagram illustrating the configuration of the master processor 31A in the embodiment. As illustrated, the master processor 31A includes an arithmetic unit 41, an address conversion unit 42, a cache memory 43, a memory interface 44, and a control unit 45 that controls the above components. Based on the control of the control unit 45, the address of the instruction word to be executed by the program counter in the arithmetic unit 41 is sent to the address conversion unit 42 and converted into a physical address. If there is an instruction word corresponding to this physical address in the cache memory 43, the instruction word is read from the cache memory 43 and stored in the instruction register in the control unit 45 via the data port and instruction port of the arithmetic unit 41. The The control unit 45 controls components such as the arithmetic unit 41 according to the contents of the instruction register. In this process, if there is no corresponding instruction word in the cache memory, the shared memory 35 is accessed by the address bus via the memory interface 44, and the portion including this instruction word is transferred to the cache memory 43 through the data bus. Load it. In this case, loading is performed after securing the bus occupation right of the shared bus 34 connected to the shared memory 35 by the bus control 0 signal.

  Further, the peripheral bus ibus0 from the arithmetic unit 41 is used for data setting for starting the slave processors 31B to 31E and ending the assigned thread.

  In addition, there are a plurality of interrupt terminals in the master processor 31A so that interrupts from a plurality of external devices such as an interrupt signal 0 and an interrupt signal N can be received. The interrupt signal 0 shown here is a slave processor 31B. Used to receive a thread processing end report from ~ 31E. Other interrupt signals N can be used, for example, for a connected coprocessor as shown in FIG.

  FIG. 4 is a diagram showing the configuration of the slave processor (B) 31B in the embodiment, and the other slave processors 31C to 31E have the same configuration, and the configuration is also the configuration of the master processor 31A shown in FIG. The same.

  As illustrated, the slave processor 31B includes an arithmetic unit 51, an address conversion unit 52, a cache memory 53, a memory interface 54, and a control unit 55 that controls the above components. Based on the control of the control unit 55, the address of the instruction word to be executed by the program counter in the arithmetic unit 51 is sent to the address conversion unit 52 and converted into a physical address. If the instruction word corresponding to the physical address is in the cache memory 53, the instruction word is read from the cache memory 53 and stored in the instruction register in the control unit 55 via the data port and instruction port of the arithmetic unit 51. The The control unit 55 controls components such as the arithmetic unit 51 in accordance with the contents of the instruction register. In this process, if there is no corresponding instruction word in the cache memory, the shared memory 35 is accessed by the address bus via the memory interface 54, and the portion including this instruction word is transferred to the cache memory 53 through the data bus. Load it. In this case, loading is performed after securing the bus occupation right of the shared bus 34 connected to the shared memory 35 by the bus control 1 signal.

  The peripheral bus ibus1 from the arithmetic unit 51 is used for data setting for generating an interrupt for notifying the master processor 31A of the end of the thread.

  Further, the interrupt terminal in the slave processor 31B does not need to accept an interrupt from an external device, and only the interrupt signal 1 is used to receive the start of thread processing from the master processor 31A. Furthermore, if the thread processing executed by the slave processor 31B is limited to the physical address space, the address translation unit 42 becomes unnecessary.

  FIG. 5 is a block diagram of the inter-processor connection circuit 32 in the embodiment, FIG. 6 is a block diagram of the master interrupt circuit 61 that constitutes the inter-processor connection circuit 32, and FIG. 7 is a startup process that constitutes the master interrupt circuit 61. FIG. 8 is a configuration diagram of the circuit 63, FIG. 8 is a configuration diagram of the termination processing circuit 64 that configures the master interrupt circuit 61, and FIG. 9 is a configuration diagram of the slave interrupt circuit 62 that configures the inter-processor connection circuit 32. The inter-processor connection circuit 32 will be described with reference to FIGS.

  As shown in FIG. 5, the inter-processor connection circuit 32 includes a master interrupt circuit 61 connected to the master processor 31A and slave interrupt circuits 62B to 62E connected to the slave processors 31B to 31E, respectively. In this configuration, since only four signal lines are required for connection between processors, the number of wirings is not increased.

  The operation of each circuit will be described separately when the master processor starts thread processing to the slave processor and when thread processing from the slave processor to the master processor ends. The start / end of thread processing can be performed for a plurality of slave processors among the four slave processors. Here, for simplicity of explanation, it is assumed that thread processing is assigned to the slave processor 31B. .

  First, the operation at the time of thread activation will be described. The master processor 31A sends desired data (data assigned by the thread processing to the slave processor 31B) to the master interrupt circuit 34 via the peripheral bus ibus0. In response to this, the master interrupt circuit 34 sends an activation interrupt signal ireq1 to the slave processor 31B. When the slave processor 31B receives the activation interrupt signal ireq1, the slave processor 31B starts an interrupt process, and a signal iack1 for notifying the master processor 31A of acceptance of the activation interrupt signal ireq1 is transmitted to the master interrupt circuit 61. The master processor 31A reads the reception of the signal iack1 in the master interrupt circuit 61 through ibus0, thereby confirming that the activation of the thread processing in the slave processor 31B has been received.

  On the other hand, the slave processor 31B sends the signal iack1 to the master interrupt circuit 61, reads information (program and data) necessary for thread processing to be executed from a predetermined address in the shared memory 35, and loads it into the cache memory 53. To do. If necessary information is already loaded in the cache memory 53 (for example, in the same case as previously used), this operation is unnecessary. Then, thread processing is executed based on the loaded information. If further programs or data are needed during execution, the shared memory 35 is accessed and obtained as appropriate, and the processing results are stored in the cache memory 53. When processing is completed or when it becomes necessary to output during processing, The shared memory 35 is accessed and output.

  Next, the operation at the end of thread processing will be described. When the assigned thread processing is completed, the slave processor 31B sends certain data for generating an interrupt to the master processor 31A to the slave interrupt circuit 62B via the peripheral bus ibus1. The slave interrupt circuit 62B sends an end interrupt signal ireq1 to the master interrupt circuit 61 according to this data. When receiving the end interrupt signal ireq1, the master interrupt circuit 61 sends an interrupt signal ireq0 to the master processor 31A. The master processor 31A starts interrupt processing in response to the interrupt signal ireq0, checks the register of the master interrupt circuit 61 via the bus ibus0, and knows that the thread processing of the slave processor 31B has ended. Then, the master processor 31A sends an interrupt reception signal iack0 to the master interrupt circuit 61. In response to this, the master interrupt circuit 61 sends a signal iack1 to the corresponding slave interrupt circuit 62B. The slave processor 31B reads this via ibus1 to know that the notification of the end of the thread processing to the master processor 31A has succeeded. On the other hand, the master processor 31A starts the process for terminating the thread after sending out the interrupt reception signal iack0.

  As shown in FIG. 6, the master interrupt circuit 61 includes a start processing circuit 63 shown in FIG. 7 and an end processing circuit 64 shown in FIG.

  As shown in FIG. 7, the activation processing circuit 63 includes an activation request register 65 and an activation completion register 66. These registers are 8 bits, and there are 4 slave processors, so the lower 4 bits are used. The number of bits used can be increased to the bit width of ibus0 according to the number of slave processors. If there is a need for further increase, a plurality of registers can be arranged. Therefore, in this embodiment, the configuration is one master processor and four slave processors. However, for example, it is possible to receive 255 or more slave processors.

  In the activation processing circuit 63 of FIG. 7, the master processor 31A activates desired data with “1” set in the bit position corresponding to the slave processor (any one of 31B to 31E) to be activated via the bus ibus0. Write to request register 65. For example, when only the slave processor 31B is activated, “00000001” is written as 8-bit data, and when all slave processors are activated, “000011111” is written as 8-bit data. The upper 4 bits are set to “0000” because there is no corresponding slave processor.

  When only the slave processor 31B is activated by the write operation as described above, only the corresponding signal ireq1 among the activation interrupt signals becomes “1” and is sent to the slave processor 31B as an interrupt signal. When the slave processor 31B receives the signal ireq1, the slave processor 31B starts the activation process and sends a response signal iack1 to the activation request. This response signal iack1 is read into the activation completion register 66, and the master processor 31A reads it through ibus0. Since the contents of this register is “00000001”, it indicates that the activation to the slave processor 31B was successful. know.

  Note that the contents of the activation request register 65 are reset at an appropriate timing because it is necessary to comply with the interrupt interface specification of the master processor 31A.

  As shown in FIG. 8, the end processing circuit 64 includes an end report register 67 and an end completion register 68. These registers have an 8-bit configuration, and the lower 4 bits are used, but any bit width can be used as in the activation processing circuit.

  In the termination processing circuit 64 of FIG. 8, slave interrupt circuits 62B to 62E attached to the slave processors 31B to 31E send signals irq1 to 4 indicating the termination of the thread processing to the termination report register 67. The signals irq1 to irq4 are further input to the OR circuit 69, and an interrupt signal ireq0 is sent to the master processor 31A accordingly. With this interrupt, the master processor 31A enters an interrupt operation and reads the contents of the end report register 67 via ibus0. For example, when only the slave processor 31B notifies the end, “00000001” is read as 8-bit data, and when all the slave processors notify the end, “00001111” is displayed as the 8-bit data. Is read. The upper 4 bits are set to “0000” because there is no corresponding slave processor.

  In the case of an end notification of only the slave processor 31B, only the corresponding signal irq1 among the end interrupt signals becomes “1” by the read operation as described above, and is sent to the master processor 31A as an interrupt signal. When the master processor 31A receives the signal ireq0, the master processor 31A starts an end process, sends a reply signal iack0 to the interrupt, and writes “00000001” to the end completion register 68 via the ibus0. The response signal iak1 to irq1 is sent to the corresponding slave processors 31B to 31E by the output of the end completion register 68 and the AND circuits 70B to 70E. Thus, the slave processor 31B knows that the thread end notification has been correctly received by the master processor 31A.

  Note that the contents of the termination request register 67 are reset at an appropriate timing because it is necessary to comply with the interrupt interface specification of the master processor 31A.

  As shown in FIG. 9, the slave interrupt circuit 62 includes an end report register 71 and an acceptance completion register 72. These registers have an 8-bit configuration and show an example in which the lower 1 bit is used.

  When the thread processing ends, the slave processors 31B to 31E notify the master processor 31A of the end, and the master processor 31A needs to enter the end processing. Since the slave processors 31B to 31E perform the same operation independently, a case where the end notification is given from the slave processor 31B will be described below.

  First, the slave processor 31B writes “00000001” to the end report register 71 via ibus1. As a result, the end interrupt signal irq1 is sent to the master interrupt circuit 61. Since the subsequent operations of the master interrupt circuit 61 and the master processor 31A have already been described, they are omitted here. When the completion report is accepted by the master processor 31A, an acceptance response signal iak1 is sent to the slave interrupt circuit 62 via the master interrupt circuit 61, and the slave interrupt circuit 62 sends this signal to the least significant bit of the acceptance completion register 72 as “1”. "Is set.

  The slave processor 31B reads the reception completion register 72 through ibus1, and if the content is “00000001”, the slave processor 31B knows whether a response signal iaak1 to the end notification signal irq1 has been returned. Thereby, the slave processor 31B knows that the thread end notification has been correctly received by the master processor 31A.

As described above, if the master processor 31A and the slave processors 31B to 31E have the above-described configuration, a desired multiprocessor function can be achieved by adding an interprocessor connection circuit thereto. Therefore, the master processor 31A and the slave processors 31B to 31E and the slave processors 31B to 31E can be operated in the same manner even when the instruction systems are different.
This is the end of the description of the inter-processor connection circuit 32. Next, the bus arbitration circuit 33 will be described.

  FIG. 10A is a diagram illustrating a configuration of the bus arbitration circuit 33 according to the embodiment. This circuit arbitrates bus occupancy between the bus control signals 0 to 4 from the master processor 31A and the four slave processors 31B to 31E.

  The bus arbitration circuit 33 performs arbitration based on an arbitration method called a round robin method, but is not limited to this. Since the bus arbitration circuit 33 always accepts the signals breq0 to breq4 requesting the occupation of the shared bus 34, the five flip-flops (FF00-40) 81A to 81E triggered by the clock signal clk0 and the priority of the bus occupation right 5 for giving an occupancy right when the output of a set of five FFs (FF01-41) 82A to 82E and two corresponding FFs of FF81A to 81E and FF82A to 82E is "1" Each AND circuit 83A-83E is comprised. As for the input / output terminals of the ten flip-flops (FFij), terminals other than the illustrated S and R terminals of the FFs 82A to 82E are shown in FIG.

  When the multiprocessor system of the embodiment starts up by turning on the power, the reset signal is input to the S (set) terminal to set “1” to the FF 82A, and R (to set “0” to the FFs 82B to 82E. Input to the (Reset) terminal. As a result, immediately after the start of the multiprocessor system, the master processor 31A has the highest priority bus occupation right. In this state, when the bus request signal breq0 is sent from the master processor 31A, the output of the FF 81A becomes “1”, and the output of the FF 82A is already “1”, so the AND circuit 83A causes the bus occupation permission signal back0. Becomes “1”, and the master processor 31 A occupies the shared bus 34. The master processor 31A occupies the shared bus 34 when the bus 0 (address bus, data bus) is activated by a bus drive signal sent from the control unit 45 of FIG. 3 to the memory interface 44.

  During this time, there is a bus request signal from the slave processors 31B to 31E, and even if the outputs of the FFs 81B to 81E are “1”, the outputs of the FFs 82B to 82E are “0”, so the AND circuits 83B to 83E occupy the bus. The permission signals back1 to back4 are “0”, and the buses 1 to 4 are not active in the slave processors 31B to 31E, so that the slave processors 31B to 31E are disconnected from the shared bus 34.

  When the master processor 31A occupies the bus, the clock clkm triggers the FFs 82A to 82E, the output of the FF 82A becomes the input of the FF 82B, the output of the previous FF becomes the input of the subsequent FF, and the output of the FF 82E becomes FF 82A. Therefore, the output of the FF 82B becomes “1”, the output of the FF 82A becomes “0”, and the bus occupation priority shifts to the FF 82B, that is, the slave processor 31B. In this way, each time the shared bus 34 is occupied, the priority is transferred to the adjacent unoccupied processor, so that the shared bus can be evenly shared among the processors.

  Although not shown, when the processor adjacent to the processor having the bus occupation right does not request the occupation of the shared bus, a method of transferring the occupation right to the processor adjacent to the processor is taken. There is also. Various modifications such as a method of assigning priority in the order in which bus occupancy is requested using FIFO (First In First Out) and a method of managing priority by the master processor are also possible.

  FIG. 11 is a diagram for explaining the software operation in the multiprocessor of this embodiment in relation to access to each unit.

  First, when thread processing is requested to any of the slave processors 31B to 31E while the main program in the application program is being executed by the master processor 31A, (1) it is executed by a function call. When a function call occurs, (2) control is transferred to the OS (operating system), and (3) control is transferred to a master management program that manages the idle state of the slave processor and the like together with function processing. Thereafter, one of the slave processors 31B to 31E is selected, and (4) the slave processor 31B is activated by the inter-processor connection circuit 32, for example. At this point, the master processor 31A can continue the main program of the application program.

  The slave processor 31B executes the slave management program, and (5) reads the thread activation information and (6) executes the thread #n corresponding to the read activation information.

  Next, when the thread #n is terminated, the execution result data is written in a predetermined location assigned to each thread in the shared memory 35. When this is completed, the process returns to (7) the slave management program, and (8) this Execution of the program passes control to the master management program through the inter-processor connection circuit. The master management program performs a procedure for releasing the terminated slave processor 31B. The thread execution result in the slave processor 31B is read from the predetermined location in the shared memory 35 at the time specified in the main program and used. When a plurality of thread processes are executed, the execution results of the respective thread processes may be read and processed after all the thread processes are completed.

  FIG. 12 is a diagram illustrating thread processing assignment from the master processor 31A to the slave processors 31B and 31C in the multiprocessor system according to the embodiment. Here, it is assumed that the slave processors 31B and 31C are in an empty state, and the slave processors 31D and 31E are already executing other thread processes.

  FIG. 12A shows a state in which one application task (program A) programmed in C language and a plurality of thread processes 1 to 4 in the program are allocated to the slave processors 31B to 31E. FIG. 12B shows a slave management table showing slave processor management by the master management software shown in FIG.

  When the master processor 31A executes the function thread create () in the program, for function processing, the master processor 31A first links to the OS, and in the course of executing the function thread create (), slave management under the management of the master management software. Using the table, thread processing is assigned to the slave processors 31B to 31E as follows. It is assumed that the slave management table indicates an empty state when “0” and indicates that it is operating when “1”. The slave management table is initialized by writing “0” to the corresponding memory address when the multiprocessor system starts up.

(1) Initial state of slave management table In the initial state, it is assumed that both the slave processors 31B and 31C are empty and the slave processors 31D and 31E are already executing other thread processes. When the free state is “0”, the task number and thread number are meaningless, so “−” is shown in the table.

(2) Allocation of thread 1 When the slave processors 31B and 31D are found to be free, the master management software secures the slave processor 31B and writes “1” to the corresponding memory address indicating the free state. Furthermore, the task number of the thread 1 to be allocated (assuming “5”) and the thread number “1” are written in the corresponding memory address, and the activation interrupt is applied to the slave processor 31B as described above. As a result, the slave management table changes as shown in FIG.

(3) Allocation of thread 2 As in (2), in order to allocate thread 2 to the slave processor 31C, “1” is written in the idle state, “5” is written in the task number, and “2” is written in the thread number. A start interrupt. Thereafter, since there is no free space in the slave processor, the master processor 31A waits for the thread processing of the thread number 3 or more until one of the operating slave processors 31B to 31E finishes the thread processing being executed. . As a result, the slave management table changes as shown in FIG. In this state, when the master processor 31A does not require other processing, the master processor 31A can be put in the sleep state.

(4) Thread end processing When thread processing ends in one of the slave processors, the slave processor generates a thread end interrupt and enters a sleep state. Due to the thread end interrupt from the slave processor, the master processor 31A writes “0” in the free state portion of the corresponding processor in the slave management table, and if there is a waiting thread process (here thread 3), (2) Or, in the same manner as in (3), the thread 3 in the waiting state is allocated.

  As described above, the multiprocessor system of the present invention can be easily configured using a standard processor and a standard OS, and the processing speed can be improved.

  Although the multiprocessor system of this embodiment has been described above, it goes without saying that various modifications can be made.

  The present invention can be applied to a multiprocessor system, and is particularly suitable for application to a small device using a multicore chip in which a plurality of processors are mounted on one chip.

It is a figure which shows schematic structure of the prior art example of a multiprocessor system. 1 is a diagram showing an overall configuration of a multiprocessor system according to an embodiment of the present invention. It is a figure which shows the structure of the master processor in the multiprocessor system of an Example. It is a figure which shows the structure of the slave processor in the multiprocessor system of an Example. It is a figure which shows the structure of the connection circuit between processors in the multiprocessor system of an Example. It is a figure which shows the structure of the master interruption circuit in the inter-processor connection circuit of the multiprocessor system of an Example. It is a figure which shows the structure of the starting process circuit in the master interruption circuit of an Example. It is a figure which shows the structure of the completion | finish processing circuit in the master interruption circuit of an Example. It is a figure which shows the structure of the slave interrupt circuit in the inter-processor connection circuit of the multiprocessor system of an Example. It is a figure which shows the structure of the bus arbitration circuit of the multiprocessor system of an Example. It is a figure explaining the software operation linked | related with the memory access in the multiprocessor system of an Example. It is a figure explaining the allocation operation | movement of the thread process in the multiprocessor system of an Example.

Explanation of symbols

31A Master processor 31B to 31E Slave processor 32 Inter-processor connection circuit 33 Bus arbitration circuit 34 Shared bus 35 Shared memory

Claims (7)

A master processor having an interrupt function;
At least one slave processor having an interrupt function;
Shared memory,
A multiprocessor system, wherein the master processor and the at least one slave processor include a shared bus for accessing the shared memory,
A program for the master processor and the at least one slave processor to execute processing is stored in the shared memory,
The operating system process of the multiprocessor system is executed by the master processor,
The master processor generates a thread processing function indicating a thread processing program to be executed by the at least one slave processor, and sends a start request for executing the thread processing function to any one of the at least one slave processor. To
Upon receiving the activation request, the at least one slave processor loads the thread processing program stored in the shared memory to perform processing, notifies the master processor of the end of the thread processing,
An inter-processor connection circuit that transmits the start request from the master processor to the at least one slave processor, and notifies the end of the thread processing from the at least one slave processor to the master processor;
A bus arbitration circuit that performs arbitration when the master processor and the at least one slave processor access the shared memory;
The transmission notification of the activation request from the inter-processor connection circuit to the at least one slave processor is performed using the interrupt function of the at least one slave processor,
The multiprocessor system, wherein the end notification of the thread processing from the inter-processor connection circuit to the master processor is performed using the interrupt function of the master processor.   The multiprocessor system according to claim 1, wherein the at least one slave processor enters a sleep state after the thread processing is completed.   2. The multiprocessor system according to claim 1, wherein the master processor enters a sleep state when the master processor is in a waiting state until the thread processing is completed after the activation request.   The multiprocessor system according to claim 1, wherein the master processor and the at least one slave processor have the same configuration.   The multiprocessor system according to claim 1, wherein the master processor and the at least one slave processor have different configurations.   The multiprocessor system according to claim 1, wherein the master processor and the at least one slave processor are provided in one chip.   The multiprocessor system according to claim 6, wherein the shared memory is also provided in the one chip.

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