JP2007233270A - Organic el display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent display unevenness due to variation in parasitic capacity of each pixel circuit. <P>SOLUTION: Pixel circuits of the same colors even in different rows are made qual in area of an overlap part between a semiconductor layer SCL1 and a power line PVDD. Further, the pixel circuits of the same color even in different rows are made equal in area of an overlap part between a gate 24g of a driving TFT 24 and the power line PVDD. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an organic EL display panel in which each pixel includes a pixel circuit including a plurality of transistors and the pixels are arranged in a matrix, and more particularly to a layout of the transistors.

  An EL display device using an electroluminescence (hereinafter referred to as EL) element, which is a self-luminous element, as a light-emitting element for each pixel is advantageous in that it is self-luminous and thin and consumes less power. It attracts attention as a display device that replaces a display device such as a device (LCD) or CRT.

  In particular, an active matrix EL display device in which a switching element such as a thin film transistor (TFT) for individually controlling an EL element is provided in each pixel and the EL element is controlled for each pixel enables high-definition display.

  In this active matrix EL display device, a plurality of gate lines extend in a row (horizontal) direction on a substrate, a plurality of data lines and a power supply line extend in a column (vertical) direction, and each pixel is an organic EL. An element, a selection TFT, a driving TFT, and a storage capacitor are provided. The selection TFT is turned on by selecting the gate line, the data voltage (voltage video signal) on the data line is charged to the holding capacitor, and the driving TFT is turned on with this voltage, and the power from the power supply line is supplied to the organic EL element. Supply.

  However, in such a pixel circuit, if the threshold voltage of the driving TFTs of the pixel circuits arranged in a matrix varies, there is a problem that the luminance varies and the display quality deteriorates. It is difficult to make the characteristics of the TFTs constituting the pixel circuit of the entire display panel the same, and it is difficult to prevent the on / off threshold value from varying.

  Therefore, it is desirable to prevent the influence on the display of the variation in threshold value in the driving TFT.

  Here, various proposals have conventionally been made for a circuit for preventing the influence on the fluctuation of the threshold value of the TFT (for example, Patent Document 1 below).

Special table 2002-514320 gazette

  However, this proposal requires a circuit for compensating for threshold fluctuation, and the data voltage on the data line is applied to the gate of the driving TFT via the capacitor. Therefore, the voltage set at the gate of the driving TFT is likely to be affected by the parasitic capacitance in the path for applying the data voltage.

  In addition, the display has a stripe type in which each pixel is arranged linearly in the vertical scanning direction, and a delta type in which each pixel is slightly shifted in the horizontal scanning direction in the vertical scanning direction. It is said that the delta type is preferable for the display.

  On the other hand, in the case of this delta type, the data line extending in the vertical scanning direction and the power supply line cannot be made straight, and are shifted in the horizontal scanning direction for each row. For this reason, the detailed layout may be different between each row, particularly even rows and odd rows, and the parasitic capacitances on the path to the gate of the data voltage driving TFT are different between even rows and odd rows. There is a problem that display unevenness occurs.

  The present invention is an organic EL display panel having a pixel circuit including a plurality of transistors in each pixel, and arranging the pixels in a matrix. Each pixel includes an organic EL element and an organic power supply line. A drive transistor that controls the amount of current supplied to the EL element, a selection transistor that controls whether a data signal from the data line is supplied to the gate of the drive transistor via a capacitor, and the gate and drain of the drive transistor are short-circuited. A short-circuit transistor that controls whether or not to perform, and a drive control transistor that controls whether or not current from the drive transistor disposed between the drive transistor and the organic EL element is supplied to the organic EL element, and an even number The arrangement of transistors in each pixel is different between a row and an odd row, but an even row pixel and an odd row pixel, In the color pixel, the area where the semiconductor layer connected from the selection transistor to the capacitor intersects the power supply line is substantially the same, and the parasitic capacitance generated here is the same between the same color pixels in each row. It is characterized by being set.

  Each pixel has a pixel circuit including a plurality of transistors, and the pixels are arranged in a matrix. Each pixel includes one organic EL element and an organic EL element from a power supply line. A short circuit between the drive transistor that controls the amount of current supplied to the gate, the selection transistor that controls whether or not the data signal from the data line is supplied to the gate of the drive transistor via the capacitor, and the gate drain of the drive transistor A short-circuit transistor that controls whether or not, and a drive control transistor that controls whether or not a current from a drive transistor disposed between the drive transistor and the organic EL element is supplied to the organic EL element, and even rows, The arrangement of transistors in each pixel is different between the odd-numbered rows, but the pixels of the even-numbered rows and the odd-numbered rows have the same color. In the pixel, wherein the parasitic capacitance between the control terminal and the power supply line of the driving transistor is set to be the same between the same color pixels in each row.

  In the present invention, regarding the path from the data line to the gate of the driving TFT of the data voltage, the parasitic capacitance is the same for the even and odd rows and the same color, and the even and odd rows are displayed differently. Can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a pixel circuit of one pixel according to the embodiment. The drain of the n-channel selection TFT 20 is connected to the data line DL extending in the vertical scanning direction. The gate of the selection TFT 20 is connected to the gate line GL extending in the horizontal scanning direction, and the source is connected to one end of the capacitor 22. The other end of the capacitor 22 is connected to the gate of the p-channel driving TFT 24. Furthermore, the drain of the n-channel reset control TFT 26 is connected to the connection portion of the selection TFT 20 and the capacitor 22, and the source of the reset control TFT 26 is connected to the power supply line PVDD extending in the vertical scanning direction. . Further, the source of the n-channel short-circuit TFT 28 is connected to the gate of the driving TFT 24. The drain of the driving TFT 24 is connected to the drain of the short-circuit TFT 28 via a diode 40. The gates of the reset control TFT 26 and the short-circuit TFT 28 are connected to the control line RST1.

  The source of the drive TFT 24 is connected to the power supply line PVDD, and the drain is connected to the drain of the n-channel drive control TFT 30 via the diode 40. Here, the drive TFT 24 and the drive control TFT 30 are configured using one continuous semiconductor layer, and the drain of the drive TFT 24 is doped with a p-type impurity, while the drain of the drive control TFT 30 is n A type impurity is doped. The diode 40 is generated by a pn junction in this continuous semiconductor layer. Here, as shown in the figure, by disposing the diode 40 on the drive TFT 24 side from the connection portion with the short-circuit TFT 28, the current from the short-circuit TFT 28 to the drive control TFT 30 is not blocked, and the gate voltage of the drive TFT 24 is prevented. Can be reset without problems. If the drive TFT 24 and the drive control TFT 30 are configured using separate semiconductor layers and a metal layer is used for the connection, the diode 40 can be omitted. In this case, contact with the metal layer is required. This is shown in FIGS. 10 and 11 to be described later.

  The source of the drive control TFT 30 is connected to the anode of the organic EL element 32, and the gate is connected to a control line RST2 extending in the horizontal scanning direction. The cathode of the organic EL element 32 is connected to a cathode power source CV. Here, in the normal case, the cathode of the organic EL element 32 is common to all pixels, and this cathode is connected to a cathode power source CV having a predetermined potential.

  Next, the operation of this pixel circuit will be described with reference to FIG. The gate line GL becomes High level only during the selection period of 1H (horizontal period) in which pixels of the corresponding horizontal line (row) are selected. In the figure, a gate line GL (−1) is a gate line for the horizontal line one level above the corresponding horizontal line, and becomes High level at the timing 1H before. When GL (−1) becomes High level, the control line RST1 becomes High level at the same time. Due to the high level of the control line RST1, the reset control TFT 26 and the short-circuit TFT 28 are turned on while the selection TFT 20 is turned off and the drive control TFT 30 is turned on, and a predetermined current flows through the organic EL element 32. As a result, the drain 22 and the source of the driving TFT 24 are short-circuited while the selection TFT 20 side of the capacitor 22 is at the power supply voltage PVDD, and charges are extracted from the gate of the driving TFT 24 and reset.

  Next, the control line RST2 becomes low level with a delay of a predetermined short period Δ, and the drive control TFT 30 is turned off. On the other hand, since the reset control TFT 26 and the short-circuit TFT 28 are on, the gate and drain of the drive TFT 24 are short-circuited while the opposite side of the capacitor 22 connected to the gate of the drive TFT 24 is maintained at the potential of PVDD. Shorted by the TFT 28, the driving TFT 24 is diode-connected. Therefore, the gate potential of the driving TFT 24 becomes a voltage lower than the PVDD by the threshold voltage VF, and this threshold voltage VF is held in the capacitor 22.

  In this way, the threshold voltage VF of the drive TFT 24 is charged in the capacitor 22 in the horizontal period before 1H. Next, the control line RST1 becomes a low level, and the reset control TFT 26 and the short-circuit TFT 28 are turned off. Here, the control line RST2 is maintained at the Low level, and the drive control TFT 30 is kept off.

  Next, in the selection period of the corresponding horizontal line, the gate line GL becomes High level, and thereby the selection TFT 20 is turned on. In this state, the horizontal driver sequentially supplies the video signal of each pixel supplied from the data line DL to each data line DL. Accordingly, a video signal is set for the corresponding pixel in the data line DL. The data line DL maintains the potential of the video signal until the gate line GL becomes a low level. For this purpose, it is preferable to connect a capacitor or the like to the data line DL so that the potential can be maintained.

  When the data line DL is set to the video signal potential, the gate potential of the driving TFT 24, which is the other end of the capacitor 22, is shifted by the video signal voltage (data voltage). Then, the control line RST2 becomes High level, the drive control TFT 30 is turned on, a current corresponding to the gate potential flows through the drive TFT 24, and this flows into the organic EL element 32 via the drive control TFT 30. Even after the gate line GL returns to the low level and the selection TFT 20 is turned off, the gate potential of the driving TFT 24 is maintained at the current voltage, and a current corresponding to the voltage of the video signal flows through the organic EL element 32. Emits light.

  Then, after returning the gate line GL to the Low level, the data line DL is once returned to a constant potential (for example, PVDD). As a result, there is no problem in setting the next video signal to the data line DL.

  As described above, in this embodiment, first, a voltage lower than the PVDD by the threshold voltage VF of the driving TFT 24 is set at the gate of the driving TFT 24, and this is held in the capacitor 22. Therefore, even if the threshold voltage VF varies between the driving TFTs 24 of each pixel, this can be compensated for and a current corresponding to the video signal can be supplied to the organic EL element 32.

  In particular, the voltage on the selection TFT 20 side of the capacitor 22 is set to a constant potential (PVDD in this example) by the reset control TFT 26. Therefore, the influence of the write data in the previous frame is eliminated, and the voltage corresponding to the threshold voltage VF of the drive TFT 24 can be reliably held in the capacitor 22 when the short-circuit TFT 28 is turned on. Further, when the threshold voltage VF is set, it is not necessary to change the voltage of the data line DL, and the operation of the horizontal driver is simplified. Further, if the corresponding gate line GL is in the low level period, the gate voltage of the driving TFT 24 can be reset at any timing, and the reset time can be lengthened and the threshold voltage can be reliably set. .

  Further, the reset control TFT 26 and the short-circuit TFT 28 are simultaneously turned on while the drive control TFT 30 is on. For this reason, the gate voltage of the driving TFT 24 can be reliably reset.

  In this embodiment, the drive control TFT 30 is turned on by setting the control line RST2 to the high level in a state where the gate line GL is at the high level and the selection TFT 20 is turned on. When the drive control TFT 30 is turned on, a current starts to flow through the organic EL element 32, the drain voltage of the drive TFT 24 is lowered, and the gate voltage is likely to be lowered due to this influence. In the present embodiment, when the drive control TFT 30 is turned on, the selection TFT 20 is turned on, and one end of the capacitor 22 is connected to the data line DL. Therefore, even if the gate voltage of the drive TFT 24 changes due to the drive control TFT 30 being turned on, the gate voltage is set to a voltage lower than the data voltage by the threshold voltage VF of the drive TFT 24, and the organic voltage corresponding to the data voltage is set. Light emission of the EL element 32 can be achieved.

  In addition, when the drive control TFT 30 is a p-channel, a leak current is likely to occur, and the gate voltage is lowered when the short-circuit TFT 28 is turned on between the gate and drain of the drive TFT 24 to set the gate voltage of the drive TFT 24 to PVDD-VF. Tend. By setting the drive control TFT 30 to the n-channel, the leakage current is reduced and the gate voltage of the drive TFT 24 can be set accurately.

  In this embodiment, PVDD is set to less than 5V, and the black level voltage of the data voltage set on the data line DL is set to a voltage about 2V higher than PVDD. As a result, the black level can be achieved by setting the gate of the drive TFT 24 to a sufficiently high voltage with respect to the source voltage PVDD when the black level is reached, preventing current from flowing.

"Layout"
As described above, in the pixel circuit of this embodiment, disposing the power supply line PVDD and the data line DL for each column in the vertical scanning direction is the same as that without threshold compensation. On the other hand, each row in the horizontal scanning direction has control lines RST1 and RST2 and two control lines in addition to the gate line GL. Therefore, the position of the control lines RST1 and RST2 with respect to other elements is a problem.

  FIG. 3 shows an example of a layout (planar configuration) in a panel employing such a pixel circuit. This example has a delta arrangement in which each pixel is shifted by a predetermined distance in the horizontal scanning direction. The power supply line PVDD slightly shifts in the horizontal scanning direction (right or left direction) above each pixel, and then extends right or left in the pixel in the vertical scanning direction. Therefore, the power supply line PVDD extends while being bent in a crank shape in the vertical scanning direction.

  In addition, the data line DL is shifted slightly in the horizontal scanning direction (left or right direction) at the upper part of the pixel in the vertical scanning direction (lower part of the pixel in the upper row), and then the left or right side in the pixel is vertical. Extends in the scanning direction. The data line DL is always shifted in the reverse direction in the horizontal scanning direction with respect to the power line PVDD. Therefore, after the data line DL extends in one pixel adjacent to one power line PVDD in the vertical scanning direction, In the pixel in the next row, the pixel extends in the vertical scanning direction along the power supply line PVDD on the opposite side. If one pixel is viewed, the data line DL and the power supply line PVDD are arranged on one of the left and right sides, and the data line DL for an adjacent pixel is arranged on the other side.

  The gate line GL is located at the upper end of the pixels in each row, the control line RST1 is about 1/3 from the top in the vertical scanning direction, the control line RST2 is at the bottom of the pixels, and the gate in the lower row It is located just above the line GL. All three lines positioned in the horizontal scanning direction are straight lines.

  The pixels have different sizes depending on their emission colors, and the detailed layout differs for each color. In this example, the areas are sequentially reduced in the order of blue (B), red (R), and green (G). This is because in this example, blue has the lowest luminous efficiency and green has the highest luminous efficiency. Further, the arrangement of the odd and even rows is opposite in the horizontal direction.

  FIG. 4 shows a layout for one pixel of the emission color green. A contact CT1 is provided in the data line DL at the upper left of the pixel, and one end of the semiconductor layer SCL1 is located in the contact CT1 portion. . The semiconductor layer SCL1 extends in the horizontal scanning direction along the gate line GL. Further, a gate electrode 20g extending so as to intersect with the semiconductor layer SCL1 is projected from the gate line GL. The portion of the semiconductor layer SCL1 where the gate electrode 20g intersects becomes the channel region of the selection TFT 20, and both sides thereof become the drain and source regions.

  In a portion adjacent to the selection TFT 20 in the horizontal scanning direction and close to the data line DL of the adjacent pixel, the semiconductor layer SCL1 extends in a substantially rectangular shape in the vertical scanning direction. In this quadrangular portion, a capacitor electrode 22a having the same depth as the gate line GL is disposed so as to face the gate insulating film 14, and a capacitor 22 is formed there.

  FIG. 5 shows a cross-sectional view of this portion. A buffer layer 12 is formed on the surface of the glass substrate 10, and a semiconductor layer SCL1 is formed thereon. A gate insulating film 14 is formed on the semiconductor layer SCL1, and a gate electrode 20g is formed on the gate insulating film 14 in the selection TFT 20 portion. In the portion of the capacitor 22, the capacitor 22 is formed by the semiconductor layer SCL <b> 1 and the capacitor electrode 22 a facing each other with the gate insulating film 14 interposed therebetween. An interlayer insulating film 16 is formed so as to cover the gate electrode 20g and the capacitor electrode 22a, and metal wirings such as a data line DL and a power supply line PVDD are formed on the upper surface of the interlayer insulating film 16.

  The semiconductor layer SCL1 that becomes the electrode of the capacitor 22 then extends so as to return to the original direction in the horizontal scanning direction. That is, the semiconductor layer SCL1 has a U shape as a whole. Then, the protruding portion of the control line RST1 intersects the semiconductor layer SCL1 extending in the horizontal scanning direction, and this constitutes the gate electrode 26g of the reset control TFT 26, and the reset control TFT 26 is formed here. That is, the intersection of the semiconductor layer SCL1 with the gate electrode 26g constitutes the channel region, and both sides thereof constitute the drain and source regions. The end portion of the semiconductor layer SCL1 is connected to the power supply line PVDD through a contact CT2.

  FIG. 6 shows a cross-sectional view of this portion. A semiconductor layer SCL1 forming the capacitor 22 extends in the horizontal scanning direction, and a reset control TFT 26 is formed here, and an end thereof is connected to the upper power supply line PVDD by a contact CT2. Further, a contact CT3 is provided on the capacitor electrode 22a of the capacitor 22 and is connected to the aluminum wiring 52 on the interlayer insulating film 16.

  The aluminum wiring 52 extends in the vertical scanning direction across the control line RST1, and is connected to the semiconductor layer SCL2 by a contact CT4. The semiconductor layer SCL2 extends in the horizontal scanning direction along the control line RST1, and reaches the gap between the power supply line PVDD and the data line DL. In the semiconductor layer SCL2 extending in the horizontal scanning direction, a protruding portion from the control line RST2 is formed as a gate electrode 28g, and a short-circuit TFT 28 is formed here.

  FIG. 7 shows a cross-sectional view of this portion. A gate electrode 28g is formed above the semiconductor layer SCL2, the channel region of the short-circuit TFT 28 is below the gate electrode 28g, and both sides are a source region and a drain region. It is an area.

  The semiconductor layer SCL2 extends downward between the data line DL and the power supply line PVDD in the vertical scanning direction and reaches the vicinity of the control line RST2. In the middle of the process, the pixel branches in the inner direction of the pixel (horizontal scanning direction), extends to the center of the pixel, further bends downward in the vertical scanning direction, and extends downward along the power supply line PVDD. At the end of the branched semiconductor layer SCL2, a protruding portion from the power supply line PVDD is disposed so as to be overlapped, and these are connected by a contact CT5. Accordingly, the driving TFT 24 is constituted by a semiconductor layer SCL2 bent in a hook shape.

  In addition, the gate electrode 24g of the driving TFT 24 is disposed so as to overlap with a portion bent in the vertical scanning direction in the central portion of the pixel of the semiconductor layer SCL2. On the other hand, the above-described aluminum wiring 52 extends to the side of the corner that bends in the vertical scanning direction of the semiconductor layer SCL2, and the gate electrode 24g is connected to the aluminum wiring 52.

  FIG. 8 shows a cross-sectional view of this portion, and the gate electrode 24g is connected to the aluminum wiring 52 on the interlayer insulating film 16 by a contact CT5. The semiconductor layer SCL2 below the gate electrode 24g is the channel region of the driving TFT 24. The drive TFT 24 is a p-channel TFT, and the drain region is doped with a p-type impurity. On the other hand, the wiring portion of the semiconductor layer SCL2 is doped with n-type impurities, and a diode 40 by a PN junction is formed at the boundary portion between the two.

  Further, the semiconductor layer SCL2 is bent in the inner direction of the pixel and extends along the control line RST2 before reaching the control line RST2 in the vertical scanning direction. On the semiconductor layer SCL2 extending along the control line RST2, a protruding portion from the control line RST2 is formed so as to be a gate electrode 30g of the drive control TFT 30.

  FIG. 9 shows a cross-sectional view of this portion. In this way, the contact CT7 is provided at the end of the semiconductor layer SCL2 on the center side of the pixel, and the anode 32a of the organic EL element 32 is connected via the aluminum wiring 54 on the interlayer insulating film 16. The anode 32a is disposed in a region between the control lines RST1 and RST2 in the vertical scanning direction, and is disposed in a relatively wide region between the data line DL and the power supply line PVDD in the horizontal scanning direction. The anode 32a is disposed. This area is almost the light emitting area.

  In this example, a metal (aluminum) wiring such as a data line DL and a power supply line PVDD is provided on the interlayer insulating film 16, a planarizing film 18 is formed so as to cover it, and an anode 32a is formed thereon. Yes. The anode 32a is made of a transparent conductive material such as ITO, and is connected to the metal on the interlayer insulating film 16 by a contact CT8 penetrating the planarizing film 18. The contact CT8 is made of the same material as the anode 32a.

  As described above, according to this embodiment, the three lines of the gate line GL, the control line RST1, and the control line RST2 are provided in the horizontal scanning direction. The gate electrodes of the TFTs 20, 26, 28, and 30 can be formed, wiring is reduced, and the light emitting area can be made relatively large (the aperture ratio can be made relatively large).

  In particular, since the light emitting area is disposed between the control lines RST1 and RST2, the TFTs 26 and 28 can be disposed near the control line RST1, and the drive control TFT 30 can be disposed near the control line RST2. Further, by forming the driving TFT 24 along the light emitting area, a relatively large transistor can be efficiently arranged.

  A selection TFT 20 and a capacitor 22 are arranged between the gate line GL and the control line RST1. As a result, both can be arranged close to each other, wiring can be shortened, and writing time can be shortened.

  Further, since the drive TFT 24 and the drive control TFT 30 are arranged between the control lines RST1 and RST2, the gate of the drive TFT 24 can be made large. The drive control TFT 30 is provided adjacent to the control line RST2, and the gate electrode thereof can be directly projected from the control line RST2. Further, since the drive control TFT 30 is provided adjacent to the light emitting area, the connection with the anode 32a of the organic EL element 32 is easy.

  Further, since the reset control TFT 26 and the short-circuit TFT 28 are disposed opposite to both sides of the control line RST1, both TFT gates can be formed directly projecting from the control line RST1, and the wiring efficiency is improved.

  In this embodiment, the selection TFT 20 is disposed in the region between the gate line GL and the control line RST1, but it is also preferable to dispose the selection TFT 20 between the gate line GL and the control line RST2 in the adjacent row.

  Note that the cross-sectional views of FIGS. 5 to 9 are partial cutouts of the main part of the circuit for one pixel, and schematically show each layer in an easy-to-see manner.

"Other layout examples"
10 and 11 show other layout examples. Basically, it is the same as in FIGS. 3 and 4, but the shape of the drive TFT 24 is different. That is, the branch position in the horizontal scanning direction from the semiconductor layer SCL2 forming the driving TFT 24 is lower in the vertical scanning direction of the pixel. Then, after branching, the semiconductor layer SCL2 extends straight upward in the vertical scanning direction in parallel with the power supply line PVDD, and a gate electrode is superimposed on the linear portion.

  In this example, the drain of the drive TFT 24 is not connected to the drive control TFT 30 and the short-circuit TFT 28 as they are in the same semiconductor layer SCL2, but a contact CT9 is provided and is temporarily lifted and connected to the metal layer. Therefore, the diode 40 does not exist.

  Even with such an arrangement, a panel having a high aperture ratio can be obtained as in the above-described embodiment.

“Setting parasitic capacitance”
As described above, in an actual pixel circuit, basically, a gate capacitance exists in the TFT, and the lower layer in which the semiconductors SCL1 and SCL2 are disposed, the intermediate layer in which the gate line GL is disposed, the PVDD and the data line DL. There are three wiring layers in the upper layer in which are arranged, and parasitic capacitance is generated at a place where these intersect.

  FIG. 12 is a diagram illustrating the parasitic capacitance that affects when the signal supplied from the data line DL is set to the gate of the driving TFT 24. In this figure, the diode 40 is omitted.

  FIG. 13 shows only the capacitance when the gate voltage Vg of the driving TFT 24 is determined. In addition, about the capacity | capacitance paralleled, it has shown in the form which added.

  Further, FIG. 14 points out these capacities on the layout display of FIG.

  Thus, a parasitic capacitance Ch is generated in parallel with the reset control TFT 26 between the source of the selection TFT 20 and the power supply line PVDD. In addition to the gate capacitance Cg located on the channel region, the drive TFT 24 generates a capacitance Cp between the gate and the source (PVDD) and a capacitance Cd between the gate and the drain. In FIG. 14, the gate electrode extends to the lower side of the power supply line PVDD, and the overlapping portion is a parasitic capacitance Cp. In the configuration of FIG. 11, the parasitic capacitance Cp is zero. Further, a parasitic capacitance Ccv is formed by the gate electrode and the pixel electrode above the gate electrode, and a gate capacitance Cg is formed below the gate electrode.

  In the pixel circuit, the data voltage Vsig from the data line is taken in, and the voltage Vg corresponding to this is set at the gate of the driving TFT 24. At this time, the above-described capacity is affected.

  Thus, the voltage on the selection TFT 20 side of the capacitor 22 is the signal voltage Vsig, and the capacitor Ch is arranged between this point and the power supply PVDD. The other end of the capacitor 22 (Cs) is the gate of the driving TFT 24 and becomes the gate voltage Vg. A capacitor Cp + Cg is arranged between the gate of the driving TFT 24 and the power supply PVDD, and a capacitor Ccv + Cd is arranged between the cathode power supply cv.

"When entering data"
At the time of data input when the selection TFT 20 is turned on, the reset control TFT 26, the short-circuit TFT 28, and the drive control TFT 24 are turned off. Therefore, the gate voltage Vg of the driving TFT 24 is
Vg = {Cs / (Cp + Cg + Ccv + Cd + Cs)} · Vsig
It becomes.

"Data retention status"
On the other hand, in the data holding state, the selection TFT 20 is turned off and the drive control TFT 30 is turned on. Therefore, the gate voltage Vg is
Vg = {(Ccv + Cd) / (Cp + Cg + Cd + Ch * Cs)}. (PVDD−CV)
It becomes. Here, Ch * Cs = Ch · Cs / (Ch + Cs).

If Ch << Cs, Ch * Cs = Ch, so
Vg = {(Ccv + Cd) / (Cp + Cg + Cd + Ch)}. (PVDD−CV)
It becomes.

  Thus, the voltage Vg of the driving TFT 24 is affected by various parasitic capacitances. Therefore, if there is a difference in the parasitic capacitance value, even if the data voltage Vsig is the same, the set gate voltage Vg is different.

  In particular, in the present embodiment, in each row in the horizontal scanning direction, the layout is different between the odd rows and the even rows. Therefore, if there is a difference in parasitic capacitance between pixels in odd rows and pixels in even rows, a difference occurs in the set gate voltage Vg for the same data signal Vsig, and the light emission amount of the organic EL element 32 differs. End up.

  Therefore, in the present embodiment, for the same color pixels, the layout is formed so that the parasitic capacitances, particularly Cp and Ch, are the same in the even and odd rows.

  That is, the area of the region overlapping the power supply line PVDD of the semiconductor layer SCL1 extending from the source of the selection TFT 20 to the capacitor 22 is set to be the same area in the same color in even rows and odd rows. In addition, the area where the gate electrode of the driving TFT 24 and PVDD are close to each other is set so that the even-numbered rows and the areas of the regions have the same area in the same colors of even-numbered rows and odd-numbered rows. As a result, the parasitic capacitances Ch and Cp are prevented from differing between even and odd rows, and the occurrence of unevenness between rows is prevented.

  It should be noted that since the relationship between the supplied data voltage Vsig and the luminance itself is different from the other colors in the pixels having different emission colors, it is not necessary to make these parasitic capacitances the same among the pixels of different colors.

  Further, the driving TFT 24 needs to be formed with the same ability (size) for each color, and therefore, other parasitic capacitances can be made the same for each color without being affected by the layout.

"Contact with anode"
A contact CT8 between the anode 32a of the organic EL element 32 and the aluminum wiring 54 is disposed immediately above the control line RST2.

  By arranging the contact at a position that cannot be used as the light emitting area, the light emitting area can be increased, and the aperture ratio is increased. In addition, since the contact CT8 only connects the aluminum wiring 54 and the anode 32a, the contact CT8 is shorter than the direct contact with the semiconductor layer SCL2, and the resistance can be reduced. Moreover, the aluminum wiring 54 arranged on the control line RST2 is a smooth surface, and the contact resistance can be reduced by connecting the contact CT8 thereto.

“Parasitic capacitance of control line RST1”
The gate electrode 24 g of the driving TFT 24 is configured by an aluminum wiring 52 from the capacitor 22. Therefore, the aluminum wiring 52 intersects with the control line RST1, and a parasitic capacitance is generated here. That is, since the aluminum wiring 52 and the control line RST1 face each other with the interlayer insulating film 16 therebetween, a capacitor is formed here. In this embodiment, since the aluminum wiring 52 and the control line RST1 are orthogonal to each other, the capacitance formed here is minimized, and this capacitance is basically the same for all the pixels. .

  If the capacitances are the same color and different, the coupling noise generated during the operation of the control line RST1 is different, and the gate potential of the drive TFT 24 may be different regardless of the same video signal, and the emission luminance may be different. There is. According to the present embodiment, occurrence of such a problem can be effectively prevented.

  For this purpose, the capacities must be at least the same color and the same, and the size thereof should be equal to or less than the area where the control line RST1 and the data line DL overlap. .

"Semiconductor layer SCL2"
The three TFTs 24, 28, 30 are constituted by the semiconductor layer SCL2 and are connected to each other. A connection portion by the semiconductor layer SCL2 is disposed between the data line DL extending in the vertical scanning direction and the power supply line PVDD.

  Thus, since the semiconductor layer SCL2 is arranged so as not to overlap the data line DL, the probability of picking up noise from the data line DL can be reduced. In addition, since the power supply line PVDD is not superimposed, parasitic capacitance can be reduced and signal deterioration can be prevented.

  In the present embodiment, the semiconductor layer SCL2 is an n-type impurity doped layer. This is because the n-type can reduce the wiring resistance. On the other hand, the drive TFT 24 is a p-channel TFT, and its source and drain are doped with p-type impurities. Accordingly, a diode 40 with a PN junction is formed at the junction between the drain of the driving TFT 24 and the wiring portion of the semiconductor layer SCL2. However, in this diode 40, the direction in which the current from the driving TFT 24 flows toward the EL element 32 is the forward direction, and there is no problem.

  In order to avoid the formation of the PN junction, a contact may be provided to connect the p-type portion and the n-type portion with metal. In this embodiment, since the PN junction is formed, it is not necessary to provide a contact, the structure is simple, and the yield can be improved.

“Configuration example of pixel circuit”
FIG. 15 shows another configuration example of the pixel circuit. In this circuit, the reset control TFT 26 is omitted, and instead, a capacitor 34 having one end connected to the power supply line PVDD and the other end connected to the gate of the driving TFT 24 is provided. The selection TFT 20, the short-circuit TFT 28, and the drive control TFT 30 are all formed of p-channel TFTs. This pixel circuit is similar to that described in Patent Document 1 and operates in the same manner.

  Here, in this embodiment, the timing of turning on the short-circuit TFT 28 and turning on the drive control TFT 30 is slightly shifted as shown in FIG. In this embodiment, since the p-channel TFT is used, the polarity of the signal supplied to each line is reversed.

  In this embodiment, the drive control TFT 30 is turned on when the selection TFT 20 is turned on. As a result, similarly to the above case, it is possible to prevent the gate voltage of the drive TFT 24 from being lowered as the drive control TFT 30 is turned on.

  Also in the circuit of FIG. 15, two control lines are provided in addition to the gate line GL in the horizontal scanning direction. Therefore, a layout similar to that of the above-described embodiment can be applied.

  Further, the reset control TFT 26 can be simply omitted. In this case, a predetermined voltage (for example, PVDD) may be set in the data line and the selection TFT 20 may be turned on. As a result, on the selection TFT 20 side of the capacitor 22, the voltage becomes PVDD, and the same operation as when the reset control TFT 26 is turned on is obtained.

It is a figure which shows the structure of the pixel circuit which concerns on embodiment. FIG. 2 is a waveform diagram of each signal in the pixel circuit of FIG. 1. It is a figure which shows the layout (planar structure) of the panel concerning embodiment. It is a figure which shows the layout for 1 pixel. It is a figure which shows the cross section of the principal part. It is a figure which shows the cross section of the principal part. It is a figure which shows the cross section of the principal part. It is a figure which shows the cross section of the principal part. It is a figure which shows the cross section of the principal part. It is a figure which shows another layout. It is a figure which shows the layout for 1 pixel. It is the figure which also displayed about the regulation capacity in the pixel circuit concerning an embodiment. FIG. 3 is a diagram showing only a capacitor in a pixel circuit. It is the figure which showed the position of the capacity | capacitance on a layout. It is a figure which shows the structure of another pixel circuit.

Explanation of symbols

  10 glass substrate, 12 buffer layer, 14 gate insulation film, 16 interlayer insulation film, 18 planarization film, 20 selection TFT, 22, 34 capacitance, 24 drive TFT, 26 reset control TFT, 28 short-circuit TFT, 30 drive control TFT, 32 organic EL elements, 40 diodes, 52, 54 aluminum wiring, CT1 to CT9 contacts, CV cathode power supply, DL data line, GL gate line, PVDD power supply line, RST1, RST2 control line, SCL1, SCL2 semiconductor layer.

Claims (2)

An organic EL display panel having a pixel circuit including a plurality of transistors in each pixel and arranging the pixels in a matrix,
Each pixel has
One organic EL element;
A drive transistor for controlling the amount of current supplied from the power supply line to the organic EL element;
A selection transistor for controlling whether to supply a data signal from the data line to the gate of the driving transistor via a capacitor;
A short-circuit transistor that controls whether or not to short-circuit between the gate and drain of the drive transistor;
A drive control transistor for controlling whether or not a current from a drive transistor disposed between the drive transistor and the organic EL element is supplied to the organic EL element;
Including
Although the arrangement of transistors in each pixel is different between even rows and odd rows,
Even-numbered pixels and odd-numbered pixels in the same color pixel have substantially the same area where the semiconductor layer connected from the selection transistor to the capacitor intersects the power supply line, and parasitics generated there An organic EL display panel characterized in that the capacitance is set to be the same between pixels of the same color in each row. An organic EL display panel having a pixel circuit including a plurality of transistors in each pixel and arranging the pixels in a matrix,
Each pixel has
One organic EL element;
A drive transistor for controlling the amount of current supplied from the power supply line to the organic EL element;
A selection transistor for controlling whether to supply a data signal from the data line to the gate of the driving transistor via a capacitor;
A short-circuit transistor that controls whether or not to short-circuit between the gate and drain of the drive transistor;
A drive control transistor for controlling whether or not a current from a drive transistor disposed between the drive transistor and the organic EL element is supplied to the organic EL element;
Including
Although the arrangement of transistors in each pixel is different between even rows and odd rows,
Even-numbered pixels and odd-numbered rows of pixels of the same color are set so that the parasitic capacitance generated between the control end of the drive transistor and the power supply line is the same between the same-color pixels in each row. An organic EL display panel characterized by that.

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