JP2007305766A - Circuit board manufacturing method - Google Patents

Abstract

There is provided a circuit board manufacturing method capable of miniaturizing a wiring pattern by eliminating a positional shift between a hole for conducting between conductive wiring layers and a surface wiring portion.
An exposure process is performed on a resist layer formed on a conductive layer on an insulating layer to form three types of regions having different development processing speeds (referred to as a first region, a second region, and a third region). In addition, between the removal process of the resist layer in the first area (first development process) and the removal process of the resist layer in the second area (second development process), Plating is applied to the conductive layer in one region, and the conductive layer in the second region is removed or removed between the second developing process and the resist layer removing process (third developing process) in the third region. And a step of applying plating to the conductive layer in the two regions, and forming a hole in the insulating layer in any one of the first region, the second region, and the third region after the third development processing. A method for manufacturing a circuit board.
[Selection] Figure 3

Description

  The present invention relates to a method of manufacturing a circuit board, and in particular, in a multilayer board formed by laminating a plurality of conductive wiring layers, a positional shift between a hole for conducting electricity between each conductive wiring layer and a wiring pattern is eliminated. The present invention relates to a method of manufacturing a circuit board that enables pattern miniaturization.

  As electronic devices have become smaller and more multifunctional in recent years, circuit boards have also been increased in density and wiring patterns, and means for achieving such conditions include multilayer circuit boards. . As shown in FIG. 23, a circuit board formed by laminating a plurality of conductive wiring layers is generally called a through hole (through hole) 41, a via hole 42, and an interstitial via hole 43. Conduction between layers is performed through pores such as coated or filled through holes and non-through holes (hereinafter referred to as holes).

  FIG. 24 is a schematic view of the hole as viewed from above. A conductive layer called a land 18 is formed around the hole 17. There are various types of lands such as a square, a circle, an ellipse, and an irregular shape, but a circular land is often used because of the occupied area or the ease of use of the design surface. In order to cope with higher density, a landless or narrow land width hole is required. Here, the land width means the minimum value of the annular conductor width around the hole in the case of a circular land. If the diameter of the hole at the time of drilling is D0 and the diameter of the circular conductor of the circular land is D, the landless is that the land width Lw = (D−D0) / 2 is zero, and the narrow land width is The land width Lw is greater than 0 and 40 μm or less.

  As a method for manufacturing a circuit board, a subtractive method, an additive method, and a semi-additive method are known. In the case of forming a fine circuit by the subtractive method, there is a disadvantage to the fine circuit because there is a thinning of an image line due to side etching of the conductive layer. On the other hand, the additive method is advantageous for a fine circuit, but has a problem of high manufacturing cost because all the conductive layers are formed by electroless plating. Although the semi-additive method is multi-step, it can be used as a fine circuit manufacturing method because it can use electrolytic plating capable of high-speed operation.

  An example of manufacturing a circuit board by the semi-additive method will be given. First, a through hole 41 called a through hole is formed in the insulating layer 1 (FIG. 25) (FIG. 26), and the thin conductive layer 2 is provided on the surface including the inner wall of the through hole (FIG. 27). Next, a plating resist layer 36 is formed on the non-circuit portion (FIG. 28). Subsequently, a conductive layer is formed on the surface of the portion where the conductive layer 2 is exposed by electrolytic plating (FIG. 29). Thereafter, the plating resist layer 36 is removed (FIG. 30), and the thin conductive layer 2 under the plating resist layer 36 is removed by etching to form a circuit board (FIG. 31).

  The plating resist layer can be formed by a screen printing method, a photofabrication method having an exposure / development process using a photosensitive material, an ink jet method, or the like. Can be used with advantage. As a photofabrication method, a method using a negative type (photocrosslinking type) or a positive type (photolytic type) photoresist is generally used. In the semi-additive method, since a conductive layer is provided inside the hole by electrolytic plating, a state where a plating resist layer is not formed in the hole portion is necessary.

  When using a negative (photocrosslinking type) dry film photoresist, as shown in FIG. 32, the holes and land portions are shielded from light so that the negative (photocrosslinking type) dry film photoresist does not crosslink. Unreacted dry film photoresist is removed so that there is no plating resist layer in the holes and lands. In these processes, it is important to perform hole drilling and alignment in the exposure process, and in particular, in a landless and narrow land width hole required for a high-density circuit board, extremely high alignment accuracy is required.

  For example, as shown in FIG. 33 (b), in the case of a large land width, even if a positional shift occurs by a distance of X, the hole portion is completely shielded from light and is of a negative type (photocrosslinking type). ) Dry film photoresist is not cross-linked, but as shown in FIG. 33 (a), in the case of landless and narrow land width, if the hole and the land are shifted by the same distance X, the land is cut off from the hole portion. Therefore, there is a problem that the conductive layer cannot be satisfactorily formed over the entire outer periphery.

  A technique that solves this problem and can satisfactorily form a conductive layer over the outer periphery of a hole even if a positional shift occurs in an exposure process is disclosed (see, for example, Patent Document 1). According to this method, by using toner electrodeposition, a landless or narrow land opening can be accurately formed in the hole, and a fine pattern can be formed by applying to a semi-additive method. Become. According to this method, as shown in FIG. 34, even if the positional deviation X1 occurs from the state without positional deviation (FIG. 34A) and becomes FIG. Occurrence of (a place where a good conductive layer is not formed over the outer periphery of the hole) can be avoided. However, when the positional deviation X2 that causes the wiring pattern to cover the hole occurs (FIG. 34C), a short defect occurs.

  This is because the drilling process for forming holes for connecting the conductive layers and the pattern exposure process for forming the wiring pattern on the surface are performed by performing alignment with the substrate separately. In addition, since there is a limit to the alignment accuracy of each process, it is inevitable that a displacement occurs. In particular, there has been a problem when manufacturing a circuit board having a fine wiring pattern.

  In addition, a circuit board is manufactured by using a photoplating process on a substrate made of a porous insulator, and a wiring board in which positional deviation between a hole position and a wiring pattern does not occur is also disclosed (for example, a patent) Reference 2). In this method, a hole and a wiring part are formed by one exposure using a mask having two kinds of light transmission regions. This makes it possible to produce a circuit board that does not cause misalignment.

  However, since the conductive layer and the insulating layer are formed inside the porous body, the insulation reliability is inferior compared to the insulating resin layer such as polyimide usually used as the insulating layer. However, the present situation is that high reliability has not yet been established.

  Further, a positive resist film is formed on the substrate, and exposure is performed by changing the exposure amounts of the first region and the second region, and RIE (reactive ions) of the first region and the second region are formed. There is also disclosed a technique in which the etching processing depth by etching) is changed and the positional relationship between the first region and the second region is not shifted (see, for example, Patent Document 3). However, in this method, a method using RIE is disclosed as a method for performing etching processing. However, RIE is not used for hole processing of a normal circuit board in terms of cost and productivity. In this case, the resist film is used as a resist in the drilling process because of the resistance of the resist film. difficult.

In addition, in the method of manufacturing a circuit board with a finer pattern, the semi-additive method is preferably used as described above, and a plating process is performed on the portion from which the resist layer has been removed. In a method such as Patent Document 3, plating must be applied to a portion where the positive resist exposed at half the exposure amount is removed. In this case, the positive resist exposed at half the exposure amount Resist residue remains in the removed portion, and it is difficult to perform the plating process. This method can be applied to the manufacture of Levenson-type phase shift masks or the etching of dual damascene semiconductor devices using RIE, but the manufacture of circuit boards that perform processing by combining different processing solutions. At that time, there were problems of resist film resistance and resist residue, and it could not be applied.
JP 2005-286297 A JP 2002-368383 A JP 2006-53249 A

  It is an object of the present invention to eliminate a positional shift between a hole for conducting between each conductive wiring layer and a surface wiring portion in a multilayer substrate formed by laminating a plurality of conductive wiring layers, and miniaturize a wiring pattern. It is an object of the present invention to provide a circuit board manufacturing method that can be used.

The present inventors have conducted research to solve this problem,
(1) A step of forming a resist layer on the conductive layer on the insulating layer, a step of removing or applying the conductive layer by performing an etching removal process or a plating application process, and a step of forming a hole in the insulating layer. In the method of manufacturing a circuit board including the above, after forming a resist layer, the resist layer is subjected to exposure processing to form three types of regions having different development processing speeds (referred to as a first region, a second region, and a third region). Then, the first layer resist layer removal process (first development process), the second area resist layer removal process (second development process), and the third area resist layer removal process (third development process). In this order separately, between the first development process and the second development process, the etching removal process of the conductive layer in the first region or the plating application process to the conductive layer in the first region is performed, and the second development process and Between the third development process and the second area Etching removal processing of the electric layer or plating application processing to the conductive layer in the second region is performed, and after the third development processing, a hole is formed in the insulating layer in any one of the first region, the second region, and the third region. A method of manufacturing a circuit board including a step of forming,
(2) The resist layer is a photocrosslinkable resin layer, the first area is an unexposed area in the exposure process, the second area is an area exposed at a low exposure amount in the exposure process, and the third area is The method for producing a circuit board according to the above (1), which is a region exposed at a high exposure amount in the exposure process,
(3) (a) forming a photocrosslinkable resin layer on the conductive layer on the insulating layer;
(B) performing an exposure process on the photocrosslinkable resin layer to form an unexposed portion (first region), a low exposure amount exposure portion (second region), and a high exposure amount exposure portion (third region);
(C) removing the photocrosslinkable resin layer in the first region and exposing the conductive layer in the first region by a first development process;
(D) a step of etching away the exposed conductive layer in the first region by an etching process;
(E) removing the photocrosslinkable resin layer in the second region and exposing the conductive layer in the second region by the second development treatment;
(F) a step of performing pattern plating on the exposed conductive layer in the second region by electrolytic plating;
(G) a step of removing the photocrosslinkable resin layer in the third region by the third development treatment;
(H) removing the insulating layer in the first region to form a hole;
(I) a step of conducting the conductive treatment in the hole;
(J) flash etching to remove the conductive layer in the third region;
Circuit board manufacturing method including
I found.

  In the method (1) for producing a circuit board of the present invention, a step of forming a resist layer on the conductive layer on the insulating layer, a step of removing or applying the conductive layer by performing an etching removal process or a plating application process, In the method of manufacturing a circuit board including a step of forming a hole in the insulating layer, the resist layer is subjected to an exposure process after the resist layer is formed, and three regions having different development processing speeds (first region, first region, and second region) are formed. 2 regions and third regions), a resist layer removal process in the first region (first development process), a resist layer removal process in the second region (second development process), a resist in the third region The layer removal process (third development process) is performed separately in this order, and between the first development process and the second development process, the etching removal process of the conductive layer in the first region or the conductive layer in the first region is performed. Plating is applied and second development The etching process of removing the conductive layer in the second region or the plating application process to the conductive layer in the second region is performed between the first development process and the third development process. Then, the circuit board is manufactured by a method including a step of forming a hole in the insulating layer in any region of the third region. By defining the first area, the second area, and the third area by the first exposure process, the three types of states, that is, the three areas of the hole forming area, the surface wiring area, and the surface non-wiring area are in a positional relationship. Can be determined without misalignment.

  In addition, the resist layer in each region is sequentially removed in separate steps, and the conductive layer is removed by etching or plating is applied at each stage, so that three types of states can be formed satisfactorily. In addition, when the resist layer of the entire region is completely removed, the state of the three kinds of conductive layers has been completed by the etching removal process or plating application process of the conductive layer before that, and the subsequent steps By appropriately selecting the above, it is possible to manufacture the circuit board by properly forming the three regions of the hole forming region, the surface wiring region, and the surface non-wiring region without misalignment. In addition, when the hole is formed in the insulating layer, the hole is formed without causing a problem that the resist layer is damaged and adversely affected by removing the resist layer. It becomes possible. In addition, by performing a hole forming process in a region where there is no conductive layer, the position of the hole is accurately defined, and a favorable hole can be formed. As a result, the position of the hole and the surface wiring portion can be positioned with a simple configuration without taking much time and cost to improve the alignment accuracy during exposure and drilling. A circuit board with a fine pattern such as can be manufactured stably and accurately.

  In the circuit board manufacturing method (2) of the present invention, the resist layer is a photocrosslinkable resin layer, and in the exposure process, the unexposed area is the first area, the low exposure dose exposed area is the second area, and the high exposure is performed. By making the amount exposure part the third region, it is possible to easily form three types of regions using existing equipment, and each development process is performed sequentially in separate steps, and the resist in each region is good It is possible to remove it. In addition, when a photocrosslinkable resin layer is used, when a plating treatment is performed on the exposed conductive layer region, a resist residue does not remain on the exposed conductive layer surface, so that a favorable plating treatment is performed. In addition, by adjusting the exposure amount appropriately, it is possible to maintain the necessary and sufficient thickness of the resist layer.

  In the circuit board manufacturing method (3) of the present invention, first, a photocrosslinkable resin layer is formed on a conductive layer on an insulating layer. Next, the photocrosslinkable resin layer is subjected to an exposure treatment to form an unexposed portion (first region), a low exposure amount exposure portion (second region), and a high exposure amount exposure portion (third region). As a result, three different states, that is, a base state for creating a hole forming portion, a surface wiring portion, and a surface non-wiring portion can be formed through each subsequent processing step. In addition, by forming these three areas collectively by exposure processing, it is possible to accurately define the positional relationship between the areas, and a circuit board having no positional deviation between the hole position and the wiring pattern can be obtained. It is done. Thereafter, by the first development process, the photocrosslinkable resin layer in the first region is removed, and the conductive layer in the first region is exposed. Thereafter, the exposed conduction in the first region is removed by etching. Next, the photo-crosslinkable resin layer in the second region is removed by the second development treatment to expose the conductive layer in the second region, and pattern plating is performed on the exposed conductive in the second region by the electrolytic plating treatment. Since the conductive layer in the hole portion has already been removed by etching, the plating grows only on the surface wiring portion. Subsequently, after the photocrosslinkable resin layer in the third region is removed by the third development process, the insulating layer in the first region is removed to form a hole. When the hole is formed in the insulating layer, the conductive layer has already been subjected to three types of states (conductive layer-free region, thick conductive layer region, and thin conductive layer region) by etching and plating. As a result, it is possible to avoid the adverse effects due to the damage of the resist layer, and to form favorable holes at accurate positions. Next, the conductive treatment in the hole is performed, and finally the flash etching is performed to remove the conductive layer in the third region, thereby manufacturing a circuit board having a fine pattern with no displacement.

  Hereinafter, the circuit board manufacturing method of the present invention will be described in detail.

  An example of a method for manufacturing a circuit board according to the present invention will be described with reference to FIGS. An example in which the resist layer is a photocrosslinkable resin layer, the etching removal process is performed between the first development process and the second development process, and the plating application process is performed between the second development process and the third development process. explain.

  As shown in FIG. 1, after preparing the board | substrate which formed the conductive layer 2 on the surface of the insulating layer 1, and forming the resist layer 3 which consists of a photocrosslinkable resin layer as shown in FIG. An exposure process is performed to form three types of resist layers: a resist layer 31 in the first region, a resist layer 32 in the second region, and a resist layer 33 in the third region (FIG. 3). The resist layer 31 in the first region is an unexposed portion, the resist layer 32 in the second region is a low exposure amount exposure portion, and the resist layer 33 in the third region is a high exposure amount exposure portion. Subsequently, a removal process (first development process) of the resist layer 31 in the first region is performed to expose the conductive layer 21 in the first region as shown in FIG. Subsequently, the conductive layer 21 in the first region is removed by performing an etching removal process (FIG. 5). Next, by a second development process, a removal process of the resist layer 32 in the second region is performed to expose the conductive layer 22 in the second region (FIG. 6). Subsequently, an electrolytic plating process is performed, and a conductive layer is applied on the exposed conductive layer 22 to increase the thickness of the conductive layer in the second region (FIG. 7). Next, a third development process is performed to remove the resist layer 33 in the third region, thereby exposing the conductive layer 23 in the third region (FIG. 8). Next, a hole is formed in the first region where the insulating layer 1 is exposed (FIG. 9). Thereafter, the conductive treatment in the hole is performed, and the conductive layer 24 in the hole is formed to conduct between the conductive layers on both sides (FIG. 10). Finally, the conductive layer 23 in the third region is removed by flash etching, and a circuit board as shown in FIG. 11 is manufactured.

  In the above description, the resist layer is a photocrosslinkable resin layer (that is, a negative resist layer), but a positive resist layer can also be used. However, in this case, the first area is a high exposure amount exposure part, the second area is a low exposure amount exposure part, and the third area is an unexposed part. However, when performing the plating treatment, a photocrosslinkable resin layer is preferably used because of merits such as the absence of resist residue and the ability to maintain a large film thickness.

  In the above description, an example in which the etching removal process is performed between the first development process and the second development process and the plating application process is performed between the second development process and the third development process has been described. The etching removal process and the plating application process can be arbitrarily combined. Any combination can be used as long as the regions having three different conductive layer thicknesses can be created at least when the removal of the resist layer in the third region is completed by the third development process. However, when the surface wiring portion is formed by pattern plating as in the semi-additive method and the life of the plating solution is strictly controlled at that time, the resist layer in the second region of the low-exposure-exposure portion is mixed. It is not preferable, and the plating treatment is preferably performed after the second development process in which the resist layer in the second region is removed.

  Examples of the insulating layer according to the present invention include a phenol resin layer, an epoxy resin layer, a polyester resin layer, a polyimide resin layer, and a liquid crystal polymer layer. If perforation is possible, you may have base materials, such as glass cloth and paper. As the conductive layer, copper, silver, gold, aluminum, stainless steel, 42 alloy, nichrome, tungsten, ITO, conductive polymer, various conductive complexes, and the like can be used. Examples of these are described in “Handbook of Printed Circuit Technology” (edited by Japan Printed Circuit Industry Association, Nikkan Kogyo Shimbun, 1987).

  As a method of providing a conductive layer on the insulating layer according to the present invention, a sputtering method, a vapor deposition method, an electroless plating method, an electrolytic plating method, a method of bonding an ultrathin conductive layer such as a conductive foil to the insulating layer, or a conductive layer A method of forming a conductive layer of a laminate laminated with a thin film by etching treatment can be used alone or in combination. It can also be formed by applying the resin of the insulating layer to the conductive layer.

  As the resist layer according to the present invention, a negative or positive photosensitive photopolymer is used. Etching removal process that is performed between the first development process and the second development process, and has appropriate removability by the first development process, removability by the second development process, and removability by the third development process Alternatively, any one can be used as long as it has resistance to the plating application process, the etching removal process or the plating application process performed between the second development process and the third development process. In the first development process, the resist layers in the second region and the third region may be reduced in thickness if the conductive layers in the second region and the third region are not exposed. However, when the plating application process is performed between the first development process and the second development process, the thicknesses of the resist layers in the second region and the third region after the first development process are applied by the plating application process. A setting that is thicker than the thickness of the plating to be performed is preferable.

  Examples of negative-type and positive-type photosensitive photopolymers include “Photopolymer Handbook” (edited by Photopolymer Social Society, Kogyo Kenkyukai, 1989) and “Photopolymer Technology” (Akio Yamamoto, Mototaro Nagamatsu). Ed., Nikkan Kogyo Shimbun, 1988).

  In the case of performing the plating treatment, a negative type, that is, a photocrosslinkable resin layer is preferably used because of merits such that there is no resist residue and the film thickness can be maintained thick. In the present invention, examples of the photocrosslinkable resin that can be used as the photocrosslinkable resin layer include a photocrosslinkable dry film photoresist for manufacturing a circuit board. Examples will be given below, but any photocrosslinkable resin layer can be applied as long as it does not differ from the gist of the present invention. For example, a negative photosensitive resin composition comprising a binder polymer containing a carboxylic acid group, a photopolymerizable polyfunctional monomer, a photopolymerization initiator, a solvent, and other additives can be used. Their blending ratio is determined in accordance with required properties such as sensitivity, resolution, and hardness. In these examples, as a commercial product, for example, Liston from DuPont MRC Dry Film Co., Ltd., Fotec from Hitachi Chemical Co., Ltd., Sunfort from Asahi Kasei Electronics Co., Ltd. can be used. In the commercial product, the photocrosslinkable resin film is sandwiched between a support film such as a polyester film and a protective film such as a polyethylene film. For the formation of the resist layer, when a dry film photoresist is used, a thermal laminating method can be suitably used.

  As a method of forming three types of regions, the first region, the second region, and the third region, by the exposure process, a resist layer in the first region is used in the subsequent first development process, second development process, and third development process. As long as the resist layer in the second region and the resist layer in the third region can be removed separately, any exposure processing can be performed. Three types of regions are formed by changing the exposure wavelength and exposure amount. It is preferable to process the three types of areas in a series of steps that do not cause misregistration. However, if the amount of misregistration can be set to a small amount, the three types of areas can be processed by different exposure processes on the same apparatus. An area exposure process can also be performed.

  From the viewpoint that existing exposure processing equipment can be used, it is desirable to form three types of regions by changing the exposure amount. To use the photocrosslinkable resin layer as a resist layer and to form three types of regions according to the exposure amount, the first region is an unexposed region, the second region is a low exposure region, and the third region is a high exposure. It is desirable to make it an area of quantity. When exposure is performed directly by a drawing apparatus as an exposure processing facility, three types of regions can be formed by performing two exposures of a low exposure amount exposure and a high exposure amount exposure. In the case of exposure using a photomask, by using a halftone mask in which the shading density of the second region portion is halftone in advance, three types of regions can be formed by one exposure. . In the halftone mask, the second region portion may be halftone by adjusting the optical density, or the halftone can be formed by forming a fine halftone dot pattern.

  By appropriately setting the exposure processing conditions in each region and the development processing conditions in each subsequent development processing step, the first region can be removed by the first development processing, and the second region can be removed by the first development processing. The area that is not removed but can be removed by the second development process and the third area can be an area that is not removed by the first and second development processes but can be removed by the third development process.

  If the above conditions are satisfied, any exposure processing condition is possible, but when the photocrosslinkable resin layer is used, the exposure amount of the second region is in the range of 1% to 80% of the exposure amount of the third region, More preferably, it is in the range of 3% to 60%, preferably in the range of 5% to 40%. If the exposure amount of the second region is too low, the film thickness reduction of the resist layer in the second region is too large in the first development process, which causes a problem that the conductive layer in the second region is exposed, and the exposure amount is too high. Then, the curing proceeds too much, and there arises a problem that it is difficult to remove the resist layer in the second region by the second development process.

  The exposure apparatus used for the exposure processing according to the present invention is performed by direct laser drawing, contact exposure through a photomask, proximity exposure, projection exposure, or the like. As the light source, in addition to various laser light sources, an ultrahigh pressure mercury lamp, a high pressure mercury lamp, a metal halide lamp, a xenon lamp, or the like can be used.

  Each development process is desirably performed using an alkaline development processing solution when the photocrosslinkable resin layer is alkali-soluble. Any method and condition can be used as long as proper removal is possible as described above, but an aqueous solution of sodium carbonate, sodium hydroxide, potassium hydroxide or the like is preferably used.

  When the same processing solution is used in the first development process and the second development process, the processing time of the second development process is 0.5 to 30 times the processing time of the first development process, more preferably It is desirable to perform the second development processing in a processing time of 1.5 times to 20 times, preferably 2 times to 10 times.

  The etching solution used for the etching removal process according to the present invention may be any one as long as the resist layer present in each region has resistance and can dissolve and remove the conductive layer. For example, common etching solutions such as alkaline ammonia, sulfuric acid-hydrogen peroxide, cupric chloride, persulfate, ferric chloride, and the like can be used. Moreover, as an apparatus and a method, apparatuses and methods, such as horizontal spray etching and immersion etching, can be used, for example. These details are described in “Printed Circuit Technology Handbook” (edited by Japan Printed Circuit Industry Association, published in 1987, published by Nikkan Kogyo Shimbun).

  As the plating application treatment according to the present invention, an electrolytic plating treatment can be suitably used. For example, those described in “Handbook of Printed Circuit Technology” (edited by Japan Printed Circuit Industry Association, Nikkan Kogyo Shimbun, 1987) can be used.

  As a method for forming a hole in the insulating layer according to the present invention, any method can be used as long as the insulating layer can be removed without causing deformation of the conductive layer. Laser drilling and treatment with an insulating layer etchant can be used. A treatment with an insulating layer etchant is preferable because batch treatment is possible.

  As the insulating layer etching liquid, any liquid can be used as long as it dissolves the insulating layer without dissolving the conductive layer. A suitable liquid is selected depending on the type of the insulating layer. When a polyimide resin layer is used as an insulating layer, a conventionally known etching solution for polyimide resin can be used, and particularly contains N- (β-aminoethyl) ethanolamine, potassium hydroxide, and ethanolamine. It is preferable to etch the insulating layer with a polyimide resin etchant made of an aqueous solution because the etching can be performed in a good shape with a small hole diameter.

  As a method for conducting the conductive treatment in the holes according to the present invention, a known method such as filling with a conductive paste, electroless plating, or electrolytic plating can be used. After electroless plating is performed on the entire surface, a plating resist is formed in addition to the holes by the method disclosed in Patent Document 1, and plating is performed only in the holes, so that plating is performed only at the positions of the holes. Since it is performed, it is preferable. Also, the conductive treatment in the holes can be performed by the following method.

  That is, after producing to FIG. 9, the electroless plating process is performed in the hole. Thereafter, a dry film resist for plating resist is laminated on one side. Thereafter, only the pores of the dry film resist are dissolved and removed from the opposite surface with an alkali developer. When a narrow land is required, the removal is performed up to the periphery of the hole. Then, after peeling off the cover film (polyester film) of the dry film, it is exposed and cured. Similarly, dry film lamination, supply of alkaline developer solution through the hole from the opposite side, removal of the cover film, and curing by exposure were performed on the opposite side, so that both sides were opened without misalignment. A plating resist layer can be formed. Then, after plating in the hole by electrolytic plating treatment, the plating resist layer is peeled off, so that the conductive treatment in the hole can be performed (FIG. 10). After that, as shown in FIG. 11, flash etching is performed, and the conductive layer of the surface non-wiring portion is removed by etching to manufacture a circuit board.

  The inside of the hole may be made conductive by using a conductive paste or the like, or a conductive layer may be formed on the wall surface by a combination of electroless plating and electrolytic plating. Moreover, the inside of a hole can also be filled with a conductive layer by electrolytic plating.

  Hereinafter, the present invention will be described in more detail by way of examples. However, the present invention is not limited to these examples.

  A substrate having a 25 μm-thick polyimide film as an insulating layer and a 12 μm-thick copper layer formed on both sides as a conductive layer was prepared. Next, using a laminator for dry film photoresist, a dry film photoresist for circuit formation comprising a 15 μm thick photocrosslinkable resin layer and a 25 μm mask layer (support film, material: polyester, not shown) is prepared. A resist layer (photocrosslinkable resin layer) was formed by thermocompression bonding on both surfaces of the substrate.

  A UV exposure machine having a suction adhesion mechanism by bringing a halftone photomask (surface width conductor width and gap: 20 μm, hole diameter: 25 μm) having a surface wiring portion and hole pattern formed thereon into contact with the mask layer on both sides of the substrate Was used for both-side exposure for 60 seconds. The halftone photomask used was one in which the hole portion was shielded from light, the surface non-wiring portion was transparent, and the surface wiring portion was halftone. The hole portion corresponds to the first region, the surface wiring portion corresponds to the second region, and the surface non-wiring portion corresponds to the third region. The halftone portion of the halftone photomask used was set so that the amount of transmitted light was 30% of the transparent portion. The double-sided halftone masks are position-adjusted and regulated in advance so that there is no positional deviation between the patterns on both sides when the substrate is sandwiched.

  Then, after peeling off the film of the mask layer, the first development treatment is performed by applying shower spray with a 10% by mass sodium carbonate aqueous solution (25 ° C.) for 15 seconds to remove the photocrosslinkable resin layer in the hole. The copper in the hole was exposed.

  Next, using a ferric chloride etchant, the copper in the hole was removed by etching to expose the polyimide in the hole.

  Next, using a 10% by mass sodium carbonate aqueous solution (25 ° C.), a second spray treatment is performed by applying shower spray for 120 seconds to remove the photocrosslinkable resin layer on the surface wiring portion. Exposed copper.

  Next, electrolytic copper plating treatment (Okuno Pharmaceutical Co., Ltd., OPC Process M) was performed to form an electrolytic copper plating layer having a thickness of about 10 μm on the exposed copper portion of the surface wiring portion. Next, using a 3% by mass aqueous sodium hydroxide solution (30 ° C.), a third development treatment was performed to remove the photocrosslinkable resin layer on the surface non-wiring portion.

  Next, the substrate is immersed in an etching solution for polyimide (75 ° C.) made of an aqueous solution containing 33% by mass of N- (β-aminoethyl) ethanolamine, 27% by mass of potassium hydroxide, and 1% by mass of ethanolamine. The exposed polyimide was etched to form holes in the insulating layer made of polyimide. The hole portions on both surfaces were matched without any positional deviation, and a through-hole penetrating both surfaces satisfactorily was obtained.

  Next, after etching with a sodium hydroxide aqueous solution containing 3-methyl-1,3-butanediol, electroless plating is performed in a copper EDTA bath, and a copper layer having a thickness of 0.5 μm is formed on the inner wall of the hole. A conductive layer was formed.

  Thereafter, a plating resist layer was formed on the surface other than the hole openings as follows. That is, a dry film resist is laminated on one surface to form a plating resist layer and a mask layer made of polyester. With the mask layer attached, an alkali developer was supplied from the opposite surface through the hole to dissolve and remove the resist layer on the hole, and then the plating resist layer was cured by ultraviolet irradiation. After removing the mask layer, the plating resist layer and the mask layer are similarly laminated on the opposite surface, and the alkali developer is supplied through the hole from the opposite side of the laminated surface, so that the resist layer on the hole is dissolved and removed. went. Then, it exposed and hardened | cured by ultraviolet exposure, and the plating resist layer was formed in surfaces other than a hole opening part on both surfaces of a base material by removing a mask layer. The opening of the plating resist layer was formed without any displacement from the position of the hole.

  Subsequently, an electrolytic plating process was performed to form an electrolytic copper plating layer having a thickness of about 10 μm in the hole, and conduction between the conductive wiring layers on both sides was formed. Thereafter, the plating resist layer formed on the surface with a sodium hydroxide aqueous solution was removed, and flash etching was performed to remove the copper layer on the surface non-wiring portion, thereby producing a circuit board.

  When the completed circuit board was observed, there was no positional deviation between the surface wiring part and the hole part on both sides, and a circuit board having a fine wiring pattern could be manufactured.

  After the insulating layer 1 was formed on both sides of the double-sided circuit board (FIG. 11) formed in the same manner as in Example 1, a conductive layer 2 composed of a nickel chromium layer and a copper layer was formed by sputtering (FIG. 12). Using a laminator for dry film photoresist in the same manner as in Example 1, a circuit forming dry film comprising a 15 μm thick photocrosslinkable resin layer and a 25 μm mask layer (support film, material: polyester, not shown). A film photoresist was thermocompression bonded to both sides of the substrate to form a resist layer (photocrosslinkable resin layer) (FIG. 13).

  Next, a halftone photomask (surface wiring portion conductor width and gap: 20 μm, hole diameter: 25 μm) in which a pattern of the surface wiring portion and the hole portion is formed is aligned with one side of the substrate, and ultraviolet exposure is performed for 60 seconds. went. Similarly, with respect to the opposite surface, the halftone photomask was aligned and subjected to ultraviolet exposure for 60 seconds (FIG. 14). The halftone photomask used was one in which the hole portion was shielded from light, the surface non-wiring portion was transparent, and the surface wiring portion was halftone. The hole portion corresponds to the first region, the surface wiring portion corresponds to the second region, and the surface non-wiring portion corresponds to the third region. The halftone portion of the halftone photomask used was set so that the amount of transmitted light was 30% of the transparent portion. The halftone masks on each side are aligned to match the inner layer pattern of the double-sided circuit board.

  The alignment of the halftone mask is done by using a halftone mask that has no deviation in dimensional accuracy with the mask pattern used in the exposure at the time of double-sided circuit board production, and by aligning so that there is no positional deviation, The wiring pattern can be formed on the outer layer with almost no displacement from the wiring pattern of the double-sided circuit board.

  After the exposure process, similarly to Example 1, the removal of the resist layer 31 in the first region (FIG. 15), the etching removal process of the conductive layer in the first region (FIG. 16), and the removal of the resist layer 32 in the second region. (FIG. 17), plating treatment for the exposed conductive layer 22 in the second region (FIG. 18), removal of the resist layer 33 in the third region (FIG. 19), and then formation of holes (FIG. 17) by laser irradiation. 20). Laser drilling was performed under conditions where only the insulating layer was removed without affecting the output of the laser to the copper layer. Thereafter, in the same manner as in Example 1, after performing electroless plating treatment in the hole, by performing electrolytic plating after forming a plating resist layer other than the hole portion as follows, Conductive treatment was performed.

  A method of forming a plating resist layer other than the hole was performed as follows. That is, a dry film resist for plating resist (10 μm thick) is laminated on both sides, the cover film is removed, and then a positive charge toner for Mitsubishi OPC printing system (“ODP-TW” manufactured by Mitsubishi Paper Industries Co., Ltd.) is used. Then, a bias voltage +200 V was applied to perform electrodeposition coating, and the toner was electrodeposited on the entire surface other than the hole. Subsequently, the toner was fixed by heating at 70 ° C. for 2 minutes, and then the substrate was treated with an alkaline aqueous solution to remove the plating resist layer in the hole, thereby producing a substrate on which the plating resist layer was formed other than the hole. . Thereafter, an electrolytic plating treatment was performed in the same manner as the in-hole conductive treatment in Example 1, and copper was filled in the holes as the in-hole conductive layer 24. Thereafter, the plating resist layer was removed (FIG. 21). Finally, the conductive layer in the third region was removed by flash etching to manufacture a four-layer circuit board as shown in FIG.

  When the completed circuit board was observed, there was no positional deviation between the surface wiring part and the hole part on both sides, and a circuit board having a fine wiring pattern could be manufactured.

Sectional drawing which shows 1 process in the method of this invention. Sectional drawing which shows the process following FIG. 1 in the method of this invention. Sectional drawing which shows the process following FIG. 2 in the method of this invention. Sectional drawing which shows the process following FIG. 3 in the method of this invention. Sectional drawing which shows the process following FIG. 4 in the method of this invention. Sectional drawing which shows the process following FIG. 5 in the method of this invention. Sectional drawing which shows the process following FIG. 6 in the method of this invention. Sectional drawing which shows the process following FIG. 7 in the method of this invention. Sectional drawing which shows the process following FIG. 8 in the method of this invention. Sectional drawing which shows the process following FIG. 9 in the method of this invention. Sectional drawing which shows the process following FIG. 10 in the method of this invention. Sectional drawing which shows 1 process in the method of this invention. Sectional drawing which shows the process following FIG. 12 in the method of this invention. Sectional drawing which shows the process following FIG. 13 in the method of this invention. Sectional drawing which shows the process following FIG. 14 in the method of this invention. Sectional drawing which shows the process following FIG. 15 in the method of this invention. Sectional drawing which shows the process following FIG. 16 in the method of this invention. FIG. 18 is a cross-sectional view showing a step following FIG. 17 in the method of the present invention. Sectional drawing which shows the process of following the process in FIG. 18 in the method of this invention. Sectional drawing which shows the process following FIG. 19 in the method of this invention. Sectional drawing which shows the process following FIG. 20 in the method of this invention. Sectional drawing which shows the process following FIG. 21 in the method of this invention. 1 is a schematic cross-sectional view showing an example of a multilayer circuit board. The schematic plan view showing a hole and a land. Sectional drawing which shows 1 process in the conventional method. Sectional drawing which shows the process of following the conventional method in FIG. Sectional drawing which shows the process of following the conventional method in FIG. FIG. 28 is a cross-sectional view showing a step following FIG. 27 in the conventional method. FIG. 29 is a cross-sectional view showing a step following FIG. 28 in the conventional method. Sectional drawing which shows the process of following the conventional method in FIG. Sectional drawing which shows the process following FIG. 30 in the conventional method. Sectional drawing which shows the exposure process of the hole part in the conventional method. Schematic showing the position shift with a hole, a land, and a wiring pattern. Schematic showing the position shift of the wiring pattern with respect to a hole.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating layer 2 Conductive layer 3 Resist layer 17 Hole 18 Land 21 Conductive layer of 1st area | region 22 Conductive layer of 2nd area | region 23 Conductive layer of 3rd area | region 24 In-hole conductive layer 31 Resist layer 32 of 1st area | region 32 2nd area | region Resist layer 33 Third region resist layer 36 Plating resist layer 37 Negative dry film photoresist 41 Through hole (through hole)
42 Viahole 43 Interstitial Viahole

Claims (3)

  A circuit board including a step of forming a resist layer on a conductive layer on an insulating layer, a step of removing or applying the conductive layer by performing an etching removal process or a plating application process, and a step of forming a hole in the insulating layer In this manufacturing method, after the resist layer is formed, the resist layer is exposed to form three types of regions having different development processing speeds (referred to as a first region, a second region, and a third region). The resist layer removal process (first development process) in one area, the resist layer removal process (second development process) in the second area, and the resist layer removal process (third development process) in the third area in this order. Separately, between the first development process and the second development process, an etching removal process of the conductive layer in the first region or a plating application process to the conductive layer in the first region is performed, and the second development process and the third development process In between the processing, the second region conductive layer A step of performing etching removal processing or plating application processing to the conductive layer in the second region, and forming a hole in the insulating layer in any one of the first region, the second region, and the third region after the third development processing. A method for manufacturing a circuit board, comprising:   The resist layer is a photocrosslinkable resin layer, the first area is an unexposed area in the exposure process, the second area is an area exposed at a low exposure amount in the exposure process, and the third area is in the exposure process. 2. The method of manufacturing a circuit board according to claim 1, wherein the region is exposed at a high exposure amount. (A) forming a photocrosslinkable resin layer on the conductive layer on the insulating layer;
(B) performing an exposure process on the photocrosslinkable resin layer to form an unexposed portion (first region), a low exposure amount exposure portion (second region), and a high exposure amount exposure portion (third region);
(C) removing the photocrosslinkable resin layer in the first region and exposing the conductive layer in the first region by a first development process;
(D) a step of etching away the exposed conductive layer in the first region by an etching process;
(E) removing the photocrosslinkable resin layer in the second region and exposing the conductive layer in the second region by the second development treatment;
(F) a step of performing pattern plating on the exposed conductive layer in the second region by electrolytic plating;
(G) a step of removing the photocrosslinkable resin layer in the third region by the third development treatment;
(H) removing the insulating layer in the first region to form a hole;
(I) a step of conducting the conductive treatment in the hole;
(J) removing the conductive layer in the third region by flash etching;
A method of manufacturing a circuit board including the above in this order.

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