JP2007324729A - Receiving method and receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To deal with processing for handling sync signals of a plurality of patterns through a simple arrangement even when a plurality of transmission bands are prepared. <P>SOLUTION: The receiving method is applied when a sync signal of one unit is transmitted repeatedly and there are a plurality of transmission patterns set for every unit and signal polarity patterns of one unit, and has a reception system of a plurality of branches obtaining a reception signal individually. On each branch, the reception signal is delayed by a plurality of steps in one unit period, a plurality of reception signals at least at two delay positions are taken out in different combination from the reception signals delayed by a plurality of steps, and reception signals at least at two delay positions in a combination selected depending on a received sync signal pattern are selected among the reception signals in a plurality of combinations. Correlation is detected from each reception signal thus selected on each branch, and running average is determined from signals obtained by performing complex multiplication of correlation detection signals on respective branches thus performing sync signal detection. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a reception method for performing processing for establishing synchronization when receiving data in a wireless or wired digital communication system and a receiver to which the reception method is applied, and in particular, detection of synchronization timing using preamble correlation. It is related with the technology which performs

  In digital communication, in order to perform demodulation by a receiving circuit, it is necessary to first establish synchronization of received signals. FIG. 21 shows a configuration example of a conventional synchronization circuit. Here, it is assumed that a preamble signal including a synchronization signal used for detection of synchronization timing or the like is incorporated in the transmission signal.

  First, a received signal in the RF frequency band received by the antenna 1 is frequency-converted into a received baseband signal in the baseband by the frequency converter 2 using the carrier signal generated by the carrier signal generator 3. Next, the reception baseband signal is adjusted to a reception signal of a predetermined level by an AGC (automatic gain control) circuit 4 and then sampled and converted into a digital signal by an A / D converter 5.

  The converted digital reception signal is sent to the correlator 6 to correlate the reception baseband digital signal with a known preamble code and output a correlation value. Since this correlation value is generally a complex number, the absolute value square calculator 8 obtains the absolute value square and outputs it to the local maximum value detection circuit 9. The maximum value detector 8 outputs the maximum of the correlation value or the timing exceeding a predetermined threshold as the synchronization timing.

  The synchronization detection configuration shown in FIG. 21 is a general reception configuration, but in recent years, there are signals having a relatively complicated synchronization signal pattern as signals transmitted wirelessly, and a configuration for detecting a synchronization signal is present. It can be very complex.

  That is, for example, in recent years, a method called “ultra-wide band (UWB) communication” for performing wireless communication by placing information on a very weak impulse train has attracted attention as a wireless communication system that realizes short-range ultrahigh-speed transmission. Practical use is expected. Currently, in the IEEE802.15.3 standard and the like, a data transmission system having a packet structure including a preamble is proposed as an access control system for such ultra-wideband communication.

  In general, when a wireless network is constructed indoors, a multipath environment in which a reception device receives a superposition of a direct wave and a plurality of reflected waves / delayed waves is formed, and intersymbol interference occurs due to delay distortion. For this reason, a multicarrier transmission scheme represented by an OFDM (Orthogonal Frequency Division Multiplexing) scheme is applied.

  For example, in the IEEE 802.15.3 standard, the standardization of the UWB communication system adopting the OFDM modulation system is underway. In the case of the OFDM_UWB communication system, three subbands each having a frequency of 3.1 to 4.8 GHz are frequency hopped (FH) each having a width of 528 MHz, and OFDM modulation using IFFT / FFT in which each frequency band is composed of 128 points. Is being considered.

Japanese Patent Application Laid-Open No. 2004-228561 discloses an example in which synchronization detection is performed from this type of signal.
Japanese Patent Laid-Open No. 11-215097

  The OFDM system that performs frequency hopping, as in the communication system defined by the IEEE 802.15.3 standard, is usually called a Multi-Band OFDM (MB-OFDM) system. In this system, preamble transmission, which is a signal for acquiring synchronization, is used. Hopping is performed, and the hopping pattern and data transmission pattern (hereinafter referred to as Time Frequency Code; hereinafter referred to as TFC) are defined to have various types.

  That is, for example, as shown in FIG. 22, seven patterns from TFC1 to TFC7 are defined, and a preamble signal that is a synchronization signal is transmitted in any of the seven patterns. Specifically, three frequencies f1, f2, and f3 are prepared as frequencies to be transmitted, and one unit of preamble signal (synchronization signal) is used by using any one of the three frequencies f1, f2, and f3. Are repeatedly sent 24 times (24 slots). In FIG. 22, only 12 periods are shown.

  Explaining each pattern, in the TFC1 pattern, as shown in FIG. 22A, the frequency f1, f2, and f3 are changed in order for each unit of preamble signal (synchronization signal). In the TFC2 pattern, as shown in FIG. 22B, the frequency f1, f3, and f2 are changed in order for each preamble signal in one slot. In the TFC3 pattern, as shown in FIG. 22C, the frequency is changed in the order of the frequencies f1, f2, and f3 for each 2-slot preamble signal. In the TFC4 pattern, as shown in FIG. 22D, the frequency is changed in the order of the frequencies f1, f3, and f2 for each 2-slot preamble signal. In the TFC5 pattern, the preamble signals of all slots are transmitted at the frequency f1, as shown in FIG. 22 (e). In the TFC6 pattern, the preamble signals of all slots are transmitted as shown in FIG. 22 (f). In the TFC7 pattern, the preamble signals of all slots are transmitted at the frequency f3 as shown in FIG. 22 (g). Although not shown here (see Table 2 described in the embodiment described later), the signal polarity (+ or-) of the preamble signal is also set to a specific pattern.

  In order to receive and detect a synchronization signal having such a TFC pattern, there is a problem that a very complicated synchronization detection circuit is required. FIG. 23 is a diagram showing a conventional reception configuration example corresponding to the seven types of preamble signals TFC1 to TFC7 shown in FIG. FIG. 23 shows a synchronization detection configuration after the A / D converter 5 shown in FIG. 22, and a digital signal obtained at the terminal 10a is sent to the reception energy and moving average detection unit 10 and a plurality of correlations are sent. The data is sent to devices 31, 32, 33, 34, 35, and 36. Each of the correlators 31 to 36 is a circuit that correlates a received signal with a known preamble signal pattern.

  Here, the signal obtained at the terminal 10a is directly sent to the correlator 31, and the signal obtained at the terminal 10a is supplied to the correlator 32 after being delayed by the shift register 21. The shift register 21 is a delay circuit that delays a signal for a period of three slots of the preamble signal (one slot of the preamble signal here is 165 clock cycles).

  When the signals are supplied to the correlators 31 and 32 in this way, for example, if the reception frequency is fixed at any one of the frequencies f1 to f3 (FIG. 10), the two correlators 31 and 32 have 3 slots. Correlation is detected by the difference, and when the correlation with the preamble signal is detected simultaneously every three slots, the synchronization signal having the TFC1 or TFC2 pattern is detected. The detection outputs of both correlators 31 and 32 are complex-multiplied by a complex multiplier 41 to become a correlation detection signal in which a TFC1 or TFC2 pattern is detected.

  Further, the signal obtained at the terminal 10 a is directly sent to the correlator 33, and the signal obtained at the terminal 10 a is delayed by the shift register 22 and supplied to the correlator 34. The shift register 22 is a delay circuit that delays the signal for one slot period of the preamble signal.

  When the signals are supplied to the correlators 33 and 34 in this way, for example, if the reception frequency is fixed at any one of the frequencies f1 to f3 (FIG. 22), the two correlators 33 and 34 have one slot. Correlation is detected by the difference, and when the correlation with the preamble signal is detected at every 6 slots at the same time, the synchronization signal of the TFC3 or TFC4 pattern is detected. The detection outputs of both correlators 33 and 34 are complex-multiplied by a complex multiplier 42 to become a correlation detection signal in which a TFC3 or TFC4 pattern is detected.

  Further, the correlator 35 is supplied with a signal obtained by adding the signal obtained at the terminal 10a and the signal delayed by the shift register 23 for two slots by the adder 26. The correlator 36 is supplied with the signal obtained by adding the signal obtained by delaying the signal obtained at the terminal 10 a by the shift register 23 for one slot period and the signal delayed by the shift register 23 for three slot periods by the adder 27.

  By supplying the signals to the correlators 35 and 36 in this way, for example, assuming that the reception frequency matches the transmission frequency of the preamble signal, the correlator 35 detects the correlation from the added signals of the first slot and the third slot. In the correlator 36, the correlation is detected from the addition signal of the second slot and the fourth slot, and when the correlation with the preamble signal is detected in each, the pattern of any one of TFC5, TFC6, and TFC7 is detected. A synchronization signal is detected. The detection outputs of both the correlators 35 and 36 are complex-multiplied by the complex multiplier 43 to become a correlation detection signal in which any pattern of TFC5, TFC6, and TFC7 is detected.

The correlators 31 and 32, 33 and 34, and 35 and 36 that are paired with each other output correlation values of signals that have undergone a predetermined time shift.
Here, the signal polarity pattern of the preamble signal is not particularly described (detailed in the embodiment described later), but the polarity of the preamble signal is inverted only at a specific slot position in the 24 slots to be transmitted. Therefore, the result of complex multiplication of the paired correlator outputs becomes a maximum value (or minimum value) only at that position, so that synchronization can be detected.

  The outputs of the complex multipliers 41, 42 and 43 are supplied to the selector 44, and a system corresponding to the preamble signal pattern received at that time is selected. The signal selected by the selector 44 is sent to the moving average detection unit 50 to detect the moving average. Specifically, the subtractor 52 detects the difference between the input signal delayed by the shift register 51 and the non-delayed signal, and supplies the output of the subtractor 52 to the adder 53 for addition. The output of the unit 53 is added to the signal delayed by one clock period by the delay circuit 4, and the added output is used as a moving average signal.

  The moving average signal detected by the moving average detector 50 is supplied to the divider 61 and divided by the average value of the received energy and the received energy output by the moving average detector 10 to make the signal level a certain range. Normalization is performed, and the output of the divider 61 is supplied to the synchronization detector 62 to perform synchronization detection processing for determining the synchronization detection timing.

  In the reception energy and moving average detection unit 10, the absolute value square calculator 12 calculates the absolute value square of the signal obtained by delaying the input signal by the shift register 11 for 6 slots, and the input signal is directly converted to the absolute value 2 The absolute value is squared by supplying to the multiplier 13 and the difference between the two signals is obtained by the subtractor 14 to obtain received energy. The obtained reception energy value is supplied to the adder 15, and the output of the adder 15 is added to a signal that is delayed by one clock period in the delay circuit 16, and the addition output is the moving average signal and the received energy. The moving average is supplied to the divider 61.

  Synchronization detection is performed in this way, but for each received preamble signal pattern, an individual correlation detector and complex multiplier and a shift register connected to each correlation detector are required, and the circuit configuration is very high. It becomes complicated. That is, when receiving a preamble signal transmitted with various hopping patterns and data transmission patterns with a single receiver, naturally it is difficult to acquire synchronization with one synchronization acquisition algorithm, and it is necessary to have multiple algorithms. Therefore, the configuration becomes very complicated as shown in FIG. After all, the synchronization detection unit of the receiver becomes complicated, the digital circuit becomes large, and it is inevitable that it is disadvantageous in terms of portability and cost.

  In addition, when performing this type of transmission, a plurality of bands are prepared as transmission frequency bands, and different transmission bands are arranged in adjacent areas depending on the system configuration, or the transmission bands are cycled within one area. Frequency hopping may be performed. In the case of a system having a plurality of transmission bands as described above, in order to perform efficient standby, a reception processing system (branch) that receives and detects synchronization for each prepared transmission band transmits Multiple numbers are required corresponding to the number of bands. Thus, when it was set as the structure provided with a some branch, there existed a problem which the structure of a synchronous detection process will be further complicated.

  The present invention has been made in view of such a point, and an object of the present invention is to make it possible to deal with processing that can handle a plurality of patterns of synchronization signals with a simple configuration even when a plurality of transmission bands are prepared. To do.

  In the present invention, as a known synchronization signal to be received, one unit of the synchronization signal is repeatedly transmitted for a predetermined period, and a transmission frequency pattern set for each unit and a signal polarity pattern set for each unit are In the case where there are a plurality of receiving systems, the receiving system has a plurality of branches each of which receives a received signal individually. In each branch, the received signal is delayed by a plurality of stages in one unit cycle, and a plurality of received signals at at least two delay positions are extracted from the received signals delayed by the plurality of stages in different combinations, and the plurality of combinations are received. From the signals, received signals at at least two delay positions in a combination selected in accordance with the synchronization signal pattern to be received are selected. Correlation detection is performed in each branch from each selected received signal, and a moving average is obtained from a signal obtained by complex multiplication of the correlation detection signal in each branch to perform synchronization signal detection.

  By doing so, since selection processing corresponding to the synchronization signal pattern is performed in each branch at the input stage of the correlation detection means, any pattern of synchronization signals can be obtained by one set of correlation detection means for each branch. Can also detect correlation.

  According to the present invention, it is possible to detect a correlation with an excellent characteristic regardless of the pattern of the synchronization signal by one set of correlation detection means for each branch, and the configuration for synchronization detection corresponding to a large number of synchronization signal patterns is simple. Can be. Accordingly, a plurality of synchronization detections can be simultaneously performed in each branch, and for example, synchronization detection efficiency in a system in which a plurality of transmission bands are prepared can be improved.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  In this example, the present invention is applied to a receiver that receives a radio transmission signal of the MB-OFDM system defined by the IEEE 802.15.3 standard. First, a preamble signal pattern that is a synchronization signal of a signal received in this example will be described. The preamble signal pattern has seven patterns TFC1 to TFC7 as already described with reference to FIG. The frequency changes of the seven patterns TFC1 to TFC7 shown in FIG.

  In the case of this example, one unit (one slot) preamble signal is configured to be transmitted continuously for 24 slots (24 cycles). The polarity of the preamble signal in each slot is shown in Table 2 below. Are classified into the following three patterns (sequence numbers 1 to 3). The slot shown as -1 in Table 2 has a negative polarity. The state where the polarity is negative here is a state where all the codes are inverted with respect to the code sequence with a positive polarity.

  As can be seen from Table 2, regardless of the pattern, the polarity of the preamble signal is reversed in the vicinity of the last slot period of the 24 slot period. Detection is performed. In the case of this example, it is assumed that when performing reception processing, it is known in advance which pattern the preamble signal is received.

FIG. 1 shows the configuration until the synchronization detection of the receiver of this example. In this example, the receiver is provided with a plurality of branches composed of a plurality of receiving systems, and is configured to detect synchronization from the received signals in the respective branches.
In the configuration of FIG. 1, the first antenna 101 and the second antenna 201 are provided, and another branch is configured by a circuit processing system connected to the antennas 101 and 201. First, a branch configured by the reception system of the first antenna 101 will be described. A received signal in the RF frequency band received by the first antenna 101 is a frequency converter using a carrier wave signal generated by the carrier wave signal generator 103. At 102, the frequency is converted to a baseband received baseband signal. Next, the reception baseband signal is adjusted to a reception signal of a predetermined level by an AGC (automatic gain control) circuit 104 and then sampled and converted into a digital signal by an analog / digital (A / D) converter 105. The

  The converted digital received signal is delayed by shift registers 106, 107, 108 connected in series in a plurality of stages. Each shift register 106, 107, 108 functions as a delay circuit that delays one slot period (ie, 165 clock periods) of the received preamble signal.

  The output of the shift register 108 is supplied to the reception energy and moving average detection unit 120. In the received energy and moving average detection unit 120, the supplied delay signal is further delayed by the shift register 121, and then the absolute value square calculator 122 calculates the absolute value square, and the A / D converter 105 The output is directly supplied to the absolute value square calculator 124 to calculate the square of the absolute value, and the difference between the two signals is obtained by the subtractor 123. The difference signal obtained by the subtracter 123 is supplied to the adder 125, and the output of the adder 125 is added to the signal delayed by one clock cycle by the delay circuit 126. In the shift register 121, processing for delaying the preamble signal by 3 slots (that is, delaying by 495 clock periods) is performed. As a result, the two absolute value square calculators 122 and 124 calculate signals having different timings of 6 slots. Will be done. The difference between the arithmetic outputs of the absolute value square calculators 122 and 124 is detected by the subtractor 123, and the output is supplied to the adder 125. The output of the adder 125 is delayed by one clock period by the delay circuit 126. The signal is added to the signal and the added output is used as a moving average signal. With this configuration, a moving average of received energy is obtained.

  The moving energy of the received energy and the received energy output from the moving average detector 120 is supplied to the adder 109 and added to the moving average of another branch (the configuration of another branch will be described later).

  Then, the output of the A / D converter 105 and the output of the shift register 108 are supplied to the selector 133 as a first set, and the output of the A / D converter 105 and the output of the shift register 106 are supplied to the second set. To the selector 133. Further, the output of the A / D converter 105 and the output of the shift register 107 are added by the adder 131, and the output of the shift register 106 and the output of the shift register 108 are added by the adder 132, whereby both adders are added. The added outputs 131 and 132 are supplied to the selector 133 as a third set.

  In the selector 133, one of the first set to the third set is selected according to the preamble pattern received by the receiver. Then, one of the two signals in the selected set is supplied to the correlator 134, and a correlation with a known preamble signal pattern is detected. The other of the two signals in the selected set is supplied to the correlator 135 to detect a correlation with a known preamble signal pattern.

  The outputs of the two correlators 134 and 135 are supplied to the complex multiplier 136 and subjected to complex multiplication, and the complex multiplied signal is supplied to the adder 137. The adder 137 adds the complex multiplication output of another branch.

  The output of the adder 137 is supplied to the moving average detection unit 140, and the moving average of the correlation detection signal is detected. The detected moving average signal is supplied to the divider 110, and the received energy and moving average detection are performed. The synchronization is performed by dividing the average value of the received energy output by the unit 109 so that the signal level is in a certain range, and supplying the output of the divider 110 to the synchronization detector 111 to determine the synchronization detection timing. Perform detection processing.

  Next, a branch configured by the reception system of the second antenna 201 will be described. The reception signal in the RF frequency band received by the second antenna 201 is obtained by using the carrier wave signal generated by the carrier wave signal generator 203. The converter 202 converts the frequency into a received baseband signal in the baseband. The frequency band received by the frequency converter 202 may be the same as or different from the frequency band received by the reception system of the first antenna 101. The reception frequency band selection process when the frequency bands are different will be described later. The received baseband signal is adjusted to a received signal at a predetermined level by an AGC (automatic gain control) circuit 204 and then sampled and converted into a digital signal by an A / D converter 205.

  The converted digital reception signal is delayed by shift registers 206, 207, 208 connected in series in a plurality of stages. Each shift register 206, 207, 208 functions as a delay circuit that delays one slot period (ie, 165 clock periods) of the received preamble signal.

  The output of the shift register 208 is supplied to the received energy and moving average detection unit 220. In the received energy and moving average detection unit 220, the supplied delay signal is further delayed by the shift register 221, and then the absolute value square calculator 222 calculates the absolute value square, and the A / D converter 205 The output is directly supplied to the absolute value square calculator 224 to perform the absolute value square calculation, and the difference between the two signals is obtained by the subtractor 223. The difference signal obtained by the subtractor 223 is supplied to the adder 225, and the output of the adder 225 is added to the signal delayed by one clock cycle by the delay circuit 226. In the shift register 221, processing for delaying the preamble signal by 3 slots (that is, delaying by 495 clock periods) is performed. As a result, the two absolute value square calculators 222 and 224 calculate signals having different timings of 6 slots. Will be done. The difference between the outputs of the absolute value square calculators 222 and 224 is detected by the subtractor 223, and the output is supplied to the adder 225. The output of the adder 225 is delayed by one clock period by the delay circuit 226. The signal is added to the signal and the added output is used as a moving average signal. With this configuration, a moving average of received energy is obtained.

  The moving energy of the received energy output from the received energy and moving average detector 220 is supplied to the adder 209 and added to the moving average of the branch connected to the first antenna 101.

  Then, the output of the A / D converter 205 and the output of the shift register 208 are supplied to the selector 233 as a first set, and the output of the A / D converter 205 and the output of the shift register 206 are supplied to the second set. To the selector 233. Further, the output of the A / D converter 205 and the output of the shift register 207 are added by the adder 231, and the output of the shift register 206 and the output of the shift register 208 are added by the adder 232. The added outputs of 231 and 232 are supplied to the selector 233 as a third set.

  In the selector 233, one of the first set to the third set is selected according to the preamble pattern received by the receiver. Then, one of the two signals of the selected set is supplied to the correlator 234, and the correlation with the known preamble signal pattern is detected. The other of the two signals in the selected set is supplied to the correlator 235 to detect a correlation with a known preamble signal pattern.

  The outputs of the two correlators 234 and 235 are supplied to the complex multiplier 236 and complex-multiplied. The complex-multiplied signal is supplied to the adder 237, and the complex multiplication of the branch connected to the first antenna 101 is performed. Add with signal.

  Regarding the signals supplied to the selectors 133 and 233 of each branch, as shown in FIG. 5, there are three signals of the first set a, the second set b, and the third set c already described in FIG. There are combinations, and any of the combinations is selected by the selectors 133 and 233 according to the received preamble signal pattern. Here, as shown in detail in FIG. 5, the first set a is selected when the received preamble signal pattern is TFC1 or TFC2, and the second set when the received preamble signal pattern is TFC3 or TFC4. When the set b is selected and the received preamble signal pattern is any one of TFC5 to TFC7, the third set c is selected, and two correlators 134, 135, or 234 connected to the selectors 133 and 233 are selected. A reception signal is supplied to 235.

  As the correlation detection signals of the two correlators 134, 135 or 234, 235, for example, as shown in FIG. 9, it has a maximum value when a preamble signal is detected. Returning to the description of FIG. 1, the correlation detection values of the two correlators 134, 135, 234, and 235 take one complex conjugate, and then complex multiply by the complex multiplier 136 or 236. By performing complex multiplication in this way, polarity inversion can be detected. The complex multiplication outputs of the two branches are added by the adder 137 and then supplied to the moving average detection unit 140 to detect the moving average of the correlation detection signal. As a configuration for detecting the moving average, a subtractor 142 detects a difference between a signal delayed by the shift register 141 and a signal not delayed by the shift register 141, and supplies the output of the subtractor 142 to the adder 143. Then, the output of the adder 143 is added to the signal delayed by one clock period by the delay circuit 144, and the added output is used as a moving average signal. Here, the shift register 141 is delayed for 32 clock periods.

  The moving average signal detected by the moving average detection unit 140 is supplied to the divider 110 and divided by a signal obtained by adding the reception energy of the two branches and the average value of the reception energy output by the moving average detection units 120 and 220. Is done.

  By performing the moving average process in this way, it is possible to reduce the influence of delay wave superposition due to multipath. In other words, if a delayed wave is superimposed on the data, the maximum value of the correlator output is not a single peak, but a plurality of peaks are generated, and the heights of the peaks also vary, making synchronization determination very difficult. . By performing the moving average process, a plurality of local maximum values can be bundled into one mountain, and variations in the height can be suppressed to be small, so that stable synchronization can be obtained. Here, the order of the moving average is to be optimized from the order of the multipath, the usage environment, and the device cost, and cannot be determined uniquely, but the example of FIG. 1 shows a preferred example.

  The received energy of each branch and the moving average detectors 120 and 220 calculate the average power of the observed data series, and use the square of the absolute value of the data series as an input, Average power is measured by taking a moving average in the section. For example, in the example of FIG. 1, a moving average of 6 slots (990 clock intervals) is performed. This is determined from various data observation patterns of the received preamble signal pattern. Of course, this section should also be optimized from the usage environment and the cost of the apparatus, and is not limited to the configuration of FIG.

  In this way, the data averaged from the outputs of the complex multipliers 136 and 236 of each branch is normalized (divided) by the average power, so that the synchronization determination is performed using the normalized data, and the synchronization is performed. Can be earned.

  In this example, the moving average of the received energy of each branch is added, and the complex multiplication output of each branch is added to obtain the moving average, and the synchronization detector 111 detects the synchronization. Good synchronization detection based on reception of each branch can be performed.

  Here, a case where the received preamble signal pattern is TFC1 or TFC2, as an example, FIG. 10 shows a detailed description of data calculated by the processing of each unit. In this case, as shown in FIGS. 10A and 10B, the correlator 134 and 135 (or the correlators 234 and 235) respectively have signal data without time delay and signal data delayed by three slots. Enter. As a result, each correlator output is output with a sharp peak as shown in FIGS. The peak shown in FIG. 10 also represents a delayed wave in consideration of multipath. FIG. 10E shows the waveform obtained by performing complex multiplication by taking one of the outputs of the complex conjugates. As shown in FIG. 10E, this output has many peaks due to multipath. This mountain group is averaged by moving average processing, and becomes a single peak as shown in FIG. After that, this data is normalized (divided) by the average power, and it is possible to obtain synchronization by making the synchronization determination using the normalized data.

Next, the synchronization determination process in this example will be described with reference to the flowchart of FIG. This synchronization determination algorithm has a two-stage configuration of a maximum value detection unit and a threshold comparison unit.
First, the buffer data and the initial value of the counter are set to zero. New data is acquired (step S11). The acquired data is compared with the data in the buffer (step S12), and if it is larger than the data stored in the buffer, it is replaced with the data in the buffer (step S13). If the data in the buffer does not change more than the predetermined number of times (MaxCount) with respect to the new data, it is recognized as the maximum value and enters the next threshold comparison (steps S14 and S15). In other words, if a maximum value is not observed in 32 sections after the data, it is recognized as a maximum value. If it is recognized as a local maximum, it becomes a candidate for synchronization.

  Next, it is determined whether or not the data recognized as the maximum value is synchronized (step S16). This determination is made based on whether or not it is larger than a predetermined threshold value. If it is larger than the threshold value, it is determined that the synchronization is made, and if not, the synchronization is not determined and the operation is continued. Return to the top-level flow and resume from acquiring new data.

  In this case, since it was recognized as a local maximum, it was not synchronized, so it is clear that even if a local maximum is recognized with a value smaller than this local maximum in future data, it is clear that it is not synchronized. It is necessary to exceed this maximum value. Therefore, the counter is reset, but the buffer data is not reset.

  In addition, in the algorithm shown in the flowchart of FIG. 6, there is a possibility that synchronization is detected a plurality of times. However, since how to use the synchronization depends on the design, it will not be described in detail here. Only need to be synchronized.

  Next, the process of synchronous detection in this way will be described in detail for each preamble pattern with reference to FIG. 7 and FIG.

  First, the process for acquiring the synchronization of the TFC1 and TFC2 patterns will be described with reference to FIG. In the case of these two patterns, the receiver receives data at a rate of once every three slots when receiving continuously at one specific frequency. As can be seen from Table 2, since only the last received data has a negative polarity and all other data have a positive polarity, synchronization is achieved by utilizing this change of positive to negative. That is, the result of correlation detection of the data of the two slots indicated by the last diagonal line in FIG. 7A is subjected to complex multiplication, and synchronization detection is performed from the complex multiplied value.

  Since the data received in this way is preamble data, a maximum value appears due to the correlation when passed through the correlator. FIG. 9 shows an example of an actual correlator output. Therefore, in this type, the maximum value appears once every three slots. Since only the last data has a negative polarity, only the slot of this portion has a negative maximum value.

  In order to detect a portion where positive changes to negative, for example, multiplication may be performed. Multiplication is positive by multiplying positive and positive by nature, but becomes negative by multiplying positive and negative, so if you multiply yourself and the correlator output one slot before, only the last result is negative. It becomes possible to detect the portion where the positive value changes to negative. The actual received data is a complex number, but mathematically it can be detected in the same way by replacing the multiplication with a complex multiplication. In this way, if the place where the output becomes negative is detected and the synchronization determination is made, the synchronization of the TFC1 and TFC2 patterns can be acquired.

  Next, a process for acquiring the synchronization of the TFC3 and TFC4 patterns will be described with reference to FIG. Also in the case of these two patterns, synchronization can be obtained by the same processing as the above-described TFC1 and TFC2 patterns. That is, as shown in FIG. 7B, the data is observed by repeating a pattern in which data is obtained continuously for 2 slots and then there is no 4-slot data. The data ends when the polarity of the data behind the last two observation data is inverted.

  Also in this case, first, a maximum value is obtained through a correlator, and then complex multiplication is performed. However, since the difference from the previous TFC1 and TFC2 is continuous when data comes, complex multiplication needs to be performed on data at a certain time and data one slot before. By doing in this way, it becomes possible to perform the same synchronization acquisition as in the case of the TFC 1 and 2 patterns.

  Next, a process for acquiring the synchronization of the patterns of TFC5, TFC6, and TFC7 will be described with reference to FIG. In this case as well, the basic idea is the same as in the other two cases. However, since the polarity inversion of the received data has occurred even in the middle, some contrivance is required. In this example, every other data is taken out from every other 4 slots, summed (added), and the result of the sum is subjected to complex multiplication (signal set c in FIG. 5). Thereby, the influence of polarity reversal that occurs in the middle can be eliminated, and a negative maximum value can be obtained correctly.

  FIG. 8 shows details when the synchronization of the patterns of TFC5, TFC6, and TFC7 is acquired. In the case of the patterns TFC5, TFC6, and TFC7, all the observed patterns are classified into four from timing a to timing d in FIG. For example, at timing a, complex multiplication is performed by taking the sum of odd-numbered slots and even-numbered slots. However, since the odd-numbered slots have different polarities, the sum is zeroed. On the other hand, the sum of the even numbers is a negative value, but if it is multiplied by 0, the result is 0. In this type of timing a, only an output of 0 is output.

  Next, in the case of the timing b type, the sum of the even-numbered units is now 0, so that the multiplication result is 0. In this timing b type, only 0 output is output. In addition, in the case of the timing c type, the sum of both odd-numbered and even-numbered ones is 0, so that the multiplication result is naturally 0. In this type of timing c, only 0 output is output. . Therefore, in the three timings a to c, the output becomes 0 even though the polarity inversion occurs, so that the synchronization detection is not performed in this portion, and a desired result is obtained. It will be.

  On the other hand, in the case of the type of timing d which is a pattern in which synchronization is detected, the sum of odd numbers becomes a negative maximum value, and the sum of even numbers becomes a positive value. Can be obtained. Therefore, when a pattern of the timing d type comes, that is, when the last synchronization is to be obtained, a negative value is correctly calculated, and it can be seen that synchronization can be acquired at the correct position.

  The above is the synchronization acquisition process corresponding to each of TFC1 to TFC7 in this example, and the only difference is that the time of the other party performing the complex multiplication is different. Accordingly, a plurality of shift registers are prepared in hardware, and the selector 133 shown in FIG. 1 selects which data and which data are extracted from the predetermined TFC and subjected to complex multiplication. Therefore, it becomes possible to correspond to each TFC.

In the configuration shown in FIG. 1, the moving average of the reception energy of each branch is added and the complex multiplication output of the correlator of each branch is added, and then the synchronization detection is performed. Instead of adding, the selection may be performed by the selector, and the synchronization may be detected by the selected signal.
That is, the configuration shown in FIG. 2 is a configuration in which the received signals of two branches are selected by the selector 112 provided in the preceding stage of the synchronization detector 111. The configuration of FIG. 2 will be described focusing on the differences from the configuration of FIG. 1. In the configuration of FIG. 2, the outputs of the two correlators 134 and 135 are multipliers as branches for processing the received signal of the first antenna 101. An output obtained by performing complex multiplication at 136 is detected by the moving average detection unit 140. The internal configuration of the moving average detector 140 is the same as that shown in FIG.

  Then, the moving average detected by the moving average detection unit 140 is supplied to the divider 110 and is divided by the moving average of the received energy and the received energy output by the moving average detection unit 120. The division output is supplied to the selector 112 as the output of the first branch.

  Then, as a branch for processing the reception signal of the second antenna 201, the moving average detection unit 240 detects an output obtained by performing complex multiplication of the outputs of the two correlators 234 and 235 by the multiplier 236. The internal configuration of the moving average detector 240 is the same as that of the moving average detector 140. That is, the difference between the signal delayed by the shift register 241 and the signal not delayed by the shift register 241 is detected by the subtractor 242, and the output of the subtractor 242 is supplied to the adder 243. The output is added to the signal delayed by one clock period by the delay circuit 244, and the added output is used as a moving average signal.

  Then, the moving average detected by the moving average detection unit 240 is supplied to the divider 210 and is divided by the moving average of the received energy and the received energy output by the moving average detection unit 220. The division output is supplied to the selector 112 as the output of the second branch. The selector 112 selects a signal that has been successfully received, and supplies the selected signal to the synchronization detector 111 for synchronization detection. Even with the configuration shown in FIG. 2, it is possible to perform good synchronization detection using reception results of a plurality of branches.

  Moreover, it is good also as a structure which receives and processes the signal of a temporally different timing in several branches. FIG. 3 is a diagram showing a configuration example in this case. The configuration shown in FIG. 3 will be described with a focus on the differences from the configuration shown in FIG. 1. The complex multiplication output of the complex multiplier 136 of one branch is supplied to the adder 137 and the complex multiplier 236 of the other branch is supplied. Are output to the adder 137 after being delayed by the shift register 237. In the shift register 237, for example, the period is delayed for a period corresponding to one cycle of the synchronization signal. The output of the adder 137 is supplied to the moving average detector 140 to detect the moving average, and the output is supplied to the divider 110.

  For the moving average of the received energy of each branch, the adder 109 adds the received energy of each branch and the outputs of the moving averages 120 and 220. Then, the moving average of the received energy of each branch added by the adder 109 is supplied to the divider 110, the output of the moving average detector 140 is divided, and the divided signal is supplied to the synchronization detector 111. Synchronize detection. Even with the configuration shown in FIG. 3, it is possible to perform good synchronization detection using reception results of a plurality of branches.

  Further, in the case where a plurality of branches receive signals at different timings and process them, one of the outputs of the two branches is delayed by a shift register in the configuration shown in FIG. It is good. That is, for example, as shown in FIG. 4, the output of the divider 110 of one branch is supplied to the selector 112 as it is, the output of the divider 210 of the other branch is supplied to the selector 112, and the output of the shift register 211 is supplied to the selector 112. The selector 112 selects one of the outputs. In the shift register 211, for example, the period is delayed for a period corresponding to one cycle of the synchronization signal. Even with this configuration, it is possible to perform good synchronization detection using reception results of a plurality of branches.

  Next, in the case where the two branches described so far are prepared and received and the process of detecting the synchronization signal is performed, an example of the process of receiving the different frequency bands in the two branches and performing the synchronization detection will be described. In a standby state in which a receiver waits for a transmission signal to be transmitted, it may be necessary to receive in a plurality of different frequency bands. That is, for example, as shown in FIG. 11, the frequency band received by the frequency converter 102 (one branch) connected to the first antenna 101 is band A, and the frequency converter 202 (connected to the second antenna 201) The reception frequency is set by the RF controller 99 so that the frequency band received by the other branch) is band B. Based on the output of the frequency converter 102 and the output of the frequency converter 202, the synchronization circuit 100 executes synchronization detection processing. The synchronization circuit 100 performs synchronization detection with any one of the configurations shown in FIGS. 1, 2, 3, and 4, for example.

  Then, when waiting in a plurality of frequency bands as described above, it may be made to correspond to frequency hopping in which the transmission frequency changes at a constant period. That is, for example, it is assumed that three bands of band A, band B, and band C are prepared as transmission frequency bands, and frequency hopping using each band alternately is performed. At this time, in one branch (first receiving system), as shown in FIG. 12A, standby is performed in band A, and in synchronization with the start of frequency hopping, band A → band B → Change band C → band A →. In the other branch (second receiving system), as shown in FIG. 12B, standby is performed in band B, and in synchronization with the start of frequency hopping, band A → band B → band C → Change band A → ... and receive the same frequency during frequency hopping. As shown in FIG. 12, synchronization detection can be performed better by receiving different frequency bands in the two systems only during standby. In the case of performing frequency hopping in this way, the same frequency band may be received by two branches even when waiting.

Even when the transmission signal is a multi-carrier signal composed of a plurality of sub-carriers and only a specific sub-carrier of the multi-carrier signal transmitted in a specific frequency band has no transmission power. It can receive and detect synchronization.
Hereinafter, a processing example in this case will be described. As shown in FIG. 13A, a normal multicarrier transmission signal is transmitted on all the subcarriers that are to transmit data. FIG. 13A shows band A (center frequency FA), band B (center frequency FB), and band C (center frequency FC). Here, for example, as shown in FIG. 13B, it is assumed that there are subcarriers of subcarrier I in band A to subcarrier I + J that do not transmit data signals.

When subcarriers having no transmission power as shown in FIG. 13B are present in a specific band, when the reception wait state is performed in the band A, the synchronization result is shifted.
The process for avoiding the deviation of the synchronization result is shown in the flowchart of FIG. In this example, band A is first received by one branch, band B is received by the other branch, and reception standby is performed (step S21). Then, after acquiring synchronization, the synchronization results in band A and band B are compared (step S22). Here, when there is a subcarrier with no transmission power in either band, a difference occurs in the result. If there is a difference, use the better result. That is, when the synchronization acquisition result of band A is satisfactory, reception processing such as reception timing setting is performed using the synchronization acquisition result of band A (step S23). If the synchronization acquisition result of band B is good, reception processing such as reception timing setting is performed using the synchronization acquisition result of band B (step S24). Further, when there is almost no difference between the synchronization results in band A and band B, it is determined that there is no subcarrier having no transmission power, and both synchronization results are used after correcting errors due to band differences ( Step S25).

  As an example in which there are a plurality of bands waiting for reception, a case where there is an overlap in band groups can be considered. That is, for example, as shown in FIG. 15, six transmission bands of band # 1 to band # 6 are prepared, and band group # 1 performs frequency hopping using band # 1 to band # 3, Group # 2 is configured to perform frequency hopping using bands # 4 to # 6, and band group # 3 is configured to perform frequency hopping using bands # 3 to # 5. Suppose that the same preamble signal is used in a group. Then, for example, as shown in FIG. 16, it is assumed that band group # 1 and band group # 3 exist in adjacent areas, and standby is performed in an area where both areas overlap.

  In such a case, for example, if reception standby is performed in band # 3, synchronization is acquired by the preamble of band group # 1. This starts reception. A processing example for avoiding this is shown in the flowchart of FIG. In this example, first, reception of band # 3 is performed on one branch, reception of band # 4 is performed on the other branch, and reception standby is performed (step S31). Then, after acquiring synchronization, the synchronization results in band # 3 and band # 4 are compared (step S32). Here, when only the synchronization acquisition result of band # 3 is good, it is determined as band group # 1, and reception processing is performed in synchronization with the frequency hopping of band group # 1 (step S33). When only the synchronization acquisition result of the band # 4 is good, it is determined as the band group # 2, and reception processing is performed in synchronization with the frequency hopping of the band group # 2 (step S34). Further, if there is almost no difference in the synchronization result between band # 3 and band # 4, it is determined as band group # 3, and reception processing is performed in synchronization with the frequency hopping of band group # 3 (step S35). .

  By using reception results from a plurality of branches in this way, better standby is possible.

  In the reception configurations (synchronization detection configurations) shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, the moving average of the correlation values multiplied by the complex is divided by the moving average of the received energy. The process of dividing by the moving average of energy may be omitted. 18, 19, and 20 are configurations in which the received energy and moving average detection units 120 and 220 and the dividers 110 and 210 are excluded from the synchronization detection configurations illustrated in FIGS. 1, 2, and 3, respectively. Is. Other parts are configured in the same manner as in FIGS. 1, 2, and 3. The configuration of FIG. 4 excluding the reception energy and moving average detection units 120 and 220 is also possible although not shown.

  When the gain of the received signal is stable by processing in the automatic gain control circuit (so-called AGC circuit) provided in the receiving system, the moving average of the received energy shown in FIGS. 18, 19 and 20 is used. Even if the configuration does not divide by 1, the synchronization can be detected well.

  In addition, the received energy and moving average detectors 120 and 220 shown in FIGS. 1, 2, and 3 are signals obtained by simply dividing the output of the shift register 108 or 208 by a constant signal serving as a reference. It is good also as a structure which estimates an average.

  Further, in the embodiments described so far, the description has been given as an example applied to a receiver in which the circuit configuration shown in FIGS. 1 and 2 is assembled. For example, a part or all of the same synchronization detection processing method is programmed. And may be performed by executing the program.

In the above-described embodiment, MB-OFDM defined in the IEEE 802.15.3 standard is used.
This method is applied when receiving a wireless signal of the system, but may be applied to reception of a wired signal, and similarly applicable to reception processing of other communication systems that detect a synchronization signal from a plurality of synchronization signal patterns. is there.

It is a block diagram which shows the example of a receiving structure (example 1) by one embodiment of this invention. It is a block diagram which shows the example of a receiving structure (example 2) by one embodiment of this invention. It is a block diagram which shows the example of a receiving structure (example 3) by one embodiment of this invention. It is a block diagram which shows the example of a receiving structure (example 4) by one embodiment of this invention. It is the block diagram which showed the example of the selector by one embodiment of this invention. It is the flowchart which showed the example of the synchronous detection process by one embodiment of this invention. It is explanatory drawing which shows the example of a detection of the signal of each pattern by one embodiment of this invention. It is explanatory drawing which showed the reception state in each timing at the time of the synchronous signal reception of TFC5, TFC6, and TFC7 by one embodiment of this invention. It is a wave form diagram which shows the example of the detection waveform by one embodiment of this invention. It is a timing diagram which shows the example of a detection by one embodiment of this invention. It is a principle figure for demonstrating the reception standby state by one embodiment of this invention. It is a timing diagram which shows the example of reception frequency setting by one embodiment of this invention. It is a wave form diagram which shows the example of the transmission signal received in one embodiment of this invention. It is the flowchart which showed the synchronous process example (example 1) by one embodiment of this invention. It is explanatory drawing which shows the example (example of a band) of a setting with an overlap in a band group. It is explanatory drawing which shows the example (example of an area) of a setting with an overlap in a band group. It is the flowchart which showed the synchronous process example (example 2) by one embodiment of this invention. It is a block diagram which shows the example of a receiving structure (example 1) by other embodiment of this invention. It is a block diagram which shows the example of a receiving structure (example 2) by other embodiment of this invention. It is a block diagram which shows the example of a receiving structure (example 3) by other embodiment of this invention. It is a block diagram which shows the example of a conventional receiving structure. It is explanatory drawing which shows the example of the transmission pattern of a preamble signal. It is a block diagram which shows the example of a conventional synchronous detection structure.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... 1st antenna, 102 ... Frequency converter, 103 ... Carrier wave signal generator, 104 ... AGC circuit, 105 ... A / D converter, 106, 107, 108 ... Shift register, 109 ... Adder, 110 ... Divider , 111 ... synchronization detector, 112 ... selector, 120 ... received energy and moving average detector, 131, 132 ... adder, 133 ... selector, 134, 135 ... correlator, 136 ... complex multiplier, 137 ... adder, DESCRIPTION OF SYMBOLS 138 ... Synchronous detector, 140 ... Moving average detection part, 201 ... 2nd antenna, 202 ... Frequency converter, 203 ... Carrier wave signal generator, 204 ... AGC circuit, 205 ... A / D converter, 206, 207, 208 ... shift register, 220 ... received energy and moving average detector, 231,232 ... adder, 233 ... selector, 234,235 ... correlator, 36 ... complex multiplier

Claims (16)

A reception method of receiving the transmission signal by performing synchronization detection processing of the reception signal based on a known synchronization signal included in the transmission signal,
As the known synchronization signal, one unit of synchronization signal is repeatedly transmitted for a predetermined period, and there are a plurality of transmission frequency patterns set for each unit and a plurality of signal polarity patterns set for each unit. In case of receiving method,
Provided with a plurality of branch receiving systems that individually obtain received signals,
In each branch, the reception signal is delayed by a plurality of stages in the unit cycle, and a plurality of reception signals at at least two delay positions are extracted from the reception signals delayed by the plurality of stages in different combinations. A received signal of at least two delay positions in a combination selected according to the received synchronization signal pattern,
Correlation detection is performed in each branch from each of the selected received signals,
A receiving method, wherein a moving average is obtained from a signal obtained by complex multiplication of a correlation detection signal in each branch and the synchronization signal is detected. The receiving method according to claim 1,
In each branch, the received energy and moving average are obtained from the received signal, the moving average value obtained from the complex multiplication signal is divided by the obtained value, and the synchronization signal is detected from the divided signal. A receiving method characterized by the above. The receiving method according to claim 2,
Each branch listens for reception in a different frequency band,
The reception energy and the moving average are obtained from the received signal of each branch, the moving average value obtained from the complex multiplication signal is divided by the obtained value of each branch, and the synchronization signal is detected from the divided signal. A receiving method characterized in that it is performed. The receiving method according to claim 1,
The reception method of each branch receives a different frequency and detects a synchronization signal from a reception signal of a branch that has been successfully received. The receiving method according to claim 1,
The receiving system of each branch receives a different frequency and synthesizes the received signals of each branch to detect a synchronization signal. The receiving method according to claim 1,
The transmission signal is a transmission signal that performs frequency hopping to periodically change the transmission frequency,
The reception method according to claim 1, wherein each branch receives a signal having a different transmission frequency from among a plurality of transmission frequencies that change due to the frequency hopping, and waits for reception. The receiving method according to claim 6, wherein
The signal of each branch subjected to the complex multiplication is shifted and added for a period corresponding to a period in which the transmission frequency changes due to the frequency hopping, and a moving average of the added signal is obtained to perform the synchronization signal detection. Characteristic reception method. The receiving method according to claim 6, wherein
A reception method comprising: comparing synchronization signal detection results of reception signals having different transmission frequencies received in each branch to determine a band group performing the frequency hopping. A receiver that receives the transmission signal by performing synchronization detection processing of the reception signal based on a known synchronization signal included in the transmission signal,
As the known synchronization signal, one unit of synchronization signal is repeatedly transmitted for a predetermined period, and there are a plurality of transmission frequency patterns set for each unit and a plurality of signal polarity patterns set for each unit. In the receiver in case
Each branch has multiple branches that can be set individually.
Delay means for delaying a received signal by a plurality of stages in the unit period;
A plurality of received signals of at least two delay positions are extracted from the received signals delayed by a plurality of stages by the delay means in different combinations, and selected from the received signals of the plurality of combinations according to the received synchronization signal pattern Selecting means for selecting received signals of at least two delay positions of the combination;
A plurality of correlation detection means for performing correlation detection from each received signal selected by the selection means;
Complex multiplication means for performing complex multiplication on the correlation detection signals detected by the plurality of correlation detection means,
Furthermore, a moving average detecting means for obtaining a moving average from the signal complex-multiplied by the complex multiplying means of each branch;
A receiver comprising: synchronization detection means for detecting a synchronization signal from the moving average detected by the moving average detection means. The receiver of claim 9, wherein
Each branch comprises reception energy and moving average calculation means for calculating reception energy and moving average from the received signal,
Dividing means for dividing the detection value of the moving average detection means by the received energy of each branch and the value calculated by the moving average calculation means and sending the divided signal to the synchronization detection means A receiver characterized by. The receiver of claim 10, wherein
For each reception means of each branch, perform reception standby in different frequency bands,
Dividing means for dividing the detection value of the moving average detection means by the received energy of each branch and the value calculated by the moving average calculation means, and sending the divided signal to the synchronization detection means A receiver characterized by. The receiver of claim 9, wherein
For each reception means of each branch, perform reception standby in different frequency bands,
A receiver comprising: a selector that selects a reception signal of a well-received branch among the signals received by the reception frequency setting unit of each branch and sends the selected signal to the synchronization detection unit. The receiver of claim 9, wherein
For each reception means of each branch, perform reception standby at a different frequency,
A receiver comprising: combining means for combining the received signals of the branches and sending the combined signal to the synchronization detecting means. The receiver of claim 9, wherein
A receiver characterized in that reception is performed for each reception means of each branch with a different reception frequency setting in a frequency hopping state. The receiver of claim 14, wherein
Shift means for shifting the signal of each branch subjected to the complex multiplication for a period corresponding to a cycle in which a transmission frequency changes by the frequency hopping;
Adding means for adding the signal of the branch shifted by the shift means and the signal of the branch not shifted;
A moving average calculating means for obtaining a moving average from the output of the adding means,
The receiver characterized in that the synchronization detection means detects a synchronization signal from the output of the moving average calculation means. The receiver of claim 14, wherein
A receiver comprising: a discriminating unit that discriminates a band group performing frequency hopping by comparing synchronization signal detection results of received signals having different transmission frequencies received in each branch.

Images