JP2008042673A - Photoelectric conversion device and driving method thereof - Google Patents

Abstract

For example, a photoelectric conversion device capable of suppressing vertical stripe noise in an image is provided.
A photoelectric conversion device according to a first aspect of the present invention includes a photoelectric conversion unit that converts light into a charge, a charge conversion unit that converts the charge into a potential, and the charge from the photoelectric conversion unit to the charge. Apply at least three voltages to a transfer unit that transfers to the conversion unit, an amplification unit that reads a signal based on the potential of the charge conversion unit, a reset transistor that resets the potential of the charge conversion unit, and a gate of the reset transistor And a difference circuit that performs a difference between a signal based on the reset potential of the charge conversion unit and a signal based on the potential of the charge conversion unit to which the charge has been transferred.
[Selection] Figure 4

Description

  The present invention relates to a photoelectric conversion device and a driving method thereof.

  A case where photographing is performed using a photoelectric conversion device that performs CDS (Correlated Double Sampling) will be described below. When a very bright subject exists in the imaging region, a strong light image is formed on the photoelectric conversion unit of the corresponding pixel. In the photoelectric conversion unit, charges corresponding to the intensity of the light are generated. In the period when the charge conversion unit (floating diffusion) adjacent to the photoelectric conversion unit is reset, the photoelectric conversion unit and the charge conversion unit are electrically disconnected. Even in this case, in a pixel on which very strong light is imaged, charges may overflow from the photoelectric conversion unit to the charge conversion unit. As a result, the potential of the charge conversion unit may attenuate from the reset level (approach the base level) during the noise readout period.

  Further, normally, the photoelectric conversion unit is not shielded from light, whereas the charge conversion unit is shielded from light. Even in this case, part of the light irradiated to the photoelectric conversion unit may leak into the charge conversion unit. Thereby, the potential (noise potential) of the charge conversion unit in the noise readout period may attenuate from the reset level.

  When the noise potential is attenuated from the reset level, the potential (noise output potential) output from the amplifying unit that amplifies the signal based on the potential of the charge conversion unit to the vertical signal line is also attenuated in the noise reading period. As a result, it becomes difficult to make a large difference between the potential of the vertical signal line (signal output potential) and the noise output potential in the signal readout period, and the dynamic range of the vertical signal line is compressed. As a result, an optical signal output from a pixel that has been exposed to strong light is attenuated, and a phenomenon occurs in which the gradation of the pixel sinks to a black tone (hereinafter referred to as a high luminance black sink phenomenon).

  For example, when the sun is photographed, the central portion of the sun becomes a black dot, resulting in an unnatural image. This problem can be solved for still images by providing a mechanical shutter between the subject and the photoelectric conversion unit. Even when taking a still image, an inexpensive camera often omits the mechanical shutter, so the high-intensity black sun phenomenon may not be suppressed for a still image.

  Also, using a mechanical shutter together with moving image shooting is a great disadvantage in securing the exposure time and frame speed, and therefore is not feasible. As a result, the high-luminance black sun phenomenon may not be suppressed for moving images.

On the other hand, a method of clipping the potential of the vertical signal line has been proposed (for example, see Patent Document 1).
JP 2004-222273 A

  In the technique of Patent Document 1, a clip transistor is provided that clips the potential of the vertical signal line during a noise readout period. Accordingly, even when strong light is irradiated on the photoelectric conversion unit, the potential of the vertical signal line can be prevented from dropping below the clip potential during the noise readout period, and the high-luminance black sun phenomenon can be suppressed.

  However, in the technique of Patent Document 1, the threshold value of the clip transistor in one column tends to be different from the threshold value of the clip transistor in another column due to manufacturing variation of the clip transistor. For example, in a column in which the threshold value of the clip transistor is higher than the threshold value of the clip transistor in the other column, the vertical signal line in that column is clipped to a clip potential lower than the vertical signal line in the other column. Alternatively, for example, in a column in which the threshold value of the clip transistor is lower than the threshold value of the clip transistor in the other column, the vertical signal line in that column is clipped to a clip potential higher than the vertical signal line in the other column. As a result, the noise output potential output via the vertical signal line tends to vary from column to column, and the image signal obtained by CDS as the difference between the noise output potential and the signal output potential also tends to vary from column to column. For this reason, vertical streak noise may appear on an image obtained by photoelectric conversion.

  An object of the present invention is to provide a photoelectric conversion device that can suppress vertical stripe noise in an image while suppressing, for example, a high-luminance black sun phenomenon.

  The photoelectric conversion device according to the first aspect of the present invention includes a photoelectric conversion unit that converts light into an electric charge, a charge conversion unit that converts the electric charge into an electric potential, and the charge transferred from the photoelectric conversion unit to the charge conversion unit. A transfer unit, an amplification unit that reads a signal based on the potential of the charge conversion unit, a reset transistor that resets the potential of the charge conversion unit, and a control unit that applies at least three voltages to the gate of the reset transistor; And a difference circuit for differentiating a signal based on the reset potential of the charge conversion unit and a signal based on the potential of the charge conversion unit to which the charge has been transferred.

  In the photoelectric conversion device according to the first aspect of the present invention, for example, vertical streak noise in an image can be suppressed.

  A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a configuration diagram of a photoelectric conversion apparatus according to the first embodiment. FIG. 2 is a configuration diagram of the pixel cell. FIG. 4 is a waveform diagram showing the operation of the photoelectric conversion device. Here, the case where the transistor is an NMOS (N-channel MOS transistor) will be described, but the same effect as in this embodiment can be obtained even when the transistor type and the polarity of the pulse are reversed.

  As shown in FIG. 1, the photoelectric conversion device 100 includes a plurality of pixel cells 101, 111, 121, a plurality of constant current sources 155, a plurality of vertical signal lines L1, a vertical scanning circuit (control unit) 170, and a horizontal scanning circuit 180. Prepare.

  The pixel cells 101, 111, 121 are arranged two-dimensionally (in the row direction and the column direction). A vertical scanning circuit 170 is disposed in the vicinity of the end in the column direction and a horizontal scanning circuit 180 is disposed in the vicinity of the end in the row direction with respect to the arranged two-dimensional region such as the pixel cell 101. . A vertical signal line L1 is connected to the pixel cells 101, 111, and 121 arranged in the column direction for each column. A constant current source 155 and an output line L4 are connected to each vertical signal line L1. The arrangement of the pixel cells 101 shown in FIG. 1 is an example, and is not limited to 3 rows and 4 columns.

  The vertical scanning circuit 170 supplies a control signal (for example, a reset signal Res and a transfer signal Tx) to each pixel cell 101 and the like. On the other hand, the horizontal scanning circuit 180 sequentially reads out signals (output signals) output from the pixel cells 101 and the like via the vertical signal line L1 and outputs them to the output line.

  The constant current source 155 includes a transistor, for example. A gate voltage VG common to a plurality of columns is applied to the gate of the transistor via a gate line L2. A ground line L3 common to a plurality of columns is connected to the source of the transistor of the constant current source 155.

  The output line L4 connects the vertical signal line L1 and the output terminal 159. A CDS circuit 160 (see FIG. 2) is connected to the end of the output terminal 159.

  Next, a detailed configuration and operation of the pixel cell 101 will be described. The same applies to the other pixel cells 111 and 121.

  As shown in FIG. 2, the pixel cell 101 includes a photodiode (photoelectric conversion unit) 102, a transfer transistor (transfer unit) 104, a reset transistor 105, a floating node (charge conversion unit) FN, and an amplification transistor (amplification unit) 106. Including.

  The photodiode 102 has a cathode connected to the ground potential GND and an anode connected to the transfer transistor 104. The photodiode 102 converts received light into electric charge by photoelectric conversion and accumulates it.

  The transfer transistor 104 has a source connected to the photodiode 102 and a drain connected to the floating node FN. For example, the photodiode 102 may also serve as the source of the transfer transistor 104. A transfer signal Tx is supplied to the gate of the transfer transistor 104. The transfer transistor 104 is turned off in the noise reading period in response to the transfer signal Tx, but is turned on in the signal reading period. When the transfer transistor 104 is turned ON, the charge stored in the photodiode 102 is transferred to the floating node FN.

  The floating node FN forms a parasitic capacitance 103 with the ground potential GND. The floating node FN is connected to the source of the reset transistor 105 and the gate of the amplification transistor 106. The floating node FN converts the charge into a signal potential and supplies the signal potential to the amplification transistor 106.

  The amplification transistor 106 has a gate connected to the floating node FN, a drain connected to the power supply 120, and a source connected to the vertical signal line L1. The amplification transistor 106 amplifies the output potential of the floating node FN and outputs it to the vertical signal line L1. Here, the amplification transistor 106 is connected to the constant current source 155 via the vertical signal line L1, and performs a source follower operation. The potential of the vertical signal line L1 is transmitted to the output terminal 159 via the output line L4. The potential of the vertical signal line L1 is read from the output terminal 159 by the CDS circuit 160 (see FIG. 2).

  The reset transistor 105 has a source connected to the floating node FN and a drain connected to the power source 120. The reset transistor 105 is supplied with a reset signal Res at its gate. The reset transistor 105 controls the potential of the floating node FN according to the reset signal Res.

  Here, row selection is performed by controlling the potential of the floating node FN. The potential of the floating node FN is controlled by controlling the potential of the gate of the reset transistor 105. That is, row selection is performed by the reset signal Res (see FIG. 4).

  Specifically, a low voltage (VresL) is applied to the power supply 120, and a high voltage (first voltage) VH is applied to the reset transistors 105 and the like in all rows. As a result, a low voltage (VresL) is written to the floating nodes FN of all rows.

  Next, a high voltage (VresH) is applied to the power supply 120, and a high voltage VH is applied as the reset signal Res to the gate of the reset transistor 105 in the selected row. On the other hand, a low voltage (third voltage) VL is applied as the reset signal Res to the gates of the reset transistors 105 in the unselected rows. As a result, only the reset transistor 105 in the selected row is turned on, and the potential VresH (or VH−Vt) is written only in the floating node FN in the selected row. Here, Vt is a threshold value of the reset transistor 105.

  With the above operation, only the potential of the floating node FN in the selected row is reset, and the potential of the vertical signal line L1 is determined by the source follower operation of the amplification transistor 106 in the selected row.

  That is, the reset transistor 105 resets the potential (noise potential) of the floating node FN during the noise readout period. The amplification transistor 106 outputs a signal obtained by amplifying the noise potential to the vertical signal line L1 as a noise output potential. The noise output potential is transmitted to the output terminal 159 via the output line L4.

  Further, the amplification transistor 106 outputs a signal obtained by amplifying the potential (signal potential) of the floating node FN in the signal readout period as a signal output potential. The signal output potential is transmitted to the output terminal 159 via the output line L4.

  The CDS circuit 160 includes a transistor 161, a storage capacitor 162, a transistor 163, and a storage capacitor 164. The transistor 161 has its source connected to the vertical signal line L 1 and its drain connected to the storage capacitor 162. The transistor 161 is supplied with the sample hold signal S / H (N) at its gate. The transistor 163 has a source connected to the vertical signal line L1 and a drain connected to the storage capacitor 164. The sample hold signal S / H (S) is supplied to the gate of the transistor 163.

  The CDS circuit 160 reads the potential of the vertical signal line L1 from the output terminal 159. That is, the transistor 161 and the storage capacitor 162 sample and hold the potential of the vertical signal line L1 (noise output potential) in the noise readout period. The transistor 163 and the storage capacitor 164 sample and hold the potential (signal output potential) of the vertical signal line L1 in the signal readout period. Then, the difference between the noise output potential and the signal output potential is taken (not shown). An example of a circuit that takes this difference is a differential amplifier. Further, the CDS circuit 160 does not have a transistor and a storage capacitor and may be a clamp circuit, and can be selected as appropriate. Further, although the CDS circuit is connected after the output terminal 159, this CDS circuit may be arranged on each vertical signal line L1.

  Next, the detailed configuration and operation of the vertical scanning circuit 170 will be described with reference to FIG. FIG. 3 is a configuration diagram of the vertical scanning circuit.

  The vertical scanning circuit 170 includes transfer gates 171 to 174 and input terminals 175 to 178. The transfer gates 171 to 174 are configured to receive a control signal (not shown).

  First, one of the transfer gates 171 to 173 is selectively turned on at a predetermined timing. When the transfer gate 171 is turned on, the high voltage VH input to the input terminal 175 is set to the reset signal Res. When the transfer gate 172 is turned on, the intermediate voltage VM input to the input terminal 176 is set to the reset signal Res. When the transfer gate 173 is turned on, the low voltage VL input to the input terminal 177 is set to the reset signal Res. Thus, any potential selected from at least three potentials can be supplied to the gate of the reset transistor 105 as the reset signal Res.

  On the other hand, the transfer gate 174 is turned on at a predetermined timing. When the transfer gate 174 is turned on, the high voltage VH input to the input terminal 178 is set to the transfer signal Tx. Thereby, the high voltage VH can be supplied to the gate of the transfer transistor 104 as the transfer signal Tx.

  The operation of the photoelectric conversion device (control method of the photoelectric conversion device) will be described with reference to FIG. In FIG. 4, the selection signal Res, the sample hold signal S / H (N), the transfer signal Tx, and the sample hold signal S / H (S) are all supplied by the vertical scanning circuit 170. FIG. 4 is a waveform diagram showing the operation of the photoelectric conversion device. In FIG. 4, the period from timing T2 to T5 is referred to as a noise readout period NP. A period after timing T5 is referred to as a signal readout period SP.

  In the period of timing T21 to T22, a low voltage (VresL) is applied to the power supply 120, and the high voltage (first voltage) VH is applied to the reset transistors 105 and the like in all rows by the vertical scanning circuit 170. As a result, a low voltage (VresL) is written to the floating nodes FN of all rows.

  In the period of timing T22 to T1, the potential of the power source 120 is switched from a low voltage (VresL) to a high potential (VresH).

  In the period of timing T1 to T2, a high potential (VresH) is applied to the power supply 120, and the vertical scanning circuit 170 applies a high voltage VH as the reset signal Res to the gate of the reset transistor 105 in only the selected row. On the other hand, the low voltage VL is applied as the reset signal Res by the vertical scanning circuit 170 to the gates of the reset transistors 105 in the unselected rows. Thereby, for example, the potential VresH (or VH−Vt) is written only in the floating node FN of the selected row.

  At timing T2, the vertical scanning circuit 170 changes the reset signal Res supplied to the gate of the reset transistor 105 in the selected row from the high voltage VH to the intermediate voltage (second voltage) VM. As a result, the reset transistor 105 in the selected row is turned off because the gate-source voltage becomes lower than the threshold value. On the other hand, the low voltage VL is still applied as the reset signal Res to the gates of the reset transistors 105 in the unselected rows by the vertical scanning circuit 170.

  Here, suppose a case where strong light is applied to the photodiode 102 and electric charge leaks from the photodiode 102 to the floating node FN. At this time, the potential of the floating node FN starts to decrease from the reset level VH-Vt. However, before the potential of the floating node FN reaches the ground potential GND, the reset transistor 105 is turned on because the gate-source voltage becomes equal to or higher than the threshold value. Thus, the reset transistor 105 limits the decrease in the potential of the floating node FN by clipping the potential of the floating node FN. That is, the vertical scanning circuit 170 limits the decrease in the potential of the floating node FN via the reset transistor 105 (via the reset signal Res). Specifically, the reset transistor 105 clips the decrease in the potential of the floating node FN with the clipping potential VM−Vt. This suppresses the potential of the floating node FN from dropping below the clip potential VM-Vt.

  At timing T3, the sample hold signal S / H (N) is activated, and the transistor 161 conducts the source and drain to detect the potential of the vertical signal line L1 (noise output potential) and to hold capacitance. Output to 162. Here, the noise output potential is the potential of the vertical signal line L1 in the noise readout period NP.

  At timing T4, the signal S / H (N) is deactivated, and the transistor 161 blocks the source and the drain. As a result, the storage capacitor 162 holds the potential (noise output potential) of the vertical signal line L1.

  At timing T5, the reset signal Res supplied to the gates of the reset transistors 105 in the selected row changes from the intermediate voltage VM to the lower potential (second voltage) VL. On the other hand, the low voltage VL is still applied as the reset signal Res to the gates of the reset transistors 105 in the unselected rows. As a result, the reset transistors 105 in the selected row are turned off if they are turned on, and are kept off if they are turned off. Note that the second voltage (low voltage VL) is closer to the base level (for example, the ground potential GND) than the first voltage (high voltage VH).

  At timing T6, the transfer signal Tx is activated, and the transfer transistor 104 makes the source and drain conductive, and transfers the charge accumulated in the photodiode 102 to the floating node FN.

  At timing T7, the transfer signal Tx is deactivated, and the transfer transistor 104 cuts off the source and the drain.

  At timing T8, the signal S / H (S) is activated, and the transistor 163 of the CDS circuit 160 conducts the source and the drain to detect the potential (signal output potential) of the vertical signal line L1. The data is output to the storage capacitor 164. Here, the signal output potential is the potential of the vertical signal line L1 in the signal readout period SP.

  At timing T9, the signal S / H (S) is deactivated, and the transistor 163 blocks the source and the drain. As a result, the storage capacitor 164 holds the potential (signal output potential) of the vertical signal line L1.

  Then, the CDS circuit 160 calculates the difference between the noise output potential held in the holding capacitor 162 and the signal output potential held in the holding capacitor 164. The CDS circuit 160 outputs the calculation result as an image signal.

  As described above, the potential of the floating node is clipped for each pixel without providing a clipping circuit for each vertical signal line. Thereby, since the high-intensity black sun phenomenon can be suppressed for each pixel, it can be suppressed that the noise becomes the same for each column. As a result, vertical streak noise in an image obtained by photoelectric conversion can be suppressed. Therefore, a high-quality image can be obtained even at high luminance.

  Note that the high voltage VH in FIG. 4 may be the same potential as the power supply 120. The low voltage VL may be the same potential as the ground potential GND.

  The intermediate voltage VM is set to an appropriate value between the high voltage VH and the low voltage VL. For example, the intermediate voltage VM is set to a potential at which the gate-source voltage of the reset transistor 105 is less than the threshold value Vt when the potential of the floating node FN is at the reset level (potential VH−Vt). Moreover, the intermediate voltage VM is set to a value that does not compress the dynamic range of the vertical signal line L1.

A low voltage VLa may be applied to the gate of the reset transistor 105 in the selected row as the reset signal Res in the signal read period SP. The low voltage VLa may be a potential different from the low voltage VL and capable of clipping the floating node. As a result, even when an amount of light that saturates the vertical signal line L1 is irradiated by the optical signal, the operating range of the constant current source 155 in the optical signal readout period SP is reduced due to the clipping effect of the floating node FN by the low voltage VLa. Deviation can be prevented. As a result, it is possible to suppress a phenomenon (smear phenomenon in the CMOS sensor) in which the gradation of the pixel cell adjacent in the row direction approaches the black tone with respect to the pixel cell in which the high-luminance black sun phenomenon has occurred. That is, horizontal streak noise can be suppressed in the photoelectrically converted image. (Details of the smear phenomenon in the CMOS sensor are described in Japanese Patent Laid-Open No. 2001-230974.)
Each pixel cell 101 or the like may be a system further including a selection transistor instead of the 3-transistor system.

  The clip potential VM-Vt may be variable depending on the shooting mode. When gain switching is possible in a readout circuit and signal processing circuit (not shown) provided downstream of the CDS circuit 160, the bias point of the floating node FN where the high-luminance black sun phenomenon starts to occur may vary depending on the gain setting. When the noise output potential is read out, the high-intensity black sun phenomenon starts to occur when any one of the paths of the vertical signal line L1, readout circuit, signal processing circuit, etc. is saturated. Therefore, as the gain is set higher, the high-intensity black sun phenomenon starts to occur for smaller changes in the floating node FN.

  Therefore, in the shooting mode in which the gain is set high, the clip potential VM-Vt may be set higher. On the other hand, in the shooting mode in which the gain is set low, the clip potential VM-Vt may be set lower. In this case, since the clip potential VM-Vt is appropriately set for each photographing mode, it is possible to avoid saturation of the signal and suppress the high-intensity black sun phenomenon. As a result, deterioration in image quality can be suppressed.

  Next, an example of an imaging system to which the photoelectric conversion device of the present invention is applied is shown in FIG.

  As shown in FIG. 5, the imaging system 90 mainly includes an optical system, an imaging device 86, and a signal processing unit. The optical system mainly includes a shutter 91, a photographing lens 92, and a diaphragm 93. The imaging device 86 includes a photoelectric conversion device 100. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88.

  The shutter 91 is provided in front of the photographic lens 92 on the optical path and controls exposure.

  The photographic lens 92 refracts the incident light and forms an image of the subject on the photoelectric conversion device 100 of the imaging device 86.

  The diaphragm 93 is provided between the photographing lens 92 and the photoelectric conversion device 100 on the optical path, and adjusts the amount of light guided to the photoelectric conversion device 100 after passing through the photographing lens 92.

  The photoelectric conversion device 100 of the imaging device 86 converts the subject image formed on the photoelectric conversion device 100 into an image signal. The imaging device 86 reads the image signal from the photoelectric conversion device 100 and outputs it.

  The imaging signal processing circuit 95 is connected to the imaging device 86 and processes the image signal output from the imaging device 86.

  The A / D converter 96 is connected to the imaging signal processing circuit 95 and converts the processed image signal (analog signal) output from the imaging signal processing circuit 95 into a digital signal.

  The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like.

  The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97.

  The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

  The timing generation unit 98 is connected to the imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Thereby, a timing signal is supplied to the imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal.

  The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole.

  The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

  With the above configuration, if a good image signal is obtained in the photoelectric conversion device 100, a good image (image data) can be obtained.

  Next, a photoelectric conversion device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a configuration diagram of a photoelectric conversion apparatus according to the second embodiment. FIG. 7 is a waveform diagram showing the operation of the photoelectric conversion device of FIG.

  The basic structure of the photoelectric conversion device 200 is the same as that of the first embodiment. However, the photoelectric conversion device 200 includes a pixel cell 201 and the like instead of the pixel cell 101 and the like, and further includes a compensation pulse wiring L5. Different.

  The compensation pulse line L5 extends between the pixel cells 201 and the like in the row direction.

  The pixel cell 201 further includes a compensation capacitor (compensation unit) 209. The compensation capacitor 209 is provided between the compensation pulse line L5 and the floating node FN. As a result, the compensation capacitor 209 compensates for feedthrough of the floating node FN due to fluctuations in the gate potential (reset signal Res) of the reset transistor 105. The compensation capacitor 209 is designed to have a capacitance equivalent to the parasitic capacitance between the gate of the reset transistor 105 and the floating node FN, for example.

  As shown in FIG. 7, the compensation pulse supplied to one electrode of the compensation capacitor 209 via the compensation pulse wiring L5 logically outputs the reset signal Res supplied to the gate of the reset transistor 105 in the selected row. The signal is inverted. This compensation pulse is applied to the compensation pulse wiring L5 of the selected row. On the other hand, the compensation pulse line L5 in the unselected row is in an inactive state.

  In the first embodiment, the gate potential (the potential of the reset signal Res) of the reset transistor 105 is different between the noise readout period NP and the signal readout period SP. As a result, the influence of the feedthrough of the floating node FN is superimposed as an offset on the image signal obtained by calculating the difference between the noise output potential and the signal output potential by the CDS circuit 160. The linearity of the image signal with respect to the amount of incident light may decrease due to the offset of the image signal. Alternatively, when the offset amount of the screen signal is different for each pixel, shading may occur in an image obtained by photoelectric conversion.

  On the other hand, in the second embodiment, since the feedthrough of the floating node FN is compensated, the offset of the image signal can be compensated. Thereby, the fall of the linearity with respect to the incident light quantity of an image signal can be suppressed. Alternatively, since the variation in the offset amount of the screen signal for each pixel can be reduced, it is possible to suppress the occurrence of shading in an image obtained by photoelectric conversion.

  The amplitude of the compensation pulse is determined in consideration of the capacitance ratio between the compensation capacitor 209 and the feedthrough capacitance formed between the gate potential of the reset transistor 105 (the potential of the reset signal Res) and the floating node FN. It may be a value.

  The compensation capacitor 209 may be formed by a MOS transistor similar to the reset transistor 105.

  The compensation pulse may be a simplified binary simple pulse as shown in FIG. Even in this case, the compensation capacitor 209 compensates in the periods T3a to T4a in which the sample hold signal S / H (N) is activated and in the periods T8a to T9a in which the sample hold signal S / H (S) is activated. A pulse is input. Thereby, it is possible to compensate for the offset component of the image signal obtained by calculating the difference between the noise output potential and the signal output potential by the CDS circuit 160.

  The compensation pulse may be applied uniformly to the compensation pulse lines L5 of a plurality of rows without being applied independently to the compensation pulse lines L5 of the selected row. Even in this case, since the potential of the vertical signal line L1 is determined by the potential of the floating node FN in the selected row, the offset component of the image signal obtained by calculating the difference between the noise output potential and the signal output potential is compensated. Is possible. Further, since the compensation pulse is applied uniformly to all rows, the circuit for supplying the compensation pulse (vertical selection circuit not shown) can be simplified, and the chip size can be reduced.

The block diagram of the photoelectric conversion apparatus which concerns on 1st Embodiment of this invention. The block diagram of a pixel cell. The block diagram of a vertical scanning circuit. The wave form diagram which shows operation | movement of a photoelectric conversion apparatus. The block diagram of an imaging system. The block diagram of the photoelectric conversion apparatus which concerns on 2nd Embodiment of this invention. The wave form diagram which shows operation | movement of a photoelectric conversion apparatus. The wave form diagram which shows operation | movement of a photoelectric conversion apparatus.

Explanation of symbols

90 Imaging system.
100, 200 photoelectric conversion device.
102 photodiode 104 transfer transistor 105 reset transistor 106 amplification transistor 170 vertical scanning circuit 209 compensation capacitor FN floating node

Claims (6)

A photoelectric conversion unit that converts light into electric charge;
A charge converter for converting the charge into a potential;
A transfer unit that transfers the charge from the photoelectric conversion unit to the charge conversion unit;
An amplifier that reads a signal based on the electric potential of the charge converter;
A reset transistor for resetting a potential of the charge conversion unit;
A controller that applies at least three voltages to the gate of the reset transistor;
A difference circuit for subtracting a signal based on the reset potential of the charge converter and a signal based on the potential of the charge converter to which the charge has been transferred;
A photoelectric conversion device comprising: The photoelectric conversion device according to claim 1, wherein the reset unit clips a potential of the charge conversion unit. The charge is an electron;
3. The photoelectric conversion device according to claim 1, wherein the voltage applied to the gate of the reset transistor during the transfer of the charge is the lowest voltage. 4. The photoelectric conversion apparatus according to claim 1, further comprising a compensation unit that compensates for feedthrough to the charge conversion unit. Based on a photoelectric conversion unit that converts light into a charge, a charge conversion unit that converts the charge into a potential, a transfer unit that transfers the charge from the photoelectric conversion unit to the charge conversion unit, and a potential of the charge conversion unit A control method of a photoelectric conversion device including an amplification unit that reads a signal and a reset transistor that resets a potential of the charge conversion unit,
The charge is an electron;
Applying a first voltage to the gate of the reset transistor;
Applying a second voltage that is lower than the first voltage to the gate of the reset transistor;
Applying a third voltage that is lower than the second voltage to the gate of the reset transistor;
A control method for a photoelectric conversion device comprising: Optical system,
An imaging system comprising: the photoelectric conversion device according to claim 1.

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