JP2008060152A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device capable of reducing on-resistance while maintaining good avalanche resistance and a method of manufacturing the same are provided.
A first conductive type first semiconductor region, a second conductive type second semiconductor region formed on a surface of the first semiconductor region, and a second semiconductor region are formed. A third semiconductor region 14 of the first conductivity type, a fourth semiconductor region 12 of the second conductivity type formed inside the first semiconductor region 10 so as to be located below the second semiconductor region 11, and a second A fifth semiconductor region 13 of a second conductivity type formed on the surface of the first semiconductor region 10 adjacent to the fourth semiconductor region 12 so as to be located on the side of the semiconductor region 11, and the fourth semiconductor region Reference numeral 12 denotes the same potential as that of the fifth semiconductor region 13.
[Selection] Figure 2

Description

  The present invention relates to a vertical semiconductor device and a manufacturing method thereof, and more particularly to a transistor and a manufacturing method thereof.

  In recent years, efforts have been made to reduce on-resistance and improve avalanche resistance with respect to vertical semiconductor devices from the viewpoint of reducing power consumption of electronic devices and improving reliability. In addition, as one of techniques for realizing a reduction in on-resistance and an improvement in avalanche resistance, a technique for performing electric field relaxation is employed.

  FIG. 22 is a cross-sectional view showing the structure of a planar gate N-channel MOS transistor as a conventional vertical semiconductor device (see, for example, Patent Document 1).

This transistor includes an N ⁺ type semiconductor layer 2, an N ⁻ type drain layer 3, a P type body layer 4, a P ⁻ type field relaxation floating layer 5, and an N ⁺ type source layer 6 formed in a semiconductor substrate. . The drain layer 3 is formed on the semiconductor layer 2, and the body layer 4 and the electric field relaxation floating layer 5 are formed in the drain layer 3. The source layer 6 is formed in the body layer 4. Further, a gate electrode 8 is formed on the source layer 6, the body layer 4 and the electric field relaxation floating layer 5 via a gate oxide film 7, and a drain electrode 1 is formed on the back surface of the semiconductor substrate (semiconductor chip).

  In the conventional transistor having the above structure, the electric field strength between the body layer 4 and the drain layer 3 (PN junction) is relaxed by the action of the electric field relaxation floating layer 5. As a result, the breakdown voltage is improved and the avalanche resistance is increased. The principle is shown below.

  23 and 24 show how the depletion layer spreads and the electric field strength is maximum when a positive potential is applied to the drain electrode 1 and the gate electrode 8 and the source electrode 9 are set to 0 V in the conventional transistor having the above structure. It shows where to become.

  FIG. 23 shows that the depletion layer spreads from the body layer 4 and the drain layer 3 (PN junction) toward the drain layer 3. At this time, the place where the electric field strength becomes maximum is the PN junction corresponding to the portion of the shape where the curvature in the depletion layer is maximum, and becomes the corner portion near the bottom of the body layer 4 (A portion in FIG. 23). I understand.

  FIG. 23 shows that when the collector voltage is increased, the depletion layer spreading from between the body layer 4 and the drain layer 3 (PN junction) reaches the electric field relaxation floating layer 5. After the depletion layer reaches the electric field relaxation floating layer 5, the bottom thereof has a flat shape as shown in FIG. 24. Therefore, the electric field strength at the corner near the bottom of the body layer 4 (A portion in FIG. 23) is relaxed. Is done. At this time, the maximum portion of the electric field strength moves to the bottom surface portion (B portion in FIG. 24) of the body layer 4.

The electric field strength at the bottom surface of the body layer 4 is determined not by the curvature of the depletion layer shape but by the impurity concentration of the body layer 4 and the drain layer 3 because the shape of the bottom of the depletion layer is flat. In general, the breakdown voltage determined by the flat portion of the PN junction is larger than the breakdown voltage determined by the corner of the PN junction. Therefore, in the conventional transistor having the above structure, the floating layer 5 causes the maximum electric field strength between the body layer 4 and the drain layer 3 (PN junction) to be flat from the corner of the PN junction to the flat portion of the PN junction. To increase the breakdown voltage. Here, since the area where the breakdown current flows in the flat portion of the PN junction is larger than the area where the breakdown current flows in the corner portion of the PN junction, the avalanche resistance increases.
Japanese Patent Laid-Open No. 7-78978

  By the way, in the conventional transistor, the breakdown voltage is determined by the impurity concentration of the body layer and the drain layer. Therefore, when the on-resistance is reduced by lowering the impurity concentration of the body layer and the drain layer, the breakdown voltage is lowered. Therefore, the on-resistance cannot be reduced while maintaining a good avalanche resistance.

  Further, there is a need for an electric field relaxation structure that has a high effect of reducing on-resistance in a transistor and that can be easily manufactured.

  In view of the above problems, an object of the present invention is to provide a semiconductor device capable of reducing on-resistance while maintaining good avalanche resistance and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device of the present invention includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region formed on a surface of the first semiconductor region, and the first conductivity type. A third semiconductor region of the first conductivity type formed inside the two semiconductor regions, and a second conductivity type of the second semiconductor type formed inside the first semiconductor region so as to be positioned below the second semiconductor region. 4 semiconductor regions, and a second conductivity type fifth semiconductor region formed on the surface of the first semiconductor region adjacent to the fourth semiconductor region so as to be located laterally of the second semiconductor region. And the fourth semiconductor region has the same potential as the fifth semiconductor region. Here, the first semiconductor region is located in the fourth semiconductor region so as to penetrate the fourth semiconductor region toward the lower side of the second semiconductor region. One semiconductor region may be arranged in a stripe shape on the surface of the fourth semiconductor region. The semiconductor device may further include an eighth semiconductor region formed adjacent to the first semiconductor region and below the first semiconductor region.

  Thus, the control of the shape of the depletion layer in the lateral direction (direction parallel to the main surface of the semiconductor substrate) by the fifth semiconductor region (lateral electric field relaxation) is controlled by the fourth semiconductor region. As a result, the avalanche resistance can be improved. As a result, when designing with the same avalanche resistance as in the conventional transistor, the on-resistance can be reduced by making the impurity concentration of the first semiconductor region higher than the impurity concentration of the drain layer of the conventional transistor. That is, the on-resistance can be reduced while maintaining a good avalanche resistance.

  Here, the first semiconductor region may be located inside the fourth semiconductor region so as to penetrate the fourth semiconductor region toward the lower side of the second semiconductor region.

  As a result, the current from the second semiconductor region can flow toward the lower side of the fourth semiconductor region.

The fifth semiconductor region may be positioned so as to sandwich the second semiconductor region.
Thereby, the shape of the depletion layer in the lateral direction by the fifth semiconductor region can be controlled from both sides of the second semiconductor region, and the avalanche resistance can be further improved.

  The fifth semiconductor region includes a second conductivity type sixth semiconductor region formed on a surface of the first semiconductor region and a lower portion of the sixth semiconductor region so as to partially overlap the sixth semiconductor region. And a seventh semiconductor region formed on the substrate.

  Accordingly, when the fifth semiconductor region is formed by ion implantation, the diffusion lateral spread of the fifth semiconductor region due to the diffusion heat treatment can be reduced, and the area of the fifth semiconductor region can be reduced.

  The fourth semiconductor region may be formed after the fifth semiconductor region is formed.

  Accordingly, when the fifth semiconductor region is formed by ion implantation, the fourth semiconductor region is not affected by the diffusion heat treatment of the fifth semiconductor region. As a result, the degree of freedom in designing the concentration profile of the fifth semiconductor region increases, and device design according to the desired withstand voltage standard becomes possible.

  The semiconductor device is a trench gate type MOS transistor, the third semiconductor region is a source region, the second semiconductor region is a body region, and the first semiconductor region includes the body region. A trench gate penetrating through the gate may be formed.

  Thereby, it is possible to realize a trench gate type MOS transistor capable of reducing on-resistance while maintaining good avalanche resistance.

  The semiconductor device is a planar gate MOS transistor, the third semiconductor region is a source region, the second semiconductor region is a body region, and the semiconductor device further includes the source region and A planar gate formed on the body region may be provided.

  Thereby, it is possible to realize a planar gate type MOS transistor capable of reducing on-resistance while maintaining good avalanche resistance.

  The semiconductor device may be a bipolar transistor, the third semiconductor region may be an emitter region, and the second semiconductor region may be a base region.

  As a result, a bipolar transistor capable of reducing the on-resistance while maintaining a good avalanche resistance can be realized.

  The semiconductor device is a trench gate insulated gate bipolar transistor, the third semiconductor region is an emitter region, the second semiconductor region is a base region, and the first semiconductor region includes the A trench gate penetrating the base region may be formed.

  As a result, it is possible to realize a trench gate type insulated gate bipolar transistor capable of reducing on-resistance while maintaining good avalanche resistance.

  The semiconductor device is a planar gate insulated gate bipolar transistor, the third semiconductor region is an emitter region, the second semiconductor region is a base region, and the semiconductor device further includes the emitter. A planar gate formed on the region and the base region may be provided.

  As a result, it is possible to realize a planar gate insulated gate bipolar transistor capable of reducing the on-resistance while maintaining a good avalanche resistance.

  The semiconductor device may be a thyristor, the third semiconductor region may be an emitter region, and the second semiconductor region may be a base region.

  As a result, it is possible to realize a thyristor capable of reducing on-resistance while maintaining good avalanche resistance.

  The present invention also provides a fifth semiconductor region forming step of forming a second conductive type fifth semiconductor region on the surface of the first conductive type first semiconductor region, and the fifth semiconductor in the first semiconductor region. Forming a fourth semiconductor region of the second conductivity type at the same potential as the fifth semiconductor region so as to be adjacent to the region; and on the surface of the first semiconductor region above the fourth semiconductor region And a second semiconductor region forming step of forming a second semiconductor region of the second conductivity type so as to be positioned on the side of the fifth semiconductor region, and a first conductivity type inside the second semiconductor region It is also possible to provide a semiconductor device manufacturing method including a third semiconductor region forming step of forming a third semiconductor region. Here, the fourth semiconductor region and the fifth semiconductor region are formed by ion implantation and heat treatment performed on the first semiconductor region, and the fourth semiconductor region is used for forming the fifth semiconductor region. It may be formed after the heat treatment is performed.

  As a result, the fourth semiconductor region and the fifth semiconductor region are formed by ion implantation. Therefore, the first semiconductor region can be formed only from an inexpensive FZ method wafer without using an expensive epitaxial layer. As a result, an inexpensive semiconductor device can be manufactured, and a low-cost semiconductor device can be realized. Further, the fourth semiconductor region is not affected by the diffusion heat treatment of the fifth semiconductor region. As a result, the degree of freedom in designing the concentration profile of the fifth semiconductor region increases, and device design according to the desired withstand voltage standard becomes possible.

  The method for manufacturing a semiconductor device may further include stacking a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate to form the first semiconductor region including the semiconductor substrate and the epitaxial layer. Including a first semiconductor region forming step, wherein the fourth semiconductor region is formed by performing ion implantation and heat treatment on the semiconductor substrate before the epitaxial layer is formed, and the fifth semiconductor region is formed by the epitaxial region. The layer may be formed by ion implantation and heat treatment.

  Accordingly, the fourth semiconductor region can be formed deep in the first semiconductor region by increasing the thickness of the epitaxial layer.

  According to the semiconductor device of the present invention, electric field intensity relaxation is performed both in the horizontal direction (direction parallel to the main surface of the semiconductor substrate) and in the vertical direction (direction perpendicular to the main surface of the semiconductor substrate). Therefore, the electric field relaxation effect can be increased and the avalanche resistance can be improved. As a result, when designing with the same avalanche resistance as in the conventional transistor, the on-resistance can be reduced by making the impurity concentration of the first semiconductor region higher than the impurity concentration of the drain layer of the conventional transistor. That is, the on-resistance can be reduced while maintaining a good avalanche resistance. Further, in the semiconductor device according to the present invention, since the electric field strength is reduced near the main surface of the semiconductor layer, a low-cost semiconductor device can be realized.

  Hereinafter, semiconductor devices according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing a configuration of a vertical semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the vertical semiconductor device (cross-sectional view taken along line XX ′ in FIG. 1). ).

  The vertical semiconductor device includes a semiconductor substrate. In the semiconductor substrate, a first conductive type first semiconductor region 10 and a second conductive type second semiconductor formed on the surface of the first semiconductor region 10 are provided. The region 11, the first conductivity type third semiconductor region 14 and the second conductivity type tenth semiconductor region 17 formed in the second semiconductor region 11, and the second semiconductor region 11 are positioned below the region 11. The second conductive type fourth semiconductor region 12 formed inside the first semiconductor region 10 and the second conductive type second semiconductor region 12 formed inside the first semiconductor region 10 adjacent to the fourth semiconductor region 12. A fifth semiconductor region 13 and a second conductivity type ninth semiconductor region 15 formed inside the fifth semiconductor region 13 are formed.

  A first electrode 19 is formed on the back surface of the semiconductor substrate, that is, on the back surface of the first semiconductor region 10. A second electrode 18 is formed on the surface of the semiconductor substrate, that is, on the surface of the first semiconductor region 10 so as to be in contact with the third semiconductor region 14 and the ninth semiconductor region 15.

  The fifth semiconductor region 13 is formed on the surface of the first semiconductor region 10 between the second semiconductor region 11 and the chip end, and is located on the side of the second semiconductor region 11 so as to sandwich the second semiconductor region 11. . Further, as shown in FIG. 1, the fifth semiconductor region 13 is positioned so as to surround the fourth semiconductor region 12 in a plane parallel to the surface of the semiconductor substrate.

  The fourth semiconductor region 12 is electrically connected to the third semiconductor region 14 via at least one or more fifth semiconductor regions 13 and the second electrode 18, and the fourth semiconductor region 12 is the fifth semiconductor region. 13 and the third semiconductor region 14 are set to the same potential.

  Here, as shown in FIG. 2, the fourth semiconductor region 12 is spaced apart in a plane perpendicular to the surface of the semiconductor substrate, and the fourth semiconductor region 12 has the first semiconductor region 11 to the first semiconductor region 12. A plurality of first semiconductor regions 10 (C in FIG. 2) are positioned so as to penetrate the fourth semiconductor region 12 toward the electrode 19 (downward). As shown in FIG. 1, the first semiconductor region 10 inside the fourth semiconductor region 12 is arranged in a stripe shape (fence shape) on the surface of the fourth semiconductor region 12, that is, in a plane parallel to the surface of the semiconductor substrate. .

  In the vertical semiconductor device of the present embodiment, the fifth semiconductor region 13 is located so as to sandwich the second semiconductor region 11. However, two second semiconductor regions 11 may be provided, and the fifth semiconductor region 13 may be located between the two second semiconductor regions 11. In this case, the electric field relaxation effect is smaller than that of the vertical semiconductor device having the above structure.

  Further, the fifth semiconductor region 13 may be composed of two semiconductor regions. For example, the fifth semiconductor region 13 is formed below the sixth semiconductor region so that the sixth semiconductor region overlaps with the sixth semiconductor region of the second conductivity type formed on the surface of the first semiconductor region 10. And a seventh semiconductor region.

(Example 1)
Next, a specific example of the vertical semiconductor device of this embodiment will be described by way of example.

  Hereinafter, in order to make the description easy to understand, description will be made using a trench gate type N-channel MOS field effect transistor.

  FIG. 3 is a cross-sectional view (cross-sectional view taken along line X-X ′ in FIG. 1) illustrating the structure of the trench gate type N-channel MOS field effect transistor according to the first embodiment. The cross-sectional view of FIG. 3 shows a cross-sectional structure in the central portion of the semiconductor chip.

The transistor includes a semiconductor substrate. In the semiconductor substrate, an n-type drain layer 110, a p-type body layer 111 formed on the surface of the drain layer 110, and an n ⁺ type formed inside the body layer 111 are provided. Source layer 114 and p ⁺ -type contact layer 117, p ⁻ -type electric field relaxation layer 112 formed inside drain layer 110 so as to be positioned below body layer 111, and drain adjacent to electric field relaxation layer 112 A p ⁻ type connection layer 113 formed inside the layer 110 and a p ⁺ type contact layer 115 formed inside the connection layer 113 are formed. Note that the drain layer 110, the body layer 111, the source layer 114, the contact layer 117, the electric field relaxation layer 112, the connection layer 113, and the contact layer 115 are the first semiconductor region 10, the second semiconductor region 11, and the second semiconductor region 11, respectively. This is an example of the third semiconductor region 14, the tenth semiconductor region 17, the fourth semiconductor region 12, the fifth semiconductor region 13, and the ninth semiconductor region 15.

A drain electrode 119 is formed on the back surface of the semiconductor substrate, that is, on the back surface of the drain layer 110. Further, on the surface of the semiconductor substrate, that is, on the surface of the drain layer 110, a source / body / P ^- type connection layer electrode 118 is formed so as to be in contact with the contact layer 117, the source layer 114, and the contact layer 115.

  A trench that penetrates the body layer 111 is formed in the body layer 111, and a trench gate electrode 116 is formed in the trench.

The connection layer 113 is electrically connected to the source layer 114 by the source / body / P ⁻ -type connection layer electrode 118.

  Hereinafter, the action of the electric field relaxation effect of the transistor having the above structure will be described. 4, 5 and 6 are diagrams showing how the depletion layer spreads in the transistor.

From FIG. 4, when the source / body / P ^- type connection layer electrode 118, the body layer 111, the source layer 114, and the trench gate electrode 116 are set to 0 V and the voltage of the drain electrode 119 is increased, the drain layer 110 is reached. It can be seen that the depletion layer extends from the body layer 111, the connection layer 113, and the electric field relaxation layer 112. This is because the body layer 111, the connection layer 113, and the electric field relaxation layer 112 are all connected to a 0 V potential.

  At this time, as already described in the conventional transistor shown in FIG. 20, the maximum electric field strength in the absence of the electric field relaxation layer 112 is determined by the locality of the depletion layer, and the corner near the bottom of the body layer 111 (FIG. 4). Part A). However, in the transistor having the above structure, the shape of the depletion layer related to the corner near the bottom surface of the body layer 111 is such that the depletion layer in the lateral direction (X direction in FIG. 4) from the connection layer 113 and the electric field relaxation layer 112 Is controlled by a depletion layer in the vertical direction (Y direction in FIG. 4), and its curvature is relaxed. In addition, the depletion layer extending from the body layer 111 and the depletion layer extending from the connection layer 113 are connected, and the electric field at the corner near the bottom surface of the body layer 111 is relaxed. (B section 4).

  From FIG. 5, it can be seen that when the drain voltage is further increased, the depletion layer moves so that the depletion layer extending from the body layer 111 and the depletion layer extending from the electric field relaxation layer 112 are connected.

  For example, consider a case where the concentration distribution of the body layer 111 and the drain layer 110 of the transistor having the above structure is the same as that of the body layer and the drain layer of the conventional transistor shown in FIG. In this case, when the width d2 of the depletion layer extending from the body layer 111 is smaller than the width d1 of the depletion layer at the breakdown voltage in the conventional transistor, the depletion layer extends from the body layer 111 and the electric field relaxation layer 112. Ensure that the depletion layer is connected. By doing so, before the bottom surface of the body layer 111 reaches the electric field strength causing breakdown, the space between the body layer 111 and the electric field relaxation layer 112 is depleted, and the electric field at the bottom surface of the body layer 111 is relaxed. Is done. This is because the electric field relaxation layer 112 is set to a 0 V potential through the connection layer 113, so that the potential gradient between the body layer 111 and the electric field relaxation layer 112 becomes gentle.

  From FIG. 6, it can be seen that when the voltage of the drain electrode 119 is further increased, the space between the body layer 111 and the electric field relaxation layer 112 is depleted. At this time, the drain layer 110 surrounded by the body layer 111, the electric field relaxation layer 112, and the connection layer 113 is depleted, and the electric field strength at the PN junction of the body layer 111 and the drain layer 110 extends from the body layer 111. It does not depend on the shape (curvature) of the depletion layer. In addition, since the electric field relaxation layer 112 is set to 0 V potential through the connection layer 113, the potential gradient between the body layer 111 and the electric field relaxation layer 112 becomes gentle, and the body layer 111 and the drain layer 110 The electric field strength at the PN junction decreases. Therefore, for example, when the impurity concentration distribution of the body layer 111 and the drain layer 110 is the same as that of the conventional transistor, the breakdown voltage can be made higher than that of the conventional transistor. In the case where the transistor having the above structure is designed with the same breakdown voltage as that of the conventional transistor, the impurity concentration of the drain layer 110 can be made higher than the impurity concentration of the drain layer of the conventional transistor.

  At this time, by increasing the impurity concentration of the drain layer 110, the electric field strength of the bottom surface portion of the body layer 111 is increased. Therefore, before the bottom surface portion of the body layer 111 reaches the breakdown voltage, the electric field relaxation layer 112 and the body The drain layer 110 between the layer 111 needs to be depleted. That is, the value of E1 (the width of the drain layer 110 between the body layer 111 and the electric field relaxation layer 112) in FIG. 5 is reduced and surrounded by the body layer 111, the electric field relaxation layer 112, and the connection layer 113 with a lower voltage. It is important to deplete the drain layer 110 formed.

  FIG. 7 is a diagram showing a current flow during transistor operation in the transistor having the above structure.

  As can be seen from FIG. 7, the drain current sequentially flows along the path of the drain layer 110, the drain layer 110 inside the electric field relaxation layer 112, the channel portion immediately below the trench gate electrode 116, and the source layer 114. At this time, in the lower portion of the drain layer 110, the electric field relaxation layer 112 reduces the current flowing area, but the on-resistance can be lowered because the impurity concentration of the drain layer 110 is increased.

  In the transistor having the above structure, the electric field relaxation layer 112 is arranged in a stripe shape in a plane parallel to the surface of the semiconductor substrate, and all the ends in the longitudinal direction are connected to the source layer 114 by the electric field relaxation layer 112 or the connection layer 113. Is done. With such a pattern, the curvature on the planar pattern of the depletion layer extending from the PN junctions of the electric field relaxation layer 112, the connection layer 113, and the drain layer 110 is increased, and the electric field strength is reduced as compared with the conventional transistor. Can be improved. As a result, the avalanche resistance can be improved as compared with the conventional transistor.

  In the transistor having the above structure, the connection layer 113 is disposed so as to sandwich the body layer 111. Therefore, in addition to the relaxation effect of the electric field strength by the depletion layer extending from the electric field relaxation layer 112, the relaxation effect of the electric field strength by the depletion layer extending from the connection layer 113 is added, and both from the direction perpendicular to and parallel to the surface of the semiconductor substrate. Electric field relaxation can be performed. As a result, the impurity concentration in the drain region and the like can be increased, and the on-resistance can be reduced.

(Example 2)
FIG. 8 is a sectional view showing the structure of the trench gate type N-channel MOS field effect transistor according to the second embodiment. The cross-sectional view of FIG. 8 shows a cross-sectional structure in the central portion of the semiconductor chip.

  This transistor differs from the transistor of Embodiment 1 in that two body layers are provided and a connection layer is formed between the two body layers. The transistor includes a semiconductor substrate. In the semiconductor substrate, a drain layer 110, a p-type body layer 211 formed on the surface of the drain layer 110, a source layer 114 and a contact layer 117, and an electric field relaxation layer 112 are provided. A connection layer 213 formed inside the drain layer 110 adjacent to the electric field relaxation layer 112 and a contact layer 115 are formed. The body layer 211 and the connection layer 213 are examples of the second semiconductor region 11 and the fifth semiconductor region 13 of this embodiment, respectively.

A drain electrode 119 is formed on the back surface of the drain layer 110, and a source / body / P ⁻ -type connection layer electrode 118 is formed on the drain layer 110 surface. A trench that penetrates the body layer 211 is formed in the body layer 211, and a trench gate electrode 116 is formed in the trench.

Two body layers 211 are provided, and the connection layer 213 is located between the two body layers 211. The connection layer 213 is electrically connected to the source layer 114 by the source / body / P ⁻ -type connection layer electrode 118.

  Hereinafter, the action of the electric field relaxation effect of the transistor having the above structure will be described. 9 and 10 are diagrams showing how the depletion layer spreads in the transistor.

  As is clear from comparison between FIG. 4 and FIG. 9, in the transistor having the above structure, the electric field relaxation at the corner near the bottom of the body layer 211 (A portion in FIG. 9) It is only due to elongation. On the other hand, in the transistor of Example 1, the electric field relaxation at the corner near the bottom of the body layer 111 (A portion in FIG. 4) is caused by the extension of the depletion layer from the electric field relaxation layer 112 and the depletion layer from the connection layer 213. This is due to both elongation. Therefore, the maximum electric field strength portion of the body layer 211 in the transistor having the above structure is such that the depletion layer from the electric field relaxation layer 112 is connected to the depletion layer from the body layer 211 as shown in FIG. It does not move from the corner near the bottom (A portion in FIG. 9).

  As described above, according to the trench gate type N-channel MOS field effect transistor of the present embodiment, the avalanche resistance can be improved as in the transistor of the first embodiment.

(Example 3)
FIG. 11 is a cross-sectional view (cross-sectional view taken along the line XX ′ of FIG. 1) showing the structure of the trench gate type N-channel MOS field effect transistor according to the third embodiment. The cross-sectional view of FIG. 11 shows a cross-sectional structure in the central portion of the semiconductor chip.

This transistor differs from the transistor of Example 1 in that the connection layer is composed of two connection layers. The transistor includes a semiconductor substrate, and in the semiconductor substrate, a drain layer 110, a body layer 111, a source layer 114 and a contact layer 117, an electric field relaxation layer 112, and a drain layer adjacent to the electric field relaxation layer 112. A p ⁻ type connection layer 320 formed inside 110, a p type connection layer 336 formed on the surface of the drain layer 110, and a contact layer 115 are formed. Note that the connection layer 320 and the connection layer 336 are examples of the seventh semiconductor region and the sixth semiconductor region in this embodiment, respectively.

A drain electrode 119 is formed on the back surface of the drain layer 110, and a source / body / P ⁻ -type connection layer electrode 118 is formed on the drain layer 110 surface. A trench that penetrates the body layer 111 is formed in the body layer 111, and a trench gate electrode 116 is formed in the trench.

The connection layer 336 and the connection layer 320 are electrically connected to the source layer 114 and the source / body / P ⁻ -type connection layer electrode 118. The connection layer 320 is formed below the connection layer 336 so as to partially overlap the connection layer 336.

  At this time, the diffusion spread in the vertical direction of the electric field relaxation layer 112 needs to be smaller than the spread in the vertical direction of the connection layer 320. This is because the width of the drain layer 110 between the body layer 111 and the electric field relaxation layer 112 needs to be maintained at a desired value according to the breakdown voltage standard of the transistor. Therefore, as a manufacturing method, it is effective to perform the impurity implantation and diffusion heat treatment for forming the connection layer 320 before the impurity implantation and diffusion heat treatment for forming the electric field relaxation layer 112. By doing so, the electric field relaxation layer 112 is not affected by the diffusion heat treatment of the connection layer 320. Hereinafter, a method for manufacturing a transistor having the above structure will be described with reference to cross-sectional views shown in FIGS.

  First, as shown in FIG. 12A, after a pattern for forming the connection layer 320 is formed by a photoresist, p-type impurities are implanted with high energy by ion implantation, and heat treatment is performed at a high temperature. A connection layer 320 is formed in the layer 110. The ion implantation is performed, for example, by implanting boron with an implantation energy of 120 keV or higher.

  Next, as shown in FIG. 12B, after forming a pattern for forming the electric field relaxation layer 112 with a photoresist, p-type impurities are implanted with high energy by ion implantation, and heat treatment is performed to form a drain layer. An electric field relaxation layer 112 is formed in 110. The ion implantation is performed, for example, by implanting boron with an implantation energy of 120 keV or higher.

  Next, as shown in FIG. 12C, after forming a pattern for forming the connection layer 336 and the body layer 111 with a photoresist, p-type impurities are implanted by an ion implantation method, heat treatment is performed, and a drain is formed. A connection layer 336 and a body layer 111 are simultaneously formed on the surface of the layer 110. Thereafter, the source layer 114 and the contact layer 117 are formed in the body layer 111 by ion implantation, and the contact layer 115 is formed in the connection layer 336 by ion implantation.

Finally, the drain electrode 119, the trench gate electrode 116, and the source / body / P ⁻ -type connection layer electrode 118 are formed.

As described above, according to the trench gate type N-channel MOS field effect transistor of the present embodiment, the connection layer connecting the field relaxation layer 112 and the source / body / P ⁻ type connection layer electrode 118 is connected. A layer 320 and a connection layer 336 are included. With such a configuration, the diffusion lateral spread of the connection layer can be reduced, and the area of the connection layer can be reduced.

  Further, according to the trench gate type N channel MOS field effect transistor of the present embodiment, the electric field relaxation layer 112 is formed after the connection layer 320 is formed. Therefore, the amount of heat received by the electric field relaxation layer 112 is not affected by the diffusion heat treatment of the connection layer 320. As a result, the degree of freedom in designing the concentration profile of the electric field relaxation layer 112 increases, and device design according to the desired withstand voltage standard becomes possible.

  In addition, according to the trench gate type N channel MOS field effect transistor of this embodiment, the electric field relaxation layer 112 and the connection layer 320 are formed by high energy ion implantation. Therefore, the drain layer 110 can be manufactured using only an inexpensive FZ method wafer without using an expensive epitaxial layer. As a result, a transistor can be manufactured at a low manufacturing cost, and a low-cost transistor can be realized.

  Note that the trench gate type N-channel MOS field effect transistor of this embodiment is formed by using an epitaxial layer and may have a structure as shown in FIG. The formation method of such a structure is effective when applied to a high breakdown voltage device in which the electric field relaxation layer 112 is formed deep in the drain layer 110. In this forming method, first, as shown in FIG. 14A, the electric field relaxation layer 112 is formed on the main surface of the N-type wafer to be the drain layer 110 by ion implantation of p-type impurities. Next, as shown in FIG. 14B, after an epitaxial layer is formed on the main surface of the N-type wafer, a connection layer 320 is formed on the surface of the epitaxial layer by ion implantation of p-type impurities. Finally, as shown in FIG. 14C, after an epitaxial layer is formed on the epitaxial layer on which the connection layer 320 is formed, ions of p-type impurities are formed at positions overlapping the connection layer 320 on the surface of the epitaxial layer. The connection layer 336 is formed by implantation, and the body layer 111 is formed simultaneously with the formation of the connection layer 336. In this transistor, the width of the drain layer 110 between the electric field relaxation layer 112 and the body layer 111 is determined by the difference between the thickness of the epitaxial layer and the diffusion depth of the electric field relaxation layer 112 and the connection layer 320. The difference in diffusion depth between the electric field relaxation layer 112 and the connection layer 320 is determined by the difference in impurity concentration between the respective diffusion layers. The higher the impurity concentration, the larger the diffusion depth. Therefore, in this transistor, it is essential that the impurity concentration of the connection layer 320 is higher than the impurity concentration of the electric field relaxation layer 112.

  Further, the trench gate type N-channel MOS field effect transistor of this embodiment may have a structure as shown in FIG. In this transistor, two body layers 211 are provided, and a connection layer 320 and a connection layer 336 are located between the two body layers 211.

(Second Embodiment)
FIG. 16 is a cross-sectional view (cross-sectional view taken along the line XX ′ in FIG. 1) showing the structure of the vertical semiconductor device according to the second embodiment of the present invention.

  This vertical semiconductor device is different from the vertical semiconductor device of the first embodiment in that it includes an eighth semiconductor region 20. The vertical semiconductor device includes a semiconductor substrate, and a first semiconductor region 10, a second semiconductor region 11, a third semiconductor region 14, a tenth semiconductor region 17, and a fourth semiconductor region are included in the semiconductor substrate. 12, a fifth semiconductor region 13, a ninth semiconductor region 15, and an eighth semiconductor region 20 formed below the first semiconductor region 10 are formed. A first electrode 19 is formed on the back surface of the eighth semiconductor region 20, and a second electrode 18 is formed on the surface of the first semiconductor region 10.

Example 4
Next, a specific example of the vertical semiconductor device of this embodiment will be described by way of example.

  FIG. 17 is a cross-sectional view (cross-sectional view taken along line X-X ′ in FIG. 1) showing the structure of a trench gate type insulated gate bipolar transistor (IGBT) according to the fourth embodiment. The cross-sectional view of FIG. 17 shows a cross-sectional structure in the central portion of the semiconductor chip.

This transistor includes a semiconductor substrate, and in the semiconductor substrate, an n-type semiconductor layer 531, a p-type base layer 532 formed on the surface of the semiconductor layer 531, and an n ⁺ -type formed inside the base layer 532. Emitter layer 533 and p ⁺ -type base contact layer 534, p ⁻ -type field relaxation layer 112 formed inside semiconductor layer 531 so as to be positioned below base layer 532, and adjacent to field relaxation layer 112 A p ⁻ -type connection layer 113 formed inside the semiconductor layer 531, a contact layer 115, and a p-type collector layer 530 formed below the semiconductor layer 531 are formed. A collector electrode 529 is formed on the back surface of the collector layer 530, and an emitter / base / P ⁻ type connection layer electrode is formed on the surface of the semiconductor layer 531 so as to be in contact with the emitter layer 533, the base contact layer 534, and the contact layer 115. 535 is formed. A trench that penetrates the base layer 532 is formed in the base layer 532, and a trench gate electrode 116 is formed in the trench. Note that the semiconductor layer 531, the base layer 532, the emitter layer 533, the base contact layer 534, and the collector layer 530 are the first semiconductor region 10, the second semiconductor region 11, the third semiconductor region 14, and the tenth layer of the present embodiment, respectively. 2 is an example of a semiconductor region 17 and an eighth semiconductor region 20.

  The field relaxation structure, operation, and effect of the IGBT having the above structure are the same as those of the trench gate type MOS transistor already described. That is, the avalanche resistance can be improved as compared with the conventional transistor. In addition, since the impurity concentration of the collector layer 530 can be increased, the on-resistance can be reduced.

  In the case of an IGBT, holes remaining in the semiconductor layer 531 when the transistor is off are extracted from the electric field relaxation layer 112 and the connection layer 113, and there is an advantage that a response at the time of off can be accelerated.

(Example 5)
FIG. 18 is a cross-sectional view (cross-sectional view taken along the line XX ′ in FIG. 1) illustrating the structure of the planar gate type IGBT according to the fifth embodiment. The cross-sectional view of FIG. 18 shows a cross-sectional structure in the central portion of the semiconductor chip.

This transistor includes a semiconductor substrate, and in the semiconductor substrate, a semiconductor layer 531, a base layer 532 formed on the surface of the semiconductor layer 531, an emitter layer 533 and a base contact layer 534, an electric field relaxation layer 112, A connection layer 113 and a collector layer 530 are formed. A collector electrode 529 is formed on the back surface of the collector layer 530, and a planar gate electrode 622 and an emitter / base / P ⁻ -type connection layer electrode 535 are formed on the surface of the semiconductor layer 531.

  The electric field relaxation structure, operation, and effect of the transistor having the above structure are the same as those of the IGBT already described in the fourth embodiment.

(Example 6)
FIG. 19 is a cross-sectional view (cross-sectional view taken along the line XX ′ in FIG. 1) illustrating the structure of the thyristor according to the sixth embodiment. The cross-sectional view of FIG. 19 shows a cross-sectional structure in the central portion of the semiconductor chip.

The thyristor includes a semiconductor substrate, and a semiconductor layer 531, a base layer 532, an emitter layer 533 and a base contact layer 534, an electric field relaxation layer 112, a connection layer 113, and a semiconductor layer 531 are included in the semiconductor substrate. The p-type anode layer 630 is formed. An anode electrode 623 is formed on the back surface of the anode layer 630, and an emitter / P ⁻ -type connection layer electrode 935 is formed on the surface of the semiconductor layer 531 so as to be in contact with the emitter layer 533 and the contact layer 115. The contact layer 115 is connected to the cathode electrode wiring.

  The electric field relaxation structure, operation, and effect of the transistor having the above structure are the same as those of the IGBT already described in the fourth embodiment.

  Although the vertical semiconductor device of the present invention has been described based on the embodiment, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.

  For example, the vertical semiconductor device may be an NPN bipolar transistor, a PNP bipolar transistor, a planar gate type P channel MOS transistor, a planar gate type N channel MOS transistor, a trench gate type P channel MOS transistor, or the like.

  That is, the vertical semiconductor device may be a planar gate N-channel MOS transistor as shown in FIG. In this transistor, a planar gate electrode 700 is formed on the source layer 114 and the body layer 111. Since the field relaxation structure, operation, and effect of this transistor are the same as those of the trench gate type N-channel MOS field effect transistor already described, description thereof is omitted.

Further, the vertical semiconductor device may be an NPN bipolar transistor as shown in FIG. In this transistor, an n-type collector layer 824, a p-type base layer 825 formed on the surface of the collector layer 824, an n ⁺ -type emitter layer 826 and a p ⁺ -type base contact layer formed inside the base layer 825. 827, the electric field relaxation layer 112, the connection layer 113, and the contact layer 115 are formed in the semiconductor substrate. A collector electrode 823 is formed on the back surface of the collector layer 824, and an emitter / p ^- type connection layer electrode 928 is formed on the surface of the collector layer 824 so as to be in contact with the emitter layer 826 and the contact layer 115. . The contact layer 115 is connected to the emitter electrode wiring. The collector layer 824, the base layer 825, the emitter layer 826, and the base contact layer 827 are the same as the first semiconductor region 10, the second semiconductor region 11, the third semiconductor region 14, and the tenth semiconductor region 17 of this embodiment, respectively. It is an example. Since the field relaxation structure, operation, and effect of this transistor are the same as those of the trench gate type N-channel MOS transistor already described, description thereof is omitted.

  The present invention can be used for a vertical semiconductor device, and can be used particularly for a transistor or the like.

1 is a plan view showing a configuration of a vertical semiconductor device according to a first embodiment of the present invention. FIG. 2 is a structural diagram (cross-sectional view taken along line X-X ′ in FIG. 1) of the vertical semiconductor device. FIG. 3 is a cross-sectional view (cross-sectional view taken along line X-X ′ in FIG. 1) illustrating the structure of the trench gate type N-channel MOS field effect transistor according to the first embodiment. It is a figure for demonstrating the electric field relaxation effect of the transistor. It is a figure for demonstrating the electric field relaxation effect of the transistor. It is a figure for demonstrating the electric field relaxation effect of the transistor. It is a figure for demonstrating the flow of the electric current of the transistor. 6 is a cross-sectional view showing the structure of a trench gate type N-channel MOS field effect transistor according to Example 2. FIG. It is a figure for demonstrating the electric field relaxation effect of the transistor. It is a figure for demonstrating the electric field relaxation effect of the transistor. FIG. 6 is a cross-sectional view (cross-sectional view taken along line X-X ′ in FIG. 1) showing a structure of a trench gate type N-channel MOS field effect transistor according to Example 3; 12 is a cross-sectional view for illustrating the method for manufacturing the transistor. FIG. It is sectional drawing (sectional drawing in X-X 'of FIG. 1) which shows the structure of the modification of the transistor. It is sectional drawing for demonstrating the manufacturing method of the modification of the transistor. It is sectional drawing which shows the structure of the modification of the transistor. FIG. 6 is a cross-sectional view (a cross-sectional view taken along line X-X ′ in FIG. 1) showing a structure of a vertical semiconductor device according to a second embodiment of the present invention. FIG. 7 is a cross-sectional view (cross-sectional view taken along line X-X ′ in FIG. 1) illustrating the structure of a trench gate type IGBT according to Example 4; FIG. 10 is a cross-sectional view (a cross-sectional view taken along line X-X ′ in FIG. 1) illustrating a structure of a planar gate type IGBT according to Example 5; FIG. 6 is a cross-sectional view (cross-sectional view taken along line X-X ′ in FIG. 1) illustrating a structure of a thyristor according to Example 6. FIG. 2 is a cross-sectional view (cross-sectional view taken along line X-X ′ in FIG. 1) showing a structure of a planar gate type N-channel MOS transistor as a vertical semiconductor device according to the present invention. FIG. 2 is a cross-sectional view (cross-sectional view taken along line X-X ′ in FIG. 1) showing the structure of an NPN bipolar transistor as a vertical semiconductor device according to the present invention. It is sectional drawing which shows the structure of the planar gate type N channel MOS transistor as the conventional vertical semiconductor device. It is a figure for demonstrating the expansion method of the depletion layer in the transistor, and the place where electric field strength becomes the maximum. It is a figure for demonstrating the expansion method of the depletion layer in the transistor, and the place where electric field strength becomes the maximum.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,119 Drain electrode 2,531 Semiconductor layer 3,110 Drain layer 4,111,211 Body layer 5 Electric field relaxation floating layer 6,114 Source layer 7 Gate oxide film 8 Gate electrode 9 Source electrode 10 1st semiconductor region 11 2nd Semiconductor region 12 4th semiconductor region 13 5th semiconductor region 14 3rd semiconductor region 15 9th semiconductor region 17 10th semiconductor region 18 2nd electrode 19 1st electrode 20 8th semiconductor region 112 Electric field relaxation layer 113, 213, 320, 336 Connection layer 115, 117 Contact layer 116 Trench gate electrode 118 Source / body / P ^- type connection layer electrode 529, 823 Collector electrode 530, 824 Collector layer 532, 825 Base layer 533, 826 Emitter layer 534, 827 Base contact layer 535 Emitter base P ^- type connection layer electrode 622, 700 Planar type gate electrode 623 Anode electrode 630 Anode layer 928, 935 Emitter P ^- type connection layer electrode

Claims (16)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type formed on the surface of the first semiconductor region;
A third semiconductor region of a first conductivity type formed inside the second semiconductor region;
A fourth semiconductor region of a second conductivity type formed inside the first semiconductor region so as to be located below the second semiconductor region;
A second conductive type fifth semiconductor region formed on a surface of the first semiconductor region adjacent to the fourth semiconductor region so as to be located laterally of the second semiconductor region;
The semiconductor device, wherein the fourth semiconductor region has the same potential as the fifth semiconductor region. 2. The semiconductor according to claim 1, wherein the first semiconductor region is located inside the fourth semiconductor region so as to penetrate the fourth semiconductor region toward the lower side of the second semiconductor region. apparatus. The first semiconductor region is located inside the fourth semiconductor region so as to penetrate the fourth semiconductor region toward the lower side of the second semiconductor region,
The semiconductor device according to claim 1, wherein the first semiconductor region inside the fourth semiconductor region is arranged in a stripe shape on a surface of the fourth semiconductor region. The semiconductor device according to claim 1, wherein the fifth semiconductor region is positioned so as to sandwich the second semiconductor region. The fifth semiconductor region is formed below the sixth semiconductor region so as to partially overlap the sixth semiconductor region of the second conductivity type formed on the surface of the first semiconductor region. The semiconductor device according to claim 1, further comprising: a seventh semiconductor region. The semiconductor device according to claim 4, wherein the fourth semiconductor region is formed after the fifth semiconductor region is formed. The semiconductor device is a trench gate type MOS transistor,
The third semiconductor region is a source region;
The second semiconductor region is a body region;
The semiconductor device according to claim 1, wherein a trench gate penetrating the body region is formed in the first semiconductor region. The semiconductor device is a planar gate type MOS transistor,
The third semiconductor region is a source region;
The second semiconductor region is a body region;
The semiconductor device according to any one of claims 1 to 6, further comprising a planar gate formed on the source region and the body region. The semiconductor device is a bipolar transistor,
The third semiconductor region is an emitter region;
The semiconductor device according to claim 1, wherein the second semiconductor region is a base region. The semiconductor device according to claim 1, further comprising an eighth semiconductor region formed adjacent to the first semiconductor region and below the first semiconductor region. The semiconductor device is a trench gate type insulated gate bipolar transistor,
The third semiconductor region is an emitter region;
The second semiconductor region is a base region;
The semiconductor device according to claim 10, wherein a trench gate penetrating the base region is formed in the first semiconductor region. The semiconductor device is a planar gate type insulated gate bipolar transistor,
The third semiconductor region is an emitter region;
The second semiconductor region is a base region;
The semiconductor device according to claim 10, further comprising a planar gate formed on the emitter region and the base region. The semiconductor device is a thyristor,
The third semiconductor region is an emitter region;
The semiconductor device according to claim 10, wherein the second semiconductor region is a base region. A fifth semiconductor region forming step of forming a second conductive type fifth semiconductor region on the surface of the first conductive type first semiconductor region;
Forming a fourth semiconductor region of the second conductivity type at the same potential as the fifth semiconductor region so as to be adjacent to the fifth semiconductor region inside the first semiconductor region;
A second semiconductor region forming step of forming a second semiconductor region of a second conductivity type on the surface of the first semiconductor region so as to be positioned above the fourth semiconductor region and beside the fifth semiconductor region; ,
And a third semiconductor region forming step of forming a first semiconductor region of the first conductivity type inside the second semiconductor region. The fourth semiconductor region and the fifth semiconductor region are formed by ion implantation and heat treatment performed on the first semiconductor region,
The method of manufacturing a semiconductor device according to claim 14, wherein the fourth semiconductor region is formed after the heat treatment for forming the fifth semiconductor region is performed. The method for manufacturing a semiconductor device further includes: stacking a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate; and forming the first semiconductor region including the semiconductor substrate and the epitaxial layer. Including a semiconductor region forming step,
The fourth semiconductor region is formed by performing ion implantation and heat treatment on the semiconductor substrate before the epitaxial layer is formed,
The method of manufacturing a semiconductor device according to claim 14, wherein the fifth semiconductor region is formed by performing ion implantation and heat treatment on the epitaxial layer.

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