JP2008065978A - Programming method in multi-level non-volatile memory device - Google Patents

Abstract

A programming method in a multi-level non-volatile memory device is provided.
A programming method in a multi-level non-volatile memory including at least one flag cell and a plurality of multi-bit storage cells includes a storage cell having a reference voltage of VR1 <VR2 <VR3. When storing the first value, it has a threshold voltage lower than VR1, and when storing the second value in the storage cell, it has a threshold voltage higher than VR1 and lower than VR2, and the storage cell has a third value. If storing, has threshold voltage higher than VR2 and lower than VR3, and storing the fourth value in the storage cell, program the least significant bit first in the storage cell to have a threshold voltage higher than VR3 After that, the flag cell is programmed to have a threshold voltage higher than VR3 to indicate that the most significant bit is programmed and that the most significant bit is programmed. Including the steps of: lamb, a.
[Selection] Figure 8

Description

  The present invention relates to a nonvolatile memory device, and more particularly to a programming method in a multi-level nonvolatile memory device.

Flash memory is a form of computer memory that maintains data without power consumption and is characterized as non-volatile memory. The flash memory is programmed and erased in units of blocks.
Flash memory stores data in an array of floating gate transistors called cells. A single level flash memory stores one bit of data in each cell. On the other hand, the multi-level flash memory stores one bit or more of data in each cell by diversifying the amount of charge stored in the floating gate of the cell.

  FIG. 1 is a diagram showing a single cell 10 of a flash memory. The flash memory includes a p-type semiconductor substrate 11 doped with boron ions or the like. The n-type source region 12 and the n-type drain region 13 are formed by doping the semiconductor substrate 11 with phosphorus, arsenic or antimony. The floating gate 14 is formed on the substrate 11 and insulated from the substrate. The control gate 15 is formed on the floating gate 14 and is insulated from the floating gate 14. Since the floating gate 14 is completely insulated, charges stored in the floating gate are trapped and data can be maintained in the floating gate without power consumption.

  The flash memory can be a NOR memory or a NAND memory. Each form of flash memory has its own characteristics. For example, NOR flash uses a hot electron injection scheme to trap charge on the floating gate and requires a quantum tunneling phenomenon to discharge the floating gate. NAND flash utilizes quantum tunneling for both charge trapping and discharge.

  The NAND flash memory device is composed of strings. FIG. 2 is a diagram illustrating an example of a string of the NAND flash memory. The string is actually formed as 200A, and if it is electrically shown, it is expressed as 200B. Each string is a group of cells connected in series. Each string comprises 16 or 32 cells. Each string includes a bit line connected to the bit line contact 210. Each string includes at least one gate for removing the string. For example, each string includes a selection gate 220 and a control gate 230. The string includes a floating gate 240 and a cell source line 250.

  Multiple strings are concatenated in page form. A word line connects cells of each string on the page. Multiple pages are combined in blocks. FIG. 3 is a diagram illustrating an example of a flash memory block. The flash memory 100 includes an X decoder 130 that controls the voltages of the word line WL, the string selection line SSL, and the ground selection line GSL. The flash memory 100 also includes a page buffer circuit 150 in order to control the voltage of the bit line BL. The flash memory 100 includes a block 110 composed of strings. FIG. 3 shows only the strings 110_1, 110_2, and 110_M, but another string is further provided between the strings 110_2 and 110_M. The string 110_1 includes a bit line BLe, and the string 110_2 includes a bit line BLo. The flash memory 100 is also composed of pages. An example of one page is shown at 110p.

  Each string is connected to a string selection line SSL, a ground selection line GSL, a word line WL numbered by WL <N-1> to WL <0>, and a common source line CSL. Each string includes a string selection transistor SST, a ground selection transistor GST, and memory cell transistors MCT numbered by MCT <N−1> to MCT <0>.

  In flash memory devices, the presence and amount of charge on the floating gate affects the threshold voltage of the cell. The cell threshold voltage refers to the minimum voltage that must be applied to the control gate in order for current to flow between the source and drain. Therefore, the cell is read based on whether a predetermined voltage is applied to the control gate and a current flows between the source and the drain. In practice, the sense amplifier is used to sense and amplify the current flow.

  In multi-level flash, charge is stored in the cell's floating gate in various levels of quantities. For example, in a 2-bit multi-level flash, there can be four distinct charge quantities stored in the cell's floating gate. In this case, the cell can exist at one of four different threshold voltages depending on the level of charge trapped in the floating gate. The amount of charge stored in the cell (stored data value) is determined by applying a test voltage to the control gate and checking the current flow through the cell. In 2-bit multilevel flash, it is necessary to test whether current flows for at least three or more distinct read voltages in order to determine the state of the cell.

Multi-level flash can store 2 bits or more in one memory cell (2-bit flash memory). For example, multi-level flash can store 3 bits or more in one memory cell (n-bit flash memory, n is a natural number of 3 or more). A 3-bit flash memory has 8 (2 ³ ) states for each cell, and a 4-bit flash has 16 (2 ⁴ ) states. Similarly, a 5-bit flash memory has 32 (2 ⁵ ) states for each cell. Each of the operation threshold voltages of such multi-level flash must be set to exceed a specific range, and there must be a voltage difference greater than a margin between adjacent threshold voltages. Therefore, in the multi-level flash, as the number of bits stored in one cell increases, the amount of charge stored in the floating gate according to the data value must be set to a narrower range and have a narrower margin. Don't be. In order to implement such a narrow range and margin, the cell must be accurately charged. Supplying a charge to a cell is called “programming”. Therefore, programming with multilevel flash memory requires a high degree of accuracy.

  An object of the present invention is to provide a programming method in a multi-level non-volatile memory device that can be programmed with high accuracy.

  In order to solve the above-mentioned problem, at least one flag cell and a plurality of multi-bit storage cells are provided, and each multi-bit storage cell has a different amount of charge used for data to be expressed. The data includes a least significant bit (LSB) and a most significant bit (MSB), and the programming method in the multi-level non-volatile memory according to an embodiment of the present invention may include a reference voltage. When the first value is stored in the storage cell when the magnitudes of VR1, VR2, and VR3 are VR1 <VR2 <VR3, the storage cell has a threshold voltage lower than the voltage VR1, and the storage cell has a second value. When the threshold voltage is higher than the voltage VR1 and lower than the voltage VR2. And having a threshold voltage higher than the voltage VR2 and lower than the voltage VR3 and trying to store a fourth value in the storage cell, Programming the MSB after first programming the LSB to the storage cell to have a threshold voltage higher than the voltage VR3, and the flag cell to indicate that the MSB is programmed, Programming to have a threshold voltage higher than voltage VR3.

  In order to solve the above problems, the multi-bit storage cell includes at least one flag cell and a plurality of multi-bit storage cells, and each multi-bit storage cell stores different amounts of charge used for data to be represented. The controller may control the memory by a programming method in a multi-level non-volatile memory including LSB and MSB. The controller according to the embodiment of the present invention may use the programming method to increase the reference voltages VR1, VR2, and VR3. When VR1 <VR2 <VR3, when the first value is stored in the storage cell, the threshold voltage is lower than the voltage VR1 and the second value is stored in the storage cell. When the threshold voltage is higher than the voltage VR1 and lower than the voltage VR2, and the third value is stored in the storage cell, the voltage VR2 If the threshold voltage is higher than the voltage VR3 and the fourth value is stored in the storage cell, the storage cell is first provided with the LSB so as to have a threshold voltage higher than the voltage VR3. After programming, programming the MSB and programming the flag cell to have a threshold voltage higher than the voltage VR3 to indicate that the MSB is programmed.

  In order to solve the above problems, the multi-bit storage cell includes at least one flag cell and a plurality of multi-bit storage cells, and each multi-bit storage cell stores different amounts of charge used for data to be represented. The programming method in the multi-level non-volatile memory according to an embodiment of the present invention, wherein the data is represented by a plurality of data pages, each programmed storage cell includes a first range and a plurality of subsequent ranges. Continuously programming at least one data page of the plurality of data pages to have a threshold voltage belonging to one of a plurality of threshold voltage ranges including at least one; Programming a flag cell with a threshold voltage belonging to a threshold voltage range representing the number of data pages to be programmed; Including. At this time, each of the plurality of subsequent ranges is equal to or higher than the respective verification voltage, and is read at the respective read voltage, and the read voltage corresponding to the predetermined range is lower by the margin M than the corresponding verification voltage. Also, the threshold voltage range of the flag cell is equal to or higher than the verification voltage of the flag cell, and is read at the flag cell read voltage, and the flag cell read voltage is lower by an increased margin than the margin.

  In order to solve the above problems, the multi-bit storage cell includes at least one flag cell and a plurality of multi-bit storage cells, and each multi-bit storage cell stores different amounts of charge used for data to be represented. The controller can control the memory by a programming method in a multi-level non-volatile memory, wherein the data is represented by a plurality of data pages. The controller according to an embodiment of the present invention can store each programmed storage cell. At least one data page among the plurality of data pages so that has a threshold voltage belonging to one of a plurality of threshold voltage ranges including the first range and a plurality of subsequent ranges. Program step and at least one flag cell with a threshold voltage range representing the number of data pages to be programmed. Comprising the steps of: programming in threshold voltage belonging to. At this time, each of the plurality of subsequent ranges is equal to or higher than the respective verification voltage, and is read at the respective read voltage, and the read voltage corresponding to the predetermined range is lower by the margin M than the corresponding verification voltage. Also, the threshold voltage range of the flag cell is equal to or higher than the verification voltage of the flag cell, and is read at the flag cell read voltage, and the flag cell read voltage is lower by an increased margin than the margin.

  According to the present invention, a multi-level nonvolatile memory device can be programmed with a high degree of accuracy.

  For a full understanding of the present invention and the operational advantages of the present invention and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating the preferred embodiments of the invention and the contents described in the drawings. Must.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same members.
Embodiments of the present invention relate to a method for highly accurate programming in a multi-level flash memory device such as a flash memory of 2 bits or more.

  FIG. 4 is a diagram illustrating four states for the threshold voltage of a cell in 2-bit multilevel flash. In graph 400, the x-axis represents the threshold voltage and the y-axis represents the probability distribution of the programmed cell threshold voltage. The threshold voltage of the cell appears as a probability distribution, and the state for the charge of the cell appears as a curve representing that the cell programmed with a particular state has a particular threshold voltage.

  The threshold voltage probability curve of a given cell is one of the four possible threshold voltage probability curves of probability curves 410, 420, 430, and 440 that are represented by the first state, the second state, the third state, and the fourth state, respectively. Distributed as one. In an ideal case, the cell having the threshold voltage probability curve 410 does not generate current even when any one of the test voltages VR1, VR2 and VR3 is applied. In addition, the cell having the threshold voltage probability curve 420 generates a current when the read voltage VR1 is applied, but this is not the case depending on the read voltages VR2 and VR3. Similarly, a cell with threshold voltage probability curve 430 generates current with read voltages VR1 and VR2, but not with read voltage VR3, and a cell with threshold voltage probability curve 440 has any read voltage VR1. , VR2 and VR3 generate current even when applied. Therefore, in an ideal case, by reading the cell for each of the three voltages VR1, VR2 and VR3, it is possible to distinguish which of the four states the cell is in.

  It is desirable to provide margins between the threshold voltage ranges 420, 430 and 440 and the measured voltages VR1, VR2 and VR3, respectively. This margin is indicated by a distance M. At this time, the distance M represents the distance from the measured voltage to the adjacent verification voltages VF1, VF2, and VF3 that represent the start of the threshold voltage ranges 420, 430, and 440, respectively.

  While the exact threshold voltage range is selected by design and process constraints, the specific voltages are provided as examples only. The cell state is then planned to be set by any voltage range. For example, the first state 410 is represented by a cell having a threshold voltage of about −2V or less. The second state 420 is represented by a cell having a threshold voltage in the range of about 0.3 to 0.7V. Similarly, the third state 430 has a threshold voltage in the range of about 1.3 to 1.7V, and the fourth state 440 has a threshold voltage in the range of about 2.3 to 2.7V. Appears by cell.

  As described above, as the number of possible memory states of a cell increases, the threshold voltage range corresponding to a given state becomes even narrower. So is the margin that distinguishes the threshold voltage from the measured voltage. Therefore, it is of utmost importance to program each cell with a high degree of accuracy.

  One of the methods for improving the accuracy of the program is the ISPP (Incremental Step Pulse Programming) method. FIG. 5 is a diagram showing a curve form of a general program voltage not using the ISPP method.

  FIG. 6 illustrates a program voltage waveform according to the ISPP method according to an embodiment of the present invention. The use of the waveform shown in FIG. 6 is easier to reduce cell threshold voltage variations than when using the waveform of FIG. In FIG. 6, the electric signal 600 (Vpgm) includes a pulse, and each pulse has a width corresponding to the time constituting the program section 620. Each pulse may be generated with a difference of only the time constituting the verification interval 640. Each voltage of the continuous pulse is increased by, for example, a voltage 630 (ΔVpgm). At this time, the voltage 630 (ΔVpgm) may be 0.5V. Also, the first pulse 610 can be 15V. Continuous pulses increase to a maximum voltage of 650. At this time, the maximum voltage 650 may be 19V. The cell threshold voltage is tested periodically, such as when testing every pulse, or every three pulses, to see if an appropriate threshold voltage is reached. If the appropriate threshold voltage is not reached, an additional pulse is applied to the cell.

  After the cell is programmed, the cell is read to see if the cell was programmed correctly. For example, the threshold voltage is tested to see if it was set high enough. If not, additional pulses are applied until the threshold voltage is sufficiently high.

  The verification test voltage is used to check the programmed threshold voltage. The verification voltage VF is different from the read voltage VR used to read the cell. For example, the verification voltages VF1, VF2, and VF3 described in connection with the distance M are higher than the corresponding read voltages VR1, VR2, and VR3 (see FIG. 4).

  The state of each cell of the multi-bit memory device is represented by a number. For example, in a 2-bit flash memory, each of the four possible states is represented by a 2-bit binary number. For example, the first unprogrammed state is represented by “11”, the second state is represented by “01”, the third state is represented by “10”, and the fourth state is represented by “00”. Is done. FIG. 7 is a diagram illustrating four states in a 2-bit memory according to an embodiment of the present invention. The threshold voltage probability distribution 700 of FIG. 7 for each of the four states is shown. A given cell has one threshold voltage at one time, and the threshold voltage is set to one of four states. At this time, the accurate threshold voltage has a distribution of states corresponding to the probability curve.

  The 2-bit binary number includes MSB and LSB. In the first unprogrammed state 710, the MSB 712 is “1” and the LSB 718 is “1”. Also, in the second state 720, the MSB 722 is “0” and the LSB 728 is “1”. Similarly, in the third state 730, the MSB 732 and LSB 738 are “1” and “0”, respectively, and in the fourth state 740, the MSB 742 and LSB 748 are each “0”.

  As described above, data is stored in the cell by supplying a corresponding amount of charge to the floating gate to have a threshold voltage in the desired range (one of the four states). Thus, data is stored by programming the cell, but in 2-bit memory, 2-bit data is stored in each cell. If required, a 2-bit memory cell may be programmed with only one bit of data. Also, a cell programmed with only the first bit of data is later programmed with the second bit of data. When one bit is programmed in one cell, that cell contains only LSB data. When 2-bit data is programmed into one cell, that cell contains both LSB data and MSB data. If necessary, the cell is first programmed (and verified) with LSB data and then the MSB data is programmed (and verified). At this time, the program is executed in units of pages. At this time, the LSB cell of the physical page is considered as the LSB logical page, and the MSB cell of the physical page is considered as the MSB logical page. Thus, the process of programming the physical page includes first programming (and verifying) the LSB logical page and then programming (and verifying) the MSB logical page.

FIG. 8 is a diagram illustrating a method for programming a cell according to an embodiment of the present invention. Line 800A represents the case where only LSB data is programmed into the cell. The unprogrammed state of the LSB data is “1”. If data “0” is to be stored in the cell, the cell is programmed until the threshold voltage is verified to be within the “0” state range (> VF2 ^* ). Such a program step is indicated by P1.

  If only LSB data is stored in the cell, the cell is read with one voltage VR1. If a current flows through the cell at the read voltage VR1, the cell is read as an unprogrammed state “1”. On the other hand, if no current flows through the cell at the read voltage VR1, the cell is read as “0”.

  As adjacent cells are located very close, the program for the adjacent cells affects the threshold voltage of a given cell. Such a phenomenon is called a coupling phenomenon. The probability curve is broadened by the electric potential of the charge with respect to the threshold voltage of the cell affected by the coupling phenomenon. Line 800B represents the case where only LSB data is programmed into the cell and the threshold voltage probability curve is extended by D1.

  According to the embodiment of the present invention, when the MSB page is programmed after the LSB page is programmed, the LSB data “1” of the line 800B corresponds to the data “11” state of the line 800C and is indicated by P2. Through the program steps, the threshold voltage is programmed until it is verified that it falls within the “01” state range (> VF1) of line 800C. Also, the LSB data “0” of the line 800B is programmed through the program step indicated by P3 until it is verified that the threshold voltage falls within the “10” state range (> VF2) of the line 800C. . Similarly, the LSB data “0” on line 800B is programmed through the program step indicated by P4 until it is verified that the threshold voltage falls within the “00” state range (> VF3) of line 800C. The Each program step can use the ISPP method described above.

  When reading data from the memory device, it is necessary to know whether only LSB data is stored in the cell, or whether both LSB data and MSB data are stored. For example, to read only LSB data, one read voltage VR1 is required, while to read both LSB data and MSB data, three read voltages VR1, VR2, and VR3 are required. The Further, as indicated by line 800B, the “0” state of the LSB data can include both sides of VR2.

  VF1 is higher than VR1 by a margin M. Similarly, VF2 and VF3 are higher by a margin M than VR2 and VR3, respectively. At this time, the margins M can be the same. The presence of the margin improves the reading accuracy of the memory device.

  Accordingly, embodiments of the present invention comprise a cell that indicates whether MSB data is stored. At this time, such a cell is called an MSB flag cell. Different from the MSB flag cell, the remaining cells are called data storage cells. The MSB flag cell is read to accurately read the stored data regardless of whether only the LSB data is stored or whether both the LSB data and the MSB data are stored. Each page includes at least one MSB flag cell to indicate whether the MSB data is stored on the page.

  Line 800D shows the MSB flag cell in the unprogrammed state “1”. This state is used to indicate that the MSB data is not programmed. Line 800E shows the MSB flag cell in the “0” state. This state is used to indicate that the MSB data is being programmed. At this time, the cell is programmed through the program step indicated by P5 until it is verified that the threshold voltage falls within the range of the line “0” state (> VF3).

As described above, the “0” state of the MSB flag is programmed until the threshold voltage of the MSB flag cell is higher than VF3. Even if the threshold voltage in this state is higher than VR3 by a margin M, the MSB flag is read with a voltage of only the margin increased from VR2. Here, the increased margin is indicated by M _Enhanced .

  Despite unintentional, charge leakage from the cell's floating gate can cause a “charge loss” phenomenon. The charge can be lost due to a lack of an insulating layer. The loss of charge can be such that the threshold voltage is below the required level. This appears as if the threshold voltage probability curve is distributed in the lower voltage direction.

  The storage cell has a higher level of error correction means than the MSB flag cell. Furthermore, charge loss in one storage cell only makes the cell unreadable, but charge loss in the MSB flag cell makes the entire page unreadable. Therefore, charge loss in the MSB flag cell can be a particular problem.

For this reason, the increased margin M _Enhanced is set sufficiently large to accurately read the MSB flag cell even if charge loss occurs from the floating gate of the MSB flag cell. According to the embodiment of the present invention, the MSB flag “0” state is positioned so that the increased margin M _Enhanced has the same distribution curve as the storage cell “00” state (line 800C “00”). . By defining the “0” state of the MSB flag cell as described above, the MSB flag cell can be accurately read even if charge loss occurs.

FIG. 9 is a diagram illustrating a programming method in a multi-level nonvolatile memory device according to an embodiment of the present invention. First, the LSB data of the storage cell is programmed (S910). As described above, to save the “0” state in the cell, the LSB logical page is programmed by the ISPP method until it is verified that the threshold voltage is higher than VF2 ^* . If a “1” state is required, there is no need to perform a separate program step. The MSB data is then used to program the “00” state (S920A), but is similarly programmed by the ISPP method until it is verified that the threshold voltage is higher than V3. This program step uses an ISPP scheme to further supply charge to the LSB state “0”.

  The MSB flag cell is programmed from an unprogrammed “1” state to a programmed state “0” to indicate whether the MSB data has been programmed. This program step includes an ISPP scheme for supplying additional charge to the “1” state to reach the “0” state. As described above, the “0” state of the MSB flag cell is programmed until it is verified that the threshold voltage is higher than VR3. Steps S920A and S920B are performed using the same VR3 voltage. The MSB data is then used to program the “01” and “10” states (S930). This programming step sets the “1” and “0” states to reach the “01” and “10” states, respectively, by programming until the threshold voltages are verified to be higher than VF1 and VF2, respectively. Includes ISPP scheme for supplying additional charge. The “11” state is formed by leaving a cell in the “1” state.

  However, when the MSB data is programmed to “00” (S920A) and the power supply is interrupted while the MSB flag cell is programmed (S920B), the above process is not performed completely. It becomes a problem. In such a case, LSB data is potentially read while MSB data is not read, and the state of the MSB flag cell cannot be clearly defined. Due to the ambiguous state of the MSB flag cell, even LSB data cannot be read.

  Embodiments of the present invention consider both the method of programming the next main memory cell and the method of programming the flag cell when the main memory cell is programmed. The method for programming the main memory cell and the method for programming the flag cell, which will be described later, are not necessarily mutually dependent or require a coupling relationship. In particular, the method of programming the main memory cell described later can be combined with another known flag cell programming method that is not a method of programming the flag cell described later. Similarly, a method for programming a flag cell, which will be described later, can be combined with another known main memory cell programming method which is not a method for programming a main memory cell, which will be described later.

  10 and 11 are diagrams illustrating a programming method in a multi-level nonvolatile memory device according to an embodiment of the present invention. First, the LSB data is programmed by the method described above (S1010, line 1100A). The “0” state is then formed into the advanced state “A” until it is verified that the threshold voltage is higher than VF2 (S1020, line 1100B). The state programmed in VF2 defines the state as “10” state. However, this state is formed when a “10” or “00” state is required. The MSB flag cell is left unprogrammed at this step (1110B). Then, if the “00” state is required, the “00” state is programmed by programming the “A” state until it is verified that the threshold voltage is higher than VF3, or “10”. If the status is required, no additional programming is done (S1030A, line 1110C). At this time, the MSB flag is programmed by programming the MSB flag cell until it is verified that the threshold voltage is higher than VF3 (S1030B, line 1110C). Program steps S1030A and S1030B are performed simultaneously or nearly simultaneously. Finally, the “01” state is programmed by programming the “1” state until it is verified that the threshold voltage is higher than VF1 (S1040A, line 1100D).

  Although the above-described embodiments of the present invention have been described for a 2-bit multi-level nonvolatile memory device, the present invention is not limited to this and can be applied to any bit multi-level nonvolatile memory device. For example, the present invention is also applied to a 3-bit multi-level nonvolatile memory device. Each cell of the 3-bit device has eight states of “111”, “011”, “101”, “001”, “110”, “010”, “100”, and “000”. The 3-bit memory device includes a first logical page, a second logical page, and a third logical page instead of the LSB page and the MSB page. At this time, the 3-bit memory device includes a first flag cell indicating when the second page is programmed and a second flag cell indicating when the third page is programmed. In an embodiment where two flag cells are used, for example, the first flag cell is programmed to a “0” state to indicate that the second data page is programmed, and the second flag cell is programmed to the third data page. Programmed to "0" state to indicate that it is being programmed.

  On the other hand, a single flag cell may be provided that represents when the second page is programmed and when the third page is programmed. The single flag cell is set to an unprogrammed “111” state, for example, indicating that none of the second and third data pages are initially programmed. The flag cell is programmed to a “010” state to indicate that the second data page is loaded, and is programmed to a “000” state to indicate that the third data page is loaded. Although the present invention is applied to both cases, the case where a single flag cell is provided will be described for convenience of explanation.

  In a memory device of 3 bits or more, there are 8 or more states and there are 3 or more flag cells, or there are 3 or more states in a single flag cell.

  12A to 12D are diagrams illustrating a 3-bit memory device according to an embodiment of the present invention. A more detailed description of how to program a cell is similar to the previously described embodiment. From the features of such embodiments, memory devices with more than 3 bits are estimated.

  According to an embodiment of the present invention, the storage cell does not advance before programming the second and third pages. 12A and 12B are such embodiments. As shown in FIGS. 12A and 12B, the first page is programmed (lines 1417, S1423). The flag cell initially has a “111” state (line 1418). The second page data is then programmed (lines 1419, S1424) and the flag cell is programmed at a level that indicates that the second data page is programmed (lines 1420, S1425). For example, the flag cell is programmed to the “010” state. S1424 and S1425 can occur simultaneously or nearly simultaneously. The third data page is programmed (lines 1421, S1426) and the flag cell is programmed at a level indicating that the third data page is programmed (lines 1422, S1427). For example, the flag cell is programmed to the “000” state. Program steps S1426 and S1427 may also occur simultaneously or nearly simultaneously.

  As shown in FIGS. 12C and 12D, the first page is programmed (lines 1430, S1440). The flag cell initially has a “111” state (line 1431). The “0” bit advances to prevent data corruption due to the occurrence of an unexpected interrupt on the first page data (lines 1432, S1441). At this time, the flag cell maintains the “111” state (line 1433). The second page data is then programmed (lines 1434, S1442), and the flag cell is programmed at a level indicating that the second data page is programmed (lines 1435, S1443). For example, the flag cell is programmed to the “000” state. Program steps S1442 and S1443 may occur simultaneously or nearly simultaneously.

  The second page data states “01”, “10”, and “00” are advanced to prevent data corruption due to an unexpected interrupt of the second page data (lines 1436, S1444). At this time, the flag cell also advances from the “000” state to the “100” state (lines 1437, S1445). The third data page is programmed (lines 1438, S1445) and the flag cell is programmed at a level indicating that the third data page is programmed (lines 1439, S1446). For example, the flag cell is programmed to the “000” state. Program steps S1445 and S1446 may also occur simultaneously or nearly simultaneously.

  The multi-level non-volatile memory device can use a structure applicable to data cell programming. FIG. 13 is a chart illustrating bias conditions for controlling a 2-bit multi-level nonvolatile memory device according to an embodiment of the present invention. This chart is used for erasing, programming, inhibiting, reading and verifying storage cells and flag cells according to embodiments of the present invention.

  The diagram of FIG. 13 summarizes the voltages applied to operate a memory cell array according to an embodiment of the present invention. The upper column of the table defines the memory operation to be performed. This operation includes erasing the memory, programming the memory, prohibiting the memory program and reading the LSB, MSB, and flag cell data. For each operation, the first row classifies each line to which the voltage used to perform the required operation is applied. The remaining columns and rows of the table define the voltage applied to each line listed in the first row to perform the required action listed in the upper column. The voltage is described as a specific voltage such as 0V or 20V. The voltage is also described in the form of a signal, such as Vcc or Vpgm. “Floating” indicates that the line is not set to a special voltage. “H” or “L” indicates that a high signal or a low signal is transmitted to the line. Vread is applied to an unselected word line when reading data. Vpass is applied to unselected word lines when programming.

  FIG. 14 schematically illustrates a memory page according to an embodiment of the present invention. Memory page 1600 shows a plurality of data storage cells on a plurality of data storage bit lines. The data storage bit lines are controlled by data storage circuits 1620, 1630 and 1640 which form a page buffer circuit together with a flag storage data circuit 1650 which controls the bit line connected to the flag cell 1605. The data storage cell and the flag cell constitute a data block 1610.

  FIG. 15 is a diagram illustrating a memory system including a flash memory according to an embodiment of the present invention. The memory system includes a flash memory 1500 and a memory controller 1510. The memory controller 1510 controls the operation of the flash memory 1500.

  Many drawings show a cell having a plurality of threshold voltage curves, which are shown to represent any possible state. It should be understood that a particular cell has a threshold voltage range at a particular time. Furthermore, when it comes to program state, it must be understood that the program is simply done to the extent required. Thus, for example, when a step for programming a program cell to a “00” state is described, this programming step is performed only if such a state is required. It must be understood that if the required state has already been achieved, the cell will not program any further states.

  As described above, the optimal embodiment has been disclosed in the drawings and specification. Although specific terms are used herein, they are merely used to describe the present invention and limit the scope of the invention as defined in the meaning and claims. It was not used for that purpose. Accordingly, those skilled in the art will appreciate that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The present invention is applicable to a technical field related to a nonvolatile memory device.

It is a figure which shows the single cell of flash memory. It is a figure which shows an example of the string of NAND flash memory. It is a figure which shows an example of a flash memory block. FIG. 6 is a diagram showing four states for the threshold voltage of a cell in 2-bit multilevel flash. It is a figure which shows the curve form of the general program voltage which does not use an ISPP system. It is a figure which shows the waveform of the program voltage by the ISPP system by embodiment of this invention. FIG. 4 is a diagram illustrating four states in a 2-bit memory according to an embodiment of the present invention. FIG. 4 illustrates a method for programming a cell according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a programming method in a multi-level nonvolatile memory device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a programming method in a multi-level nonvolatile memory device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a programming method in a multi-level nonvolatile memory device according to an embodiment of the present invention. FIG. 3 illustrates a 3-bit memory device according to an embodiment of the present invention. FIG. 3 illustrates a 3-bit memory device according to an embodiment of the present invention. FIG. 3 illustrates a 3-bit memory device according to an embodiment of the present invention. FIG. 3 illustrates a 3-bit memory device according to an embodiment of the present invention. 6 is a chart showing bias conditions for controlling a 2-bit multi-level nonvolatile memory device according to an embodiment of the present invention. FIG. 3 schematically illustrates a memory page according to an embodiment of the invention. 1 is a diagram illustrating a memory system including a flash memory according to an embodiment of the present invention.

Explanation of symbols

VF1, VF2, VF3 Verification voltage VR1, VR2, VR3 Reference voltage

Claims (28)

The multi-bit storage cell includes at least one flag cell and a plurality of multi-bit storage cells, and each multi-bit storage cell can store different amounts of charge used for data to be represented. In a programming method in a multi-level non-volatile memory comprising a bit and a most significant bit,
When the magnitudes of the reference voltages VR1, VR2 and VR3 are VR1 <VR2 <VR3,
When the first value is stored in the storage cell, the threshold voltage is lower than the voltage VR1.
When storing the second value in the storage cell, the storage cell has a threshold voltage higher than the voltage VR1 and lower than the voltage VR2.
When storing the third value in the storage cell, the storage cell has a threshold voltage higher than the voltage VR2 and lower than the voltage VR3;
If a fourth value is to be stored in the storage cell, the least significant bit is first programmed in the storage cell to have a threshold voltage higher than the voltage VR3, and then the most significant bit is programmed.
Programming the flag cell to have a threshold voltage higher than the voltage VR3 to indicate that the most significant bit is programmed. How to program.   The method according to claim 1, wherein the multi-level non-volatile memory is a flash memory.   3. The program method according to claim 2, wherein the multi-level non-volatile memory is a NAND memory.   The method of claim 1, wherein the steps of programming the least significant bit and the most significant bit are each programmed by an ISPP method. The programming method is:
The method of claim 1, further comprising selecting at least one reference voltage for reading data according to a flag cell state. The programming method is:
The method of claim 1, further comprising reading the flag cell with the reference voltage VR2. The voltage VR1 is 0V,
The voltage VR2 is 1 to 2V,
The method of claim 1, wherein the voltage VR3 is 2.5 to 3.5V. The multi-bit storage cell includes at least one flag cell and a plurality of multi-bit storage cells, and each multi-bit storage cell can store different amounts of charge used for data to be represented. In a controller for controlling a memory by a programming method in a multi-level non-volatile memory, comprising a bit and a most significant bit,
The programming method is:
When the magnitudes of the reference voltages VR1, VR2 and VR3 are VR1 <VR2 <VR3,
When the first value is stored in the storage cell, the threshold voltage is lower than the voltage VR1.
When storing the second value in the storage cell, the storage cell has a threshold voltage higher than the voltage VR1 and lower than the voltage VR2.
When storing the third value in the storage cell, the storage cell has a threshold voltage higher than the voltage VR2 and lower than the voltage VR3;
If a fourth value is to be stored in the storage cell, the least significant bit is first programmed in the storage cell to have a threshold voltage higher than the voltage VR3, and then the most significant bit is programmed.
Programming the flag cell to have a threshold voltage higher than the voltage VR3 to indicate that the most significant bit is programmed.   The controller of claim 8, wherein the multi-level non-volatile memory is a flash memory.   The controller of claim 9, wherein the multi-level nonvolatile memory is a NAND memory.   9. The controller of claim 8, wherein the steps of programming the least significant bit and the most significant bit are each programmed according to an ISPP method. The programming method is:
The controller of claim 8, further comprising selecting at least one reference voltage for reading data according to a flag cell state. The programming method is:
The controller of claim 8, further comprising: reading the flag cell with the reference voltage VR2. The voltage VR1 is 0V,
The voltage VR2 is 1 to 2V,
The controller of claim 8, wherein the voltage VR3 is 2.5 to 3.5V. The multi-bit storage cell includes at least one flag cell and a plurality of multi-bit storage cells, and each multi-bit storage cell can store different amounts of charge used for data to be represented. In a program method in a multi-level non-volatile memory represented by a data page of
At least one of the plurality of data pages such that each programmed storage cell has a threshold voltage belonging to one of a plurality of threshold voltage ranges including a first range and a plurality of subsequent ranges. Continuously programming the above data pages;
Programming at least one or more flag cells with a threshold voltage belonging to a threshold voltage range representing the number of data pages to be programmed;
The plurality of subsequent ranges are:
Each is defined as equal to or higher than its own verification voltage, each read at its own reading voltage, and the reading voltage corresponding to a predetermined range is lower than the corresponding verification voltage by a margin M,
The threshold voltage range of the flag cell is
A programming method in a multi-level non-volatile memory, which is equal to or higher than a verification voltage of a flag cell, is read at a flag cell read voltage, and the flag cell read voltage is lower by an increased margin than the margin. The at least one flag cell is a single flag cell;
The multi-level non-volatile memory of claim 15, wherein the single flag cell is programmed with one of a plurality of threshold voltages for representing the number of data pages to be programmed. How to program in The at least one flag cell is a plurality of flag cells;
The method of claim 15, wherein each of the plurality of flag cells is programmed to represent the number of data pages to be programmed.   The method according to claim 15, wherein the multi-level non-volatile memory is a flash memory.   The method according to claim 15, wherein the multi-level non-volatile memory is a NAND memory.   The method according to claim 15, wherein the steps of programming the least significant bit and the most significant bit are each programmed by an ISPP method. The programming method is:
The method of claim 15, further comprising selecting at least one reference voltage for reading data according to a flag cell state. The multi-bit storage cell includes at least one flag cell and a plurality of multi-bit storage cells, and each multi-bit storage cell can store different amounts of charge used for data to be represented. In a controller for controlling a memory by a programming method in a multi-level non-volatile memory represented by a data page of
The programming method is:
At least one of the plurality of data pages such that each programmed storage cell has a threshold voltage belonging to one of a plurality of threshold voltage ranges including a first range and a plurality of subsequent ranges. Continuously programming the above data pages;
Programming at least one or more flag cells with a threshold voltage belonging to a threshold voltage range representing the number of data pages to be programmed;
The plurality of subsequent ranges are:
Each read voltage is equal to or higher than its own verification voltage, each read at its own read voltage, and the read voltage corresponding to the predetermined range is lower than the corresponding verification voltage by a margin M,
The threshold voltage range of the flag cell is
A controller that is greater than or equal to a flag cell verification voltage and is read at a flag cell read voltage, the flag cell read voltage being lower by an increased margin than the margin. The at least one flag cell is a single flag cell;
The controller of claim 22, wherein the single flag cell is programmed with one of a plurality of threshold voltages for representing the number of data pages to be programmed. The at least one flag cell is a plurality of flag cells;
The controller of claim 22, wherein each of the plurality of flag cells is programmed to represent the number of data pages to be programmed.   The controller of claim 22, wherein the multi-level non-volatile memory is a flash memory.   The controller of claim 22, wherein the multi-level non-volatile memory is a NAND memory.   The controller of claim 22, wherein the steps of programming the least significant bit and the most significant bit are each programmed in an ISPP scheme.   23. The controller of claim 22, further comprising selecting at least one reference voltage for reading data according to a flag cell state.

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