JP2008077151A - Shared memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shared memory device for efficiently connecting and expanding a plurality of processors in a scalable way via memories and achieving a simple redundant configuration. <P>SOLUTION: The shared memory device includes a plurality of processors 12-0 to 12-16, a plurality of memory modules 14-0 to 14-63 accessible from the processors, a connection part 13 to which only a specified processor among the plurality of processors is connectable to a specified memory module. The plurality of processors are accessible to memory systems M0-M15 formed by one or more memory modules through the connection part. The memory system accessible from the different processors shares a part of the memory modules to be accessed from different processors, and has a redundant function allowing redundancy to the plurality of processors. The processors 12 to 16 are processors for redundancy. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a shared memory device in which a plurality of memory systems including a processing device such as a processor element (PE) are mixedly mounted and the memory of each system is shared.

If an architecture emphasizing parallel processing is employed in a system in which a plurality of memory systems are mixed, for example, a configuration as shown in FIG. 1 is obtained.
In the configuration of FIG. 1, PEs (processor elements) 1-1 to 1-4 and memories 2-1 to 2-4 are connected one-to-one because priority is given to parallel processing.
In the configuration of FIG. 1, PE1 and memory 2 are connected in a one-to-one relationship in order to prioritize parallel processing, but PE1 uses a path through a higher-level device to refer to data of adjacent PEs. There is a need.

Therefore, a configuration in which connection from the PE circuit 1 directly to the adjacent memory is generally performed by a crossbar (Xbar) 3 as shown in FIG.
USP 5,471,592

  In a system with multiple PEs as described above, as shown in FIG. 3, when data is shared via memory and efficient and scalable connection expansion is performed, the connection between PEs and memory increases linearly with respect to the number of PEs. There was a problem of not (in short, it increases rapidly).

As a memory sharing system, it was either SIMD or MIMD before Patent Document 1 (US 5,471,592; Multi-Processor with crossbar link of processors and memories). A memory system including both functions is required. Therefore, the basic method has been proposed.
In this case, efficient multi-PE processing is realized by changing the connection destination of the PE and the memory instead of transferring data, and has the following three types of connections.

A global connection that can access the entire memory,
Local connection that can connect to a specific PE,
Instruction transfer path for transferring PE execution instructions,
It is three.

  Each crossbar switch has a mechanism for giving priority in the vertical direction (direction in which one memory is connected) (= equivalent to each memory), and is determined by a round-robin method.

  However, since there is no mention of enlarging the connection when a very large number of PEs are crossbar-connected, there is no sudden increase in crossbar connection when the number of PEs is increased. The countermeasure method is not considered at all.

  As shown in FIGS. 4A and 4B, hierarchization of data transfer paths has also been proposed in order to suppress an increase in data transfer paths when PEs are increased. In order to configure the structure, a mechanism that is unnecessary for the original data transfer such as the installation of the connection port 6 is required, which is wasteful.

Further, as in FIG. 5 (Failure Avoidance for Array Structure Connected to Crossbar), one of the array elements has failed by simply adding a redundant portion to the array structure connected to the crossbar. In order to be able to utilize alternative array elements in some cases, the crossbar connection is increased by the number of array elements.
Even if array redundancy is possible with this method if the number of array elements is small, the crossbar connection for redundancy increases rapidly if the number of array elements increases, which is a drag on system implementation.

  An object of the present invention is to provide a shared memory device capable of efficiently and scalablely connecting and expanding a plurality of processing devices via a memory and realizing a simple redundant configuration.

  A shared memory device according to a first aspect of the present invention includes a plurality of processing devices, a plurality of memory modules accessible by the processing device, and a specific memory module only among the plurality of processing devices. The plurality of processing devices can access a memory system formed by one or a plurality of memory modules via the connection portion, and can be accessed by different processing devices. The memory system shares a part of memory modules accessed by different processing devices, and has a redundancy function that enables redundancy for the plurality of processing devices.

  Preferably, the redundancy function is a shift redundancy function.

  Preferably, the memory system is formed such that the shared memory module can be accessed by processing devices located close to each other.

  Preferably, there is an arbitration circuit that executes prioritization when there are access requests from a plurality of processing devices simultaneously to the same memory module, and performs access control according to the priorities.

  Preferably, it has a controller that can communicate with the outside and controls access to the plurality of memory modules, and the controller can access all the memory modules via the connection unit.

  A shared memory device according to a second aspect of the present invention includes a plurality of processing devices, a plurality of memory modules, and a connection unit in which only a specific processing device among the plurality of processing devices can be connected to a specific memory module, A controller capable of communicating with the outside and controlling access to the plurality of memory modules, wherein the plurality of processing devices access a memory system formed by one or a plurality of memory modules via the connection unit. The memory system that can be accessed by different processing devices partially shares a memory module that is accessed by different processing devices, and includes a plurality of shared memories including a redundant function that can be made redundant to the plurality of processing devices And a controller of each shared memory device is connected by a bus.

According to the present invention, for example, when any of a plurality of processing devices has a failure, the processing device is configured to be redundant by using a redundancy function, for example, shift redundancy.
The plurality of processing devices access the memory module of the memory system via the connection unit. At this time, the memory systems that can be accessed by different processing devices partially share memory modules that are accessed by different processing devices. That is, partial sharing.

  According to the present invention, it is possible to efficiently expand and connect a plurality of processing devices via a memory, and it is possible to realize a simple redundant configuration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 6 is a system configuration diagram of the shared memory device according to the embodiment of the present invention.

6 includes a direct memory access controller (DMA controller) 11, a plurality (16 in FIG. 5) of PE cores 12-0 to 12-16, partially overlapping multiports and shift redundancy as connection portions. A circuit (hereinafter referred to as an overlap multiport) 13, a memory bank (for example, SRAM bank) 14-0 to 14-63 as a plurality (64 in FIG. 5) of memory modules, and an arbitration circuit 15 are included.
In the shared memory device 10 of the present embodiment, the PE core 12-16 is provided as a redundant PE core, and when any PE core has a failure, shift redundancy as described later is performed. It is configured to be possible.

In the shared memory device 10 of FIG. 6, the memory banks 14-0 to 14-63 are divided into a plurality of memory systems M0 to M15 formed by adjacent eight banks.
For example, the memory system M0 is formed by eight memory banks 14-0 to 14-7.
The memory system M1 adjacent to the memory system M0 is formed by eight memory banks 14-4 to 14-11 sharing the four memory banks 14-4 to 14-7 of the memory system M0.
Similarly, the memory system M2 adjacent to the memory system M1 is formed by eight memory banks 14-8 to 14-15 sharing the four memory banks 14-8 to 14-11 of the memory system M1. Yes.
Hereinafter, the memory systems M3 to M15 are formed by eight memory banks in a form of sharing four memory banks of adjacent memory systems.
However, only the memory system M15 is formed by four memory banks.

In the shared memory device 10 of FIG. 5, each PE core 12-0 to 12-15 (16) can be accessed, for example, by 8 banks (16 kBytes), and the PE cores 12-0 to 12-15 (16). These accessible banks overlap (8kByte) between multiple PEs, such as neighbors.
Not a full crossbar connection and some connections are not made. Access competition to the overlapping SRAM bank is avoided by arbitration.
The efficiency decreases when one PE core wants to access the SRAM bank beyond the direct connection area at the same time, but the number of shared bangs can be set so that such a case becomes a rare case. It is possible to prevent the decrease in transfer efficiency of the system from contributing to a decrease in the overall system efficiency.

  When performing partial sharing of such a memory bank, etc., if the PE core that is not the end fails, the status of the shared memory bank has changed, causing changes in the execution program, changes in data delivery, etc. However, a redundancy scheme that degrades efficiency is not allowed. For this reason, the PE core relationship as viewed from the memory is not changed regardless of which PE fails. As a representative method, shift redundancy is performed on the PE core.

  FIG. 7 is a diagram for explaining a method of inserting a shift switch when a shift redundant configuration is employed.

In FIG. 7, shift switch circuits 21-0 to 21-N are inserted between the PE cores 12-0 to 12-N and 12-R (redundant PE cores) and the general logic circuit 20, and the PE cores The state of redundancy was shown.
The shift switch circuits 21-0 to 21-N include a multiplexer (mux1) 211 that selects a signal on the logic circuit 20 side and a multiplexer (mux2) 212 that selects a signal on the PE core side.

When each PE core fails, the function is passed to the logically adjacent PE core by passing the signal to other logically adjacent PE cores. The function is handed over to the next PE core, and the same handing is performed until the redundant PE core 12-R is reached.
For example, when the PE core 12-1 fails, the input signal to the PE core 12-1 is also input to the PE core 12-2, and the PE core 12-2 originally inputs to the PE core 12-2. An arithmetic process or the like is performed using the input signal to the PE core 12-1 instead of the (connected) input signal.
Further, the output signal from the PE core 12-1 to the general logic circuit 20 controls the selection signal of the multiplexer 222 so as to transmit the output signal from the PE core 12-2.

The power consumption is reduced by stopping the input change to the defective PE core. This is not necessary when the power of the defective PE core is shut off by a power gate or the like.
Since the clamp in the switch circuit is almost negligible, reducing the number of gates in the switch circuit does not lead to much reduction in overall scale and power consumption.

FIG. 8 is a diagram illustrating a connection example of signal paths of the shared memory device according to the present embodiment.
In FIG. 8, each memory system includes four memory banks for easy understanding.

  The memory system M0 is formed by the memory banks 14-0 to 14-3, the memory system M1 is formed by the memory banks 14-2 to 14-5, and the memory system M2 is formed by the memory banks 14-4 to 14-7. The memory system M3 is formed by memory banks 14-6 to 14-9.

In the shared memory device 10A of FIG. 8, there is a path for each PE core 12-0 to 12-3 to access four memory banks.
However, shift redundancy processing path unit 132 is provided between each PE core 12-0 to 12-3 and normal access path 131, and shift redundancy is provided between each PE core 12-0 to 12-3 and arbitration circuit 15. And a processing path unit 133.
In the shift redundancy processing path sections 132 and 133, the circled portions are switch mechanisms between wirings.

The PE core 12-0 is connected to the normal path 131 via the redundant path 1321, and can access the memory modules 14-0 to 14-3.
The PE core 12-1 is connected to the normal path 131 via the redundant path 1321, and can access the memory modules 14-0 to 14-3. The PE core 12-1 is connected to the normal path 131 through the redundant path 1322, and can access the memory modules 14-2 to 14-5.
The PE core 12-2 is connected to the normal path 131 via the redundant path 1322, and can access the memory modules 14-2 to 14-5. The PE core 12-2 is connected to the normal path 131 through the redundant path 1323 and can access the memory modules 14-4 to 14-7.
The PE core 12-3 is connected to the normal path 131 via the redundant path 1323 and can access the memory modules 14-4 to 14-7. The PE core 12-3 is connected to the normal path 131 through the redundant path 1324 and can access the memory modules 14-6 to 14-9.
The PE core 12-4 is connected to the normal path 131 via the redundant path 1324 and can access the memory modules 14-6 to 14-9.

The PE core 12-0 can send a signal to the arbitration circuit 15 through the redundant path 1331. The arbitration circuit 15 can send a signal to the PE core 12-0 through the redundant path 1332.
The PE core 12-1 can send a signal to the arbitration circuit 15 through the redundant path 1331 or 1334. The arbitration circuit 15 can send a signal to the PE core 12-1 through the redundant path 1332 or 1334.
The PE core 12-2 can send a signal to the arbitration circuit 15 through the redundant path 1333 or 1335. The arbitration circuit 15 can send a signal to the PE core 12-2 through the redundant path 1334 or 1336.
The PE core 12-3 can send a signal to the arbitration circuit 15 through the redundant path 1335 or 1337. The arbitration circuit 15 can send a signal to the PE core 12-3 through the redundant path 1336 or 1338.
The PE core 12-4 can send a signal to the arbitration circuit 15 through the redundant path 1337. The arbitration circuit 15 can send a signal to the PE core 12-4 through the redundant path 1338.

In the present embodiment, data transfer from the outside that is first processed by the PE core is realized by the DMA controller 11.
A data transfer method using the DMA 11 will be described with reference to FIG.

When transferring data from the outside to a specific memory bank or outputting data from a specific memory bank to the outside, the DMA controller 11 designates a transfer request from the PE cores 12-0 to 12-3 to the DMA controller 11. The transfer request to the designated address is transmitted to the arbitration circuit 15, and the transfer permission is awaited.
If the transfer permission is received from the arbitration circuit 15, the external data bus is connected to a specific memory, transfer control for the external data bus is performed while sequentially outputting the target address, and data is transferred between the external data bus and the memory. Perform transmission. The shift redundancy mechanism can be realized by a switch mechanism between wirings in the same manner as the partial shared connection of the memory.

Next, an example of data sharing and transfer between PEs will be described.
In FIG. 8, the input data of the PE core 12-0 is placed in the memory bank 14-0, and the PE core 12-0 reads and processes the contents of the memory bank 14-0, and the memory bank 14-2 and the memory bank The result is output to 14-3.
When valid data is output to the memory bank 14-2 or the memory bank 14-3, the PE core 12-0 turns on the validity confirmation bit of the specific address A-1 of the memory bank 14-2.
When the PE core 12-1 completes its processing, it checks whether the PE core 12-0 has turned on the address A-1, and if so, the memory bank 14-2 or the memory bank 14-3. Starts reading data from and computing.
The PE core 12-1 processes the data placed in the memory bank 14-2 and the memory bank 14-3 as an input and outputs the processed data to the memory bank 14-4. When the processing is completed, the PE core 12-2 requests the DMA controller 11 to transfer data to the outside, and the DMA controller 11 outputs valid data in the memory bank 14-4 via the external bus.
In the data transfer between each PE core 12-0 to 12-3 and each memory bank, each PE core transmits a data transfer request address to the arbitration circuit 15, and the arbitration circuit 15 prioritizes other PE cores and DMA controllers. Is determined by the round-robin method, and a transfer permission is issued to the PE core.

  FIG. 9 is a diagram illustrating an implementation example of the data transfer mechanism, and is a diagram illustrating an implementation example in which a multiplexer for partial sharing of a memory and a multiplexer for shift redundancy are combined into one multiplexer MUX. It is.

It is possible to suppress an increase in the number of circuits for redundancy by selecting a circuit system that realizes both of the memory sharing and shift redundancy separately, but not both.
Wirings indicated by dotted lines indicate wirings added for shift redundancy. In this example, the number of PEs actually operating is 4, the number of memory banks is 10 in total, and the number of memory banks partially shared between the PEs is 2 banks. That is, it corresponds to the configuration of FIG.

The data input to the PE core 12-0 is selected by the 4: 1 multiplexer MUX1 so that any one of the memory banks 14-0, 14-1, 14-2, and 14-3 can be selected.
The output of the PE core 12-0 is connected to one input of the multiplexer MUX2 at the input of each memory bank so that data can be transferred to any one of the memory banks 14-0, 14-1, 14-2, 14-3. Has been.
In the PE core 12-1, its input is a memory bank 14-0, 14-1 as an input from the memory bank to the PE core 12-0, which is necessary when the function of the PE core 14-0 is substituted for the shift operation. The input data is selected by the 6: 1 multiplexer MUX1 for selectively inputting the outputs from the memory banks 14-2, 14-3, 14-4, and 14-5 for normal operation.
The output of the PE core 12-1 is a memory module 14-0, 14-1 as an output destination for shift redundancy for substituting the function of the PE core 12-0, and a memory as an output destination for normal operation. The modules 14-2, 14-3, 14-4, and 14-5 are connected to the input multiplexer MUX2.
By making such a connection, the PE core 12-0 can input / output data to / from the memory modules 14-0, 14-1, 14-2, 14-3, and the PE core 12-1 Normally, data can be input / output to / from the memory modules 14-2, 14-3, 14-4, and 14-5.
When the PE core 12-0 fails, the PE core 12-1 functions as an alternative PE, so that the PE core 12-1 can input and output data to the memory modules 14-0 and 14-1. It has become.
For other PE cores 12-2, 12-3, and 12-R, a partial shared memory and shift redundancy can be realized at the same time by selecting input data by connecting a multiplexer to the input so that the same operation can be performed. It is like that.

FIG. 10 is a flowchart of access arbitration to MEM (memory bank) (2n) in PE (n) and PE (n + 1).
The access arbitration processing method for MEM (2n) in PE (n) and PE (n + 1) in FIG. 10 will be described below. Here, the PE core is described as PE.

Starting from the start immediately after resetting the chip, first, the access request to the MEM (2n) of the PE (n) is confirmed (ST1). If there is no request, the PE (n + 1) access request to the MEM (2n) is shifted to the confirmation phase (2).
When there is an access request for MEM (2n) from PE (n), PE (n) is granted access permission to MEM (2n), and PE (n + 1) is denied access to MEM (2n). Perform (ST2).
An initial value is set in a timer that counts a certain time (ST3). The timer starts counting down. The access request to the MEM (2n) of the PE (n) is confirmed again, and if there is no request, the process proceeds to (2). If there is an access request, the timer count value is confirmed, and if the timeout has not occurred, the access request confirmation for MEM (2n) of PE (n) is repeated again. If timed out, the process proceeds to (2) (ST4, ST5).

Similar processing is performed in (2). An access request for MEM (2n) of PE (n + 1) is confirmed (ST6). If there is no request, the PE (n) access request to the MEM (2n) is shifted to the confirmation phase (start).
When there is an access request for MEM (2n) from PE (n + 1), PE (n + 1) is granted access permission to MEM (2n), and PE (n) is accessed to MEM (2n). Rejection is performed (ST7).
An initial value is set in a timer that counts a certain time (ST8). The timer starts counting down. The access request to the MEM (2n) of the PE (n + 1) is confirmed again, and if there is no request, the process proceeds to (START). If there is an access request, the timer count value is confirmed, and if the timeout has not occurred, the access request confirmation for MEM (2n) of PE (n + 1) is repeated again. If timed out, the process proceeds to (START) (ST9, ST10).

  FIG. 11 is a diagram for explaining a hierarchical unit expansion method of the partially shared multiport mechanism PE. Next, an extension method in units of layers in the case of a bottleneck in DMA transfer will be described.

Regarding the data transfer between PE cores, the performance degradation due to a large amount of data transfer can be greatly reduced, but the data transfer between the outside and the memory is performed simultaneously by the PE core. When processing, the probability of collision increases.
In such a case, as shown in FIG. 11, a PE array is hierarchized.
Similar to the basic configuration of FIG. 6, a memory system 100 is configured in which 16 PE arrays and one DMA controller are connected as one layer via an AXI bus (Advanced eXtensible Interface bus) 20.
It is important to prevent the AXI hierarchy from entering even a little, and the present invention contributes to reducing this hierarchy as much as possible.

  As described above, according to the present embodiment, a plurality of PEs (processing devices) 12-0 to 12-15, a plurality of memory modules 14-0 to 14-63 accessible by the processing devices, and a plurality of Among the processing devices, only a specific processing device has a connection unit 13 connectable to a specific memory module, and the plurality of processing devices are memories formed by one or a plurality of memory modules via the connection unit Memory systems that can access the systems M0 to M15 and can be accessed by different processing devices share part of the memory modules accessed by the different processing devices, and access requests from a plurality of processing devices to the same memory module at the same time. If there is, it has an arbitration circuit 15 that executes prioritization processing and performs access control according to the priority, and shifts Since it has a long structure, the following effects can be realized.

By using a working memory module (Memory Module) used by each PE as it is for data transfer between PEs, it is possible to reduce memory modules for communication.
Only the access direction to the memory (Access) is changed, and the communication time becomes zero without limit.
Even if the number of PEs increases, the amount of connection resources between the PEs and the memory increases linearly with the number of PEs. Therefore, it is possible to easily add as many PEs as necessary in a scalable manner.
Making all PEs connectable to all memory modules is less effective for using resources, but in this embodiment, access arbitration between the same memories is limited because access arbitration between PEs is limited. Becomes simple.
In addition, a redundant structure is possible without changing the relationship of memory sharing between PEs, leading to a significant improvement in yield.
The production yield is remarkably improved by the redundancy effect while increasing the number of PEs in a scalable manner.
Rather than performing the partial shared memory processing and the redundant processing separately, there is a portion where resources can be shared, and the circuit scale can be reduced by simultaneously performing the processing.

1 is a diagram illustrating a general architecture of a multiprocessor. It is a figure which shows the architecture using a crossbar. It is a figure for demonstrating the subject of PE expansion. It is a figure which shows the structural example which used the port in order to suppress the increase in the data transfer path in the case of increasing PE. It is a figure which shows the method of the failure avoidance with respect to the array structure connected to the crossbar. 1 is a system configuration diagram of a shared memory device according to an embodiment of the present invention. It is a figure for demonstrating the insertion method of the shift switch in the case of employ | adopting a shift redundant structure. It is a figure which shows the example of a connection of the signal path | route of the shared memory device which concerns on this embodiment. It is a figure which shows the example of mounting of a data transfer mechanism, Comprising: It is the figure which showed the example of mounting which united the function for the multiplexer for partial sharing of a memory, and the multiplexer for shift redundancy in one multiplexer MUX. It is a flowchart of access arbitration to MEM (memory bank) (2n) in PE (n) and PE (n + 1). It is a figure for demonstrating the hierarchical unit expansion method of the partial shared multiport mechanism PE.

Explanation of symbols

  10, 10A, 10B ... shared memory device, 11 ... DMA controller, 12-0 to 12-15 ... PE core (processing device), 13 ... partially overlapping multi-port and shift redundant circuit, 14-0 to 14-63 ... memory bank (memory module), 15 ... arbitration circuit, 20 ... AXI bus, M0-M15, ... memory system.

Claims (10)

A plurality of processing devices;
A plurality of memory modules accessible by the processing unit;
Among the plurality of processing devices, only a specific processing device has a connection part connectable to a specific memory module,
The plurality of processing devices can access a memory system formed by one or a plurality of memory modules via the connection unit,
The memory system accessible by different processing devices partially shares memory modules accessed by different processing devices,
A shared memory device having a redundancy function capable of redundancy with respect to the plurality of processing devices. The shared memory device according to claim 1, wherein the redundancy function is a shift redundancy function. The shared memory device according to claim 1, wherein the shared memory module is configured such that processing devices close to each other are accessible to each other. The shared memory device according to claim 1, further comprising: an arbitration circuit that executes prioritization processing when a plurality of processing devices simultaneously request access to the same memory module, and performs access control according to the priorities. A controller capable of communicating with the outside and controlling access to the plurality of memory modules;
The shared memory device according to claim 1, wherein the controller is capable of accessing all memory modules via the connection unit. A plurality of processing devices;
Multiple memory modules;
Of the plurality of processing devices, only a specific processing device can be connected to a specific memory module, and
A controller capable of communicating with the outside and controlling access to the plurality of memory modules;
The plurality of processing devices can access a memory system formed by one or a plurality of memory modules via the connection unit,
The memory system accessible by different processing devices partially shares memory modules accessed by different processing devices,
A plurality of shared memory devices including a redundancy function capable of redundancy with respect to the plurality of processing devices;
A shared memory device in which controllers of each shared memory device are connected by a bus. The shared memory device according to claim 6, wherein the redundancy function is a shift redundancy function. The shared memory device according to claim 6, wherein the memory system is formed such that the shared memory modules can be accessed by processing devices located close to each other. The shared memory device according to claim 6, further comprising: an arbitration circuit that executes prioritization processing when a plurality of processing devices simultaneously request access to the same memory module, and performs access control according to the priority. The shared memory device according to claim 6, wherein the controller can access all the memory modules via the connection unit.

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