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JP2008078573A - Built-in multi-layer printed wiring board - Google Patents

Built-in multi-layer printed wiring board Download PDF

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JP2008078573A
JP2008078573A JP2006259074A JP2006259074A JP2008078573A JP 2008078573 A JP2008078573 A JP 2008078573A JP 2006259074 A JP2006259074 A JP 2006259074A JP 2006259074 A JP2006259074 A JP 2006259074A JP 2008078573 A JP2008078573 A JP 2008078573A
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substrate
electronic component
printed wiring
wiring board
component
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Koichi Takahashi
浩一 高橋
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Nippon CMK Corp
CMK Corp
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Nippon CMK Corp
CMK Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-layer printed wiring board having built-in parts which prevents warpage of substrate, has high wiring density, and can provide reduction in thickness. <P>SOLUTION: The multi-layer printed wiring board, having built-in part includes an electronic component embedded in an insulating layer which is provided in between a first insulating substrate and a second insulating substrate, wherein the electronic component is mounted on a component-mounting pad which is formed on either one of the first insulating substrate or the second insulating substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は多層プリント配線板、特に内層に電子部品を埋め込んだ部品内蔵型多層プリント配線板に関する。   The present invention relates to a multilayer printed wiring board, and more particularly to a component built-in type multilayer printed wiring board in which an electronic component is embedded in an inner layer.

近年、多層プリント配線板の小型化、高密度化が求められる中で、従来表面実装されていた電子部品をプリント配線板内に内蔵することによって得られる部品内蔵型プリント配線板に関する要求が高まっている。   In recent years, with the demand for miniaturization and higher density of multilayer printed wiring boards, there has been an increasing demand for printed wiring boards with built-in components that can be obtained by incorporating electronic components that were conventionally surface-mounted into printed wiring boards. Yes.

そこで、図11に示すような、電子部品24を実装した基板に、予め電子部品と同寸の開口部を設けた片面銅箔基板23に積層した電子部品実装基板25を、電子部品背面を片面銅箔と共に片面銅箔基板23の絶縁材料が露出するまで研磨し、別の内層配線基板21を中心として絶縁層22を介して前記研磨後の基板を上下に各1枚ずつ配置し積層することで、実装面積を積層方向に立体的に増加できるようにすると共に、高密度実装できるようにした構成の電子部品内蔵型多層プリント配線板P26が提案されている(例えば、特許文献1参照)。   Therefore, as shown in FIG. 11, an electronic component mounting board 25 laminated on a single-sided copper foil substrate 23 provided with an opening of the same size as the electronic component in advance is mounted on the board on which the electronic component 24 is mounted. Polishing until the insulating material of the single-sided copper foil substrate 23 is exposed together with the copper foil, and placing and laminating the polished substrates one above the other through the insulating layer 22 around the other inner wiring substrate 21 Thus, there has been proposed an electronic component built-in type multilayer printed wiring board P26 having a configuration in which the mounting area can be increased three-dimensionally in the stacking direction and high-density mounting is possible (see, for example, Patent Document 1).

しかしながら、電子部品を内蔵した2枚の基板を電子部品が内側に来るように向かい合うように配置することに加えて、基板の中心層となるコア基板と、前記コア基板と前記電子部品を内蔵した基板を接合するための樹脂層が必要なため、基板全体の厚みが増してしまうという問題があった。   However, in addition to arranging the two substrates containing the electronic components so that the electronic components face each other, the core substrate serving as the central layer of the substrate, the core substrate, and the electronic components are incorporated. Since a resin layer for joining the substrates is necessary, there is a problem that the thickness of the entire substrate increases.

そこで、図12に示すような、回路形成された配線パターンと実装された電子部品34を備える一対の基板の間に、前記一対の基板の層間を導電性樹脂で接続するように予めインナービア32が形成された絶縁層31を配置し積層する構成とすることで、薄型化を図る部品内蔵型プリント配線板P27が提案されている(例えば、特許文献2参照)。   Therefore, as shown in FIG. 12, the inner via 32 is previously connected between a pair of substrates including a circuit-formed wiring pattern and a mounted electronic component 34 with a conductive resin between the pair of substrates. A component-embedded printed wiring board P27 is proposed that has a structure in which the insulating layer 31 formed with the structure is arranged and laminated (see, for example, Patent Document 2).

しかしながら、前記4層IVH構造では、電子部品の実装面を組み合わせるため、上下電子部品の間隔を一定間隔以上あけなければならず、基板全体の厚みを電子部品を実装した基板の2倍以下にはできないという問題があった。   However, in the four-layer IVH structure, since the mounting surfaces of the electronic components are combined, the upper and lower electronic components must be spaced apart by a certain distance or more, and the total thickness of the substrate is less than twice that of the substrate on which the electronic components are mounted. There was a problem that I could not.

そこで、図13に示すような、複数の配線層を有する内層基板の最上層に電子部品44を実装し、接続ランド、配線層、表面を粗化処理した内層基板45を作製し、内層基板の一方の面に開口部を有する熱硬化性樹脂シート及び銅箔を、内層基板の他方の面に所定厚の絶縁層41及び銅箔42をそれぞれ積層し、加熱、加圧して、電子部品内蔵コア多層銅張積層板を作製し、ブラインドビアホール43及び配線層を作成し、さらに、ビルドアップ法にて、絶縁樹脂層、ビアホール、配線層を形成することで、実装面積を小さく、部品内蔵層厚を薄くできる構成の電子部品内蔵型多層プリント配線板P28が提案されている(例えば、特許文献3参照)。   Therefore, as shown in FIG. 13, an electronic component 44 is mounted on the uppermost layer of an inner layer substrate having a plurality of wiring layers, and a connection land, a wiring layer, and an inner layer substrate 45 whose surface has been roughened are produced. A thermosetting resin sheet having an opening on one surface and a copper foil, and an insulating layer 41 and a copper foil 42 having a predetermined thickness are laminated on the other surface of the inner substrate, respectively, and heated and pressed to provide an electronic component built-in core. A multilayer copper clad laminate is manufactured, blind via holes 43 and wiring layers are formed, and further, an insulating resin layer, via holes, and wiring layers are formed by a build-up method, thereby reducing the mounting area and the thickness of the component built-in layer There is proposed a multilayer printed wiring board P28 with a built-in electronic component that can reduce the thickness (for example, see Patent Document 3).

しかしながら、コア基板を中心に上下ビルドアップ基材を積層しているが、チップ部品を実装した側のみビルドアップ基材の厚みが厚くなるため、コア基板を中心として非対称となり、部品内蔵基板が反り易いという問題があった。
特開2001−119148号公報 特開2004−274035号公報 特開2004−311736号公報
However, although the upper and lower buildup base materials are stacked around the core substrate, the thickness of the buildup base material increases only on the side where the chip components are mounted. There was a problem that it was easy.
JP 2001-119148 A JP 2004-274035 A JP 2004-311736 A

本発明は、上記の問題と実状に鑑みてなされたもので、基板の反り発生を防ぎ、配線密度が高く、薄型化が可能な部品内蔵型多層プリント配線板を提供することを課題とする。   The present invention has been made in view of the above problems and actual circumstances, and an object of the present invention is to provide a component-embedded multilayer printed wiring board that prevents warping of the substrate, has a high wiring density, and can be thinned.

即ち、請求項1に係る本発明は、第一及び第二の絶縁基板の間に設けられた絶縁層に電子部品が埋め込まれているプリント配線板であって、前記電子部品が前記第一及び第二の絶縁基板の何れか一方に形成された部品実装パッドに実装されていることを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   That is, the present invention according to claim 1 is a printed wiring board in which an electronic component is embedded in an insulating layer provided between the first and second insulating substrates, and the electronic component is the first and second The above problems are solved by a component built-in type multilayer printed wiring board which is mounted on a component mounting pad formed on any one of the second insulating substrates.

これにより、内層に電子部品を内蔵しても基板の薄型化がなされ、且つ電子部品の上下に絶縁基板がある上下対称構造となり基板の反りが抑制される。   Thereby, even if an electronic component is built in the inner layer, the substrate is thinned, and a vertical symmetrical structure in which an insulating substrate is provided above and below the electronic component is formed, and warping of the substrate is suppressed.

また、請求項2に係る本発明は、前記第一及び第二の絶縁基板が同質の材料から成ることを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   According to a second aspect of the present invention, the above-mentioned problems are solved by a component-embedded multilayer printed wiring board in which the first and second insulating substrates are made of the same material.

これにより、基板構造の上下対称性が高まり、基板の反りがより抑制される。   Thereby, the vertical symmetry of the substrate structure is increased, and the warpage of the substrate is further suppressed.

また、請求項3に係る本発明は、前記第一及び第二の絶縁基板の厚みが略同じであることを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   According to a third aspect of the present invention, the above-described problems are solved by a component-embedded multilayer printed wiring board in which the thicknesses of the first and second insulating substrates are substantially the same.

これにより、基板構造の上下対称性が高まり、基板の反りがより抑制される。   Thereby, the vertical symmetry of the substrate structure is increased, and the warpage of the substrate is further suppressed.

また、請求項4に係る本発明は、前記第一及び第二の絶縁基板の表裏に配線層が設けられていることを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   According to a fourth aspect of the present invention, there is provided a component built-in type multilayer printed wiring board, wherein wiring layers are provided on the front and back surfaces of the first and second insulating substrates. is there.

これにより、基板構造の上下対称性が高まり、基板の反りがより抑制されると共に、内蔵した電子部品実装面と向かい合う面にも配線パターンを設けることで、高密度配線が可能となる。   As a result, the vertical symmetry of the substrate structure is enhanced, the warpage of the substrate is further suppressed, and the wiring pattern is provided on the surface facing the built-in electronic component mounting surface, thereby enabling high-density wiring.

また、請求項5に係る本発明は、前記第一及び第二の絶縁基板の間に設けられた絶縁層側の配線層及び部品実装パッドの少なくとも一部に保護膜が設けられていることを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   According to a fifth aspect of the present invention, a protective film is provided on at least a part of the wiring layer on the insulating layer side and the component mounting pad provided between the first and second insulating substrates. The above-described problems are solved by a component-embedded multilayer printed wiring board.

これにより、内蔵する電子部品の実装時のはんだ飛び散りによる部品実装パッド周辺のリークやショートを回避できると共に、基板構造の上下対称性が高まり、基板の反りがより抑制される。   As a result, it is possible to avoid leakage and short circuit around the component mounting pad due to solder scattering during mounting of the built-in electronic component, and to increase the vertical symmetry of the substrate structure, thereby further suppressing the warpage of the substrate.

また、請求項6に係る本発明は、前記埋め込まれている電子部品と対向する絶縁基板側には、配線層及び保護膜が形成されていないことを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   According to a sixth aspect of the present invention, there is provided a component built-in multilayer printed wiring board in which a wiring layer and a protective film are not formed on the insulating substrate side facing the embedded electronic component. It solves the above problems.

これにより、基板の薄型化が図られると共に、電子部品自体及び実装時に発生する高さばらつきを吸収し、電子部品と上部絶縁基板との接触による電子部品の破壊を回避することができる。   As a result, the thickness of the substrate can be reduced, the electronic component itself and the height variation generated during mounting can be absorbed, and the destruction of the electronic component due to the contact between the electronic component and the upper insulating substrate can be avoided.

また、請求項7に係る本発明は、前記埋め込まれている電子部品と対向する絶縁基板部位が開口されていると共に、当該開口部位に前記絶縁層が充填されていることを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   According to a seventh aspect of the present invention, there is provided a built-in component characterized in that an insulating substrate portion facing the embedded electronic component is opened, and the opening layer is filled with the insulating layer. The above-mentioned problem is solved by a mold multilayer printed wiring board.

これにより、前項の電子部品実装部における導体と保護膜の削除による薄型化に加えて、更に電子部品実装部上部のコア材の厚さ分だけ基板の薄型化することとなり、部品内蔵基板全体の大幅な薄型化に寄与できる。   As a result, in addition to the reduction in thickness by removing the conductor and protective film in the electronic component mounting part in the previous section, the thickness of the substrate is further reduced by the thickness of the core material above the electronic component mounting part. Contributes to a significant reduction in thickness.

また、請求項8に係る本発明は、前記埋め込まれている電子部品の電極の一部又は全部が、上層の導体と層間接続ビアによって接続されていることを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   The invention according to claim 8 is characterized in that a part or all of the electrodes of the embedded electronic component are connected to the upper layer conductor by an interlayer connection via, and the component-embedded multilayer printed wiring The above problem is solved by a plate.

これにより、内蔵された電子部品実装面上部の絶縁基板において、当該電子部品実装面と向き合わない上層面から内蔵された電子部品への直接接続が可能となり、配線長の最適化が図られ、高速伝送を用いる基板等で伝送ロスや遅延の低減がなされる。また、前記直接接続により、従来必要であった迂回配線が必要なくなるため、設計の自由度が飛躍的に向上する。   As a result, it is possible to directly connect the built-in electronic component mounting surface to the built-in electronic component from the upper surface that does not face the electronic component mounting surface. Transmission loss and delay are reduced by a substrate or the like that uses transmission. In addition, the direct connection eliminates the need for bypass wiring, which has been necessary in the past, and thus the degree of freedom in design is greatly improved.

また、請求項9に係る本発明は、前記埋め込まれている電子部品の少なくとも1つの電極が第一の絶縁基板上の導体と接続され、当該第一の絶縁基板と接続された電極以外の少なくとも1つの電極が第二の絶縁基板上の導体と接続されていることを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   According to a ninth aspect of the present invention, at least one electrode of the embedded electronic component is connected to a conductor on the first insulating substrate, and at least other than the electrode connected to the first insulating substrate. One of the electrodes is connected to a conductor on a second insulating substrate, which solves the above problem by a component built-in type multilayer printed wiring board.

これにより、従来必要であった部品実装パッドや配線パターン、層間接続ビア等の一部が不要となり、配線領域の拡大と設計自由度の向上が図られる。   As a result, parts such as component mounting pads, wiring patterns, interlayer connection vias, and the like, which have been conventionally required, are not required, and the wiring area can be expanded and the degree of design freedom can be improved.

また、請求項10に係る本発明は、前記埋め込まれている電子部品が、はんだ接続されていないことを特徴とする部品内蔵型多層プリント配線板により上記課題を解決したものである。   According to a tenth aspect of the present invention, the above-described problem is solved by a component-embedded multilayer printed wiring board, wherein the embedded electronic component is not soldered.

これにより、内層のはんだレス化が可能となり、接続信頼性の低下を防止すると共に、基板全体の重量軽減化にも寄与できる。   As a result, the inner layer can be made solder-free, preventing a decrease in connection reliability and contributing to a reduction in the weight of the entire board.

本発明により、基板の反り発生を防ぎ、配線密度が高く、薄型化が可能な部品内蔵型多層プリント配線板を提供することができる。   According to the present invention, it is possible to provide a component built-in type multilayer printed wiring board that prevents warping of a substrate, has a high wiring density, and can be thinned.

本発明の第一の実施の形態を図1を用いて説明する。   A first embodiment of the present invention will be described with reference to FIG.

図1において、P1は部品内蔵型多層プリント配線板で、上面に部品実装パッド102と配線回路を設けた第一の絶縁基板101の当該部品実装パッド102に電子部品104がはんだ105を用いて実装されていると共に、前記第一の絶縁基板101の電子部品実装面に絶縁層106と第二の絶縁基板103が設けられ、前記第二の絶縁基板103は、前記電子部品104と対向しない絶縁層106側の面に導体層112と保護膜113を備えていると共に、前記電子部品104と対向する絶縁層106側の面に導体層112と保護膜113が形成されていない。   In FIG. 1, P1 is a component built-in type multilayer printed wiring board, and an electronic component 104 is mounted on the component mounting pad 102 of the first insulating substrate 101 provided with a component mounting pad 102 and a wiring circuit on the upper surface using solder 105. In addition, an insulating layer 106 and a second insulating substrate 103 are provided on the electronic component mounting surface of the first insulating substrate 101, and the second insulating substrate 103 is an insulating layer that does not face the electronic component 104. The conductive layer 112 and the protective film 113 are provided on the surface on the 106 side, and the conductive layer 112 and the protective film 113 are not formed on the surface on the insulating layer 106 facing the electronic component 104.

ここで、図1では電子部品104の一例としてチップ抵抗器を用いて説明しているが、本発明において電子部品とはチップ抵抗器に限定されるものではなく、コンデンサ、インダクタ、ダイオード、トランジスタ、IC、LSI等、受動能動を問わず、電子部品全般を示す。尚、当然のことながら、部品実装パッド102は、当該実装する電子部品に対応したパッド数、パッドサイズ、パッドピッチの部品実装パッドを用いる。   Here, in FIG. 1, a chip resistor is used as an example of the electronic component 104. However, in the present invention, the electronic component is not limited to the chip resistor, and includes a capacitor, an inductor, a diode, a transistor, All electronic components such as IC and LSI, whether passive or active, are shown. As a matter of course, the component mounting pad 102 uses a component mounting pad having the number of pads, a pad size, and a pad pitch corresponding to the electronic component to be mounted.

また、図1では電子部品104を部品実装パッド102に接合するための手段の一例として「はんだ105」を用いて説明しているが、本発明において電子部品を部品実装パッドに接合するための手段とは「はんだ」に限定されるものではなく、導電性接着剤、導電性フィルム、異方導電性接着剤、異方導電性フィルム等、その材質及び形状を問わず、実装する電子部品を部品実装パッドに固着させ、且つ導電性接合をもたらす手段全般を示す。   In FIG. 1, “solder 105” is used as an example of means for joining the electronic component 104 to the component mounting pad 102, but means for joining the electronic component to the component mounting pad in the present invention. Is not limited to "solder", but includes electronic components to be mounted regardless of the material and shape, such as conductive adhesive, conductive film, anisotropic conductive adhesive, anisotropic conductive film, etc. A general means for securing to a mounting pad and providing a conductive bond is shown.

前記部品内蔵型多層プリント配線板P1は、前記第二の絶縁基板103が前記電子部品104と対向しない絶縁層106側の面に導体層112と保護膜113を備えているため、基板構造が上下対称となり、基板の反りが防止される。   The component-embedded multilayer printed wiring board P1 includes the conductor layer 112 and the protective film 113 on the surface on the insulating layer 106 side where the second insulating substrate 103 does not face the electronic component 104, so that the substrate structure is vertically Symmetrical and warping of the substrate is prevented.

また、導体層112に配線パターンを設けることで、高密度配線が可能となる。   Further, by providing a wiring pattern on the conductor layer 112, high-density wiring is possible.

更に、前記電子部品104と対向する第二絶縁基板103の絶縁層106側の面には、導体層112と保護膜113が形成されることなく前記電子部品104と同寸以上に開けられているため、基板の薄型化が図られると共に、電子部品自体及び実装時に発生する高さばらつきを吸収し、電子部品と上部絶縁基板との接触による電子部品の破壊を回避することができる。   Further, the conductive layer 112 and the protective film 113 are not formed on the surface of the second insulating substrate 103 facing the electronic component 104 on the insulating layer 106 side, and the electronic component 104 is opened to the same size or more. Therefore, the thickness of the substrate can be reduced, and the electronic component itself and the height variation generated during mounting can be absorbed, and the destruction of the electronic component due to the contact between the electronic component and the upper insulating substrate can be avoided.

従って、本発明の第一の実施の形態により、基板の反りが防止され、高密度配線が可能で、薄型化されても電子部品と上部絶縁基板との接触による電子部品の破壊を回避することができる部品内蔵型多層プリント配線板が得られる。   Therefore, according to the first embodiment of the present invention, warpage of the substrate is prevented, high-density wiring is possible, and even when the thickness is reduced, destruction of the electronic component due to contact between the electronic component and the upper insulating substrate is avoided. A multilayer printed wiring board with built-in components that can be obtained is obtained.

次に、本発明の第二の実施の形態を図2を用いて説明する。   Next, a second embodiment of the present invention will be described with reference to FIG.

図2(a)において、P2は部品内蔵型多層プリント配線板で、上面に部品実装パッド202と配線回路を設けた第一の絶縁基板201の当該部品実装パッド202に電子部品214がはんだ215を用いて実装されていると共に、前記第一の絶縁基板201の電子部品実装面に絶縁層216と第二の絶縁基板203が設けられ、前記第二の絶縁基板203は、前記電子部品214と対向しない絶縁層216側の面に導体層212と保護膜213を備えていると共に、前記電子部品214と対向する部位が前記電子部品214と同寸以上に開口され、当該開口部位に絶縁層216が積層時にフローした絶縁樹脂が充填されている。   In FIG. 2A, P2 is a component built-in type multilayer printed wiring board, and the electronic component 214 solders 215 to the component mounting pad 202 of the first insulating substrate 201 provided with the component mounting pad 202 and the wiring circuit on the upper surface. And an insulating layer 216 and a second insulating substrate 203 are provided on the electronic component mounting surface of the first insulating substrate 201, and the second insulating substrate 203 is opposed to the electronic component 214. The insulating layer 216 is provided with a conductor layer 212 and a protective film 213 on the surface thereof, and a portion facing the electronic component 214 is opened to the same size or more as the electronic component 214, and the insulating layer 216 is formed in the opening portion. The insulating resin that has flowed during lamination is filled.

更に、前記第二の絶縁基板203の開口された領域内の前記電子部品214の電極218と、前記第二の絶縁基板203の絶縁層216とは反対側の面に形成された導体217が層間接続ビア204によって接続されていると共に、前記層間接続ビア204によって接続された電極下218の下部には部品実装パッド202が形成されていない。   Furthermore, the electrode 218 of the electronic component 214 in the opened region of the second insulating substrate 203 and the conductor 217 formed on the surface opposite to the insulating layer 216 of the second insulating substrate 203 are provided between the layers. The component mounting pads 202 are not formed below the lower electrode 218 connected by the connection via 204 and connected by the interlayer connection via 204.

ここで、図2(a)では電子部品214の一例としてチップ抵抗器を用いて説明しているが、本発明において電子部品とはチップ抵抗器に限定されるものではなく、コンデンサ、インダクタ、ダイオード、トランジスタ、IC、LSI等、受動能動を問わず、電子部品全般を示す。尚、当然のことながら、部品実装パッド202は、当該実装する電子部品に対応したパッド数、パッドサイズ、パッドピッチの部品実装パッドを用いる。   Here, in FIG. 2A, a chip resistor is used as an example of the electronic component 214. However, in the present invention, the electronic component is not limited to the chip resistor, but includes a capacitor, an inductor, and a diode. Electronic devices such as transistors, ICs, LSIs, etc. As a matter of course, the component mounting pad 202 is a component mounting pad having the number of pads, the pad size, and the pad pitch corresponding to the electronic component to be mounted.

また、図2(a)では電子部品214を部品実装パッド202に接合するための手段の一例として「はんだ215」を用いて説明しているが、本発明において電子部品を部品実装パッドに接合するための手段とは「はんだ」に限定されるものではなく、導電性接着剤、導電性フィルム、異方導電性接着剤、異方導電性フィルム等、その材質及び形状を問わず、実装する電子部品を部品実装パッドに固着させ、且つ導電性接合をもたらす手段全般を示す。   In FIG. 2A, “solder 215” is used as an example of means for joining the electronic component 214 to the component mounting pad 202. In the present invention, the electronic component is joined to the component mounting pad. The means for this is not limited to "solder", but the electronic to be mounted regardless of its material and shape, such as conductive adhesive, conductive film, anisotropic conductive adhesive, anisotropic conductive film, etc. A general means for securing a component to a component mounting pad and providing a conductive bond is shown.

前記部品内蔵型多層プリント配線板P2は、前記第二の絶縁基板203の前記電子部品214と対向する部位が前記電子部品214と同寸以上に開口されているため、電子部品実装部における導体と保護膜の削除による薄型化に加えて、更に電子部品実装部上部のコア材の厚さ分だけ基板を薄型化することができ、部品内蔵基板全体の大幅な薄型化が可能となっている。   The component-embedded multilayer printed wiring board P2 has a portion facing the electronic component 214 of the second insulating substrate 203 opened to have the same size or more as the electronic component 214. In addition to thinning by removing the protective film, the substrate can be further thinned by the thickness of the core material above the electronic component mounting portion, and the entire component-embedded substrate can be significantly thinned.

また、前記基板203の開口された領域内の電子部品214の電極218と、前記第二の絶縁基板203の絶縁層216とは反対側の面に形成された導体217が層間接続ビア204によって接続されているため、電子部品実装面と向き合わない上層面から内蔵された電子部品への直接接続が可能となり、配線長の最適化が図られ、高速伝送を用いる基板等で伝送ロスや遅延の低減がなされると共に、従来必要であった迂回配線が必要なくなるため、設計の自由度が飛躍的に向上する。   Further, the electrode 218 of the electronic component 214 in the opened region of the substrate 203 and the conductor 217 formed on the surface opposite to the insulating layer 216 of the second insulating substrate 203 are connected by the interlayer connection via 204. Therefore, it is possible to connect directly to the built-in electronic component from the upper surface that does not face the electronic component mounting surface, the wiring length is optimized, and transmission loss and delay are reduced with a board etc. that uses high-speed transmission In addition, since the detour wiring, which has been necessary in the past, is no longer necessary, the degree of freedom in design is greatly improved.

更にまた、部分的にはんだレス接続が可能となり、接続信頼性の低下を防止低下の要因を少なくすると共に、基板全体の重量軽減化にも寄与できる上、前記層間接続ビア204によって接続された電極218の下部には部品実装パッドが不要となり、従来部品実装パッドとして使用していた領域が配線領域として使用することが可能となり、配線領域の拡大と設計自由度の向上が図られる。   Furthermore, the solderless connection can be partially made, the deterioration of the connection reliability can be prevented, the cause of the decrease can be reduced, the weight of the entire substrate can be reduced, and the electrodes connected by the interlayer connection via 204 are also connected. A component mounting pad is not required at the lower part of 218, so that a region used as a conventional component mounting pad can be used as a wiring region, so that the wiring region can be expanded and the degree of design freedom can be improved.

また、前記層間接続ビア204によって接続された電極下には部品実装パッドが不要となり、従来部品実装パッドとして使用していた領域が配線領域として使用することが可能となり、配線領域の拡大と設計自由度の向上が図られる。また、前記電極218と前記導体217が前記層間接続ビア204によって接続されていると共に、前記電子部品214のもう一方の電極219と前記部品実装パッド202が前記はんだ215によって接続されているため、前記第一の絶縁基板201上の導体202と前記第二の絶縁基板203上の導体217を前記電子部品214を介して接続する際に従来必要であった配線パターンや層間接続ビアの一部が不要となり、配線領域の拡大と設計自由度の向上が図られる。   In addition, no component mounting pad is required under the electrodes connected by the interlayer connection via 204, so that a region used as a conventional component mounting pad can be used as a wiring region. The degree is improved. The electrode 218 and the conductor 217 are connected by the interlayer connection via 204, and the other electrode 219 of the electronic component 214 and the component mounting pad 202 are connected by the solder 215. There is no need for a wiring pattern or a part of an interlayer connection via that is conventionally required when connecting the conductor 202 on the first insulating substrate 201 and the conductor 217 on the second insulating substrate 203 via the electronic component 214. Thus, the wiring area can be expanded and the design flexibility can be improved.

また、図2(b)に示すように、内蔵された電子部品314の電極318全てを層間接続ビア304を用いて接続することで内層はんだレス構造にすることが可能となる。その際、当該電子部品314を配置する直下が保護膜313で覆われていれば、当該保護膜313の下に配線パターンなどの導体層312が設けられていても構わない。また、当該電子部品314を配置する直下に、配置された当該電子部品314を積層前に仮に固定するための接着シートや接着剤を設けても良い。   Further, as shown in FIG. 2B, by connecting all the electrodes 318 of the built-in electronic component 314 using the interlayer connection via 304, an inner layer solderless structure can be obtained. At that time, a conductor layer 312 such as a wiring pattern may be provided under the protective film 313 as long as the protective film 313 covers the portion immediately below the electronic component 314. Further, an adhesive sheet or an adhesive for temporarily fixing the electronic component 314 arranged before the stacking may be provided immediately below the electronic component 314.

従って、本発明の第二の実施の形態により、基板全体の大幅な薄型化がなされ、設計の自由度が飛躍的に向上した部品内蔵型多層プリント配線板が得られる。   Therefore, according to the second embodiment of the present invention, it is possible to obtain a component-embedded multilayer printed wiring board in which the entire board is significantly reduced in thickness and the degree of freedom of design is greatly improved.

次に、本発明の第一の実施の形態の製造方法を図3〜図6を用いて説明する。   Next, the manufacturing method of 1st embodiment of this invention is demonstrated using FIGS.

まず、図3(a)に示すように、絶縁層1の上下両面に導体層2を備えた基板P4を用意する。尚、前記基板P4は、多層基板でも構わない。   First, as shown in FIG. 3A, a substrate P4 having conductor layers 2 on both upper and lower surfaces of the insulating layer 1 is prepared. The substrate P4 may be a multilayer substrate.

次に、前記基板P4の上面の導体層を回路形成し、図3(b)に示すような基板P5を得る。   Next, a circuit is formed on the conductor layer on the upper surface of the substrate P4 to obtain a substrate P5 as shown in FIG.

次に、図3(c)に示すように、保護膜3を形成し、基板P6を得る。   Next, as shown in FIG. 3C, the protective film 3 is formed to obtain the substrate P6.

次に、図4(d)に示すように、電子部品4をはんだ5を用いて実装し、基板P7を得る。   Next, as shown in FIG. 4D, the electronic component 4 is mounted using solder 5 to obtain a substrate P7.

次に、図3(a)から図3(c)までの工程と同様にして基板P8を作製し、図4(e)に示すように、基板P7に積層する際に電子部品4と重なる部位にルータ等を用いて予め穴あけ加工を施した絶縁層6を挟んで、基板P7と基板P8を積層し、図4(f)に示すような、基板P9を得る。   Next, the substrate P8 is manufactured in the same manner as in the steps from FIG. 3A to FIG. 3C, and as shown in FIG. 4E, the portion overlapping the electronic component 4 when being stacked on the substrate P7. Then, the substrate P7 and the substrate P8 are stacked with the insulating layer 6 previously drilled using a router or the like interposed therebetween, and a substrate P9 as shown in FIG. 4F is obtained.

次に、図5(g)に示すように、前記基板P9の外層に層間接続ビアを設け、基板P10を得る。   Next, as shown in FIG. 5G, an interlayer connection via is provided in the outer layer of the substrate P9 to obtain a substrate P10.

次に、図5(h)に示すように、前記基板P10に貫通穴を設け、基板P11を得る。   Next, as shown in FIG. 5H, a through hole is provided in the substrate P10 to obtain a substrate P11.

次に、図5(k)に示すように、前記基板P11にめっき層7を設け、基板P12を得る。   Next, as shown in FIG. 5 (k), a plating layer 7 is provided on the substrate P11 to obtain a substrate P12.

次に、図6(m)に示すように、前記基板P12の外層に回路形成を施し、基板P13を得る。   Next, as shown in FIG. 6M, circuit formation is performed on the outer layer of the substrate P12 to obtain a substrate P13.

次に、保護膜8の形成工程を経て、図6(n)に示すような部品内蔵型多層プリント配線板P14を得る。   Next, the component built-in type multilayer printed wiring board P14 as shown in FIG.

尚、図6(m)に示す基板P13の外層表面に、図6(n)に示すような保護膜8ではなく、絶縁層と導体層を構築し更なるビルドアップを行い、基板P13の形態をコア基板として、基板の構成層数を増しても構わない。   In addition, an insulating layer and a conductor layer are constructed on the outer layer surface of the substrate P13 shown in FIG. 6M instead of the protective film 8 shown in FIG. As a core substrate, the number of constituent layers of the substrate may be increased.

次に、本発明の第二の実施の形態の製造方法を図7〜図10を用いて説明する。   Next, the manufacturing method of 2nd embodiment of this invention is demonstrated using FIGS.

まず、図7(a)に示すように、絶縁層11の上下両面に導体層12を備えた基板P15を用意する。尚、前記基板P15は、多層基板でも構わない。   First, as shown in FIG. 7A, a substrate P15 having conductor layers 12 on both upper and lower surfaces of the insulating layer 11 is prepared. The substrate P15 may be a multilayer substrate.

次に、前記基板P15の上面の導体層を回路形成し、図7(b)に示すような基板P16を得る。   Next, a circuit is formed on the conductor layer on the upper surface of the substrate P15 to obtain a substrate P16 as shown in FIG.

次に、図7(c)に示すように、保護膜13を形成し、基板P17を得る。   Next, as shown in FIG. 7C, a protective film 13 is formed to obtain a substrate P17.

次に、図8(d)に示すように、電子部品14をはんだ15を用いて実装し、基板P18を得る。   Next, as shown in FIG. 8D, the electronic component 14 is mounted using solder 15 to obtain a substrate P18.

次に、図8(a)から図8(c)までの工程と同様にして作製した基板に電子部品14と重なる部位にルータ等を用いて予め穴あけ加工を施した基板P19を用いて、図8(e)に示すように、基板P18に積層する際に電子部品14と重なる部位にルータ等を用いて予め穴あけ加工を施した絶縁層16を挟んで、基板P18と基板P19を積層し、図8(f)に示すような、基板P20を得る。   Next, using the substrate P19 in which the substrate manufactured in the same manner as in the steps from FIG. 8A to FIG. 8 (e), the substrate P18 and the substrate P19 are stacked with the insulating layer 16 previously punched using a router or the like in a portion overlapping the electronic component 14 when stacked on the substrate P18, A substrate P20 as shown in FIG.

次に、図9(g)に示すように、前記基板P20の上面を表面研磨し、表面が平滑となるようにし、基板P21を得る。   Next, as shown in FIG. 9G, the upper surface of the substrate P20 is subjected to surface polishing so that the surface becomes smooth, thereby obtaining a substrate P21.

次に、図9(h)に示すように、前記基板P21に貫通穴と層間接続ビアを設け、基板P22を得る。   Next, as shown in FIG. 9H, through holes and interlayer connection vias are provided in the substrate P21 to obtain a substrate P22.

次に、図9(k)に示すように、前記基板P22にめっき層17を設け、基板P23を得る。   Next, as shown in FIG. 9 (k), a plating layer 17 is provided on the substrate P22 to obtain a substrate P23.

次に、図10(m)に示すように、前記基板P23の外層に回路形成を施し、基板P24を得る。   Next, as shown in FIG. 10 (m), circuit formation is performed on the outer layer of the substrate P23 to obtain a substrate P24.

次に、保護膜18の形成工程を経て、図10(n)に示すような部品内蔵型多層プリント配線板P25を得る。   Next, a component built-in type multilayer printed wiring board P25 as shown in FIG.

尚、図10(m)に示す基板P24の外層表面に、図10(n)に示すような保護膜18ではなく、絶縁層と導体層を構築し更なるビルドアップを行い、基板P24の形態をコア基板として、基板の構成層数を増しても構わない。   In addition, on the outer layer surface of the substrate P24 shown in FIG. 10 (m), not the protective film 18 as shown in FIG. 10 (n) but an insulating layer and a conductor layer are constructed, and further buildup is performed. As a core substrate, the number of constituent layers of the substrate may be increased.

本発明を説明するに当たって、前述2つの実施の形態及び各々の製造方法を例として説明したが、本発明の構成はこれらの限りでなく、また、これらの例により何ら制限されるものではなく、本発明の範囲内で種々の変更が可能である。   In describing the present invention, the above-described two embodiments and the respective manufacturing methods have been described as examples. However, the configuration of the present invention is not limited to these, and is not limited to these examples. Various modifications are possible within the scope of the present invention.

本発明の第一の実施の形態を示す概略断面説明図。BRIEF DESCRIPTION OF THE DRAWINGS Schematic cross-sectional explanatory drawing which shows 1st embodiment of this invention. 本発明の第二の実施の形態を示す概略断面説明図。The schematic cross-section explanatory drawing which shows 2nd embodiment of this invention. 本発明の第一の実施の形態の製造方法を示す概略断面工程説明図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional process explanatory diagram illustrating a manufacturing method according to a first embodiment of the present invention. 図3に続く概略断面工程説明図。FIG. 4 is a schematic cross-sectional process explanatory diagram following FIG. 3. 図4に続く概略断面工程説明図。FIG. 5 is a schematic cross-sectional process explanatory diagram subsequent to FIG. 4. 図5に続く概略断面工程説明図。FIG. 6 is a schematic cross-sectional process explanatory diagram following FIG. 5. 本発明の第二の実施の形態の製造方法を示す概略断面工程説明図。Schematic cross-sectional process explanatory drawing which shows the manufacturing method of 2nd embodiment of this invention. 図7に続く概略断面工程説明図。FIG. 8 is a schematic cross-sectional process explanatory diagram following FIG. 7. 図8に続く概略断面工程説明図。FIG. 9 is a schematic cross-sectional process explanatory diagram following FIG. 8. 図9に続く概略断面工程説明図。FIG. 10 is a schematic cross-sectional process explanatory diagram following FIG. 9. 第一の従来例を示す概略断面説明図。FIG. 3 is a schematic cross-sectional explanatory view showing a first conventional example. 第二の従来例を示す概略断面説明図。The schematic cross-section explanatory drawing which shows a 2nd prior art example. 第三の従来例を示す概略断面説明図。Schematic cross-sectional explanatory drawing which shows a 3rd prior art example.

符号の説明Explanation of symbols

1,6,11,16,22,31,41,106,216:絶縁層
2,12,112,212,312:導体層
3,8,13,18,113,213,313:保護膜
4,14,24,34,44,104,214,314:電子部品
5,15,105,215:はんだ
7,17:めっき層
21:内層配線基板
23:片面銅箔基板
25:電子部品実装基板
32:インナービア
42:銅箔
101,201:第一の絶縁基板
102,202:部品実装パッド
103,203:第二の絶縁基板
204,304:層間接続ビア
P1〜P3,P14,P25〜P28:部品内蔵型多層プリント配線板
P4〜P13,P15〜P24:基板
1, 6, 11, 16, 22, 31, 41, 106, 216: insulating layers 2, 12, 112, 212, 312: conductor layers 3, 8, 13, 18, 113, 213, 313: protective film 4, 14, 24, 34, 44, 104, 214, 314: electronic components 5, 15, 105, 215: solder 7, 17: plating layer 21: inner layer wiring substrate 23: single-sided copper foil substrate 25: electronic component mounting substrate 32: Inner via 42: Copper foil 101, 201: First insulating substrate 102, 202: Component mounting pad 103, 203: Second insulating substrate 204, 304: Interlayer connection vias P1-P3, P14, P25-P28: Built-in components Type multilayer printed wiring boards P4 to P13, P15 to P24: substrate

Claims (10)

第一及び第二の絶縁基板の間に設けられた絶縁層に電子部品が埋め込まれているプリント配線板であって、前記電子部品が前記第一及び第二の絶縁基板の何れか一方に形成された部品実装パッドに実装されていることを特徴とする部品内蔵型多層プリント配線板。   A printed wiring board in which an electronic component is embedded in an insulating layer provided between the first and second insulating substrates, wherein the electronic component is formed on one of the first and second insulating substrates A multi-layer printed wiring board with built-in components, which is mounted on a component mounting pad. 前記第一及び第二の絶縁基板が同質の材料から成ることを特徴とする請求項1記載の部品内蔵型多層プリント配線板。   2. The component built-in multilayer printed wiring board according to claim 1, wherein the first and second insulating substrates are made of the same material. 前記第一及び第二の絶縁基板の厚みが略同じであることを特徴とする請求項1又は2記載の部品内蔵型多層プリント配線板。   3. The component built-in multilayer printed wiring board according to claim 1, wherein the first and second insulating substrates have substantially the same thickness. 前記第一及び第二の絶縁基板の表裏に配線層が設けられていることを特徴とする請求項1〜3何れか1項記載の部品内蔵型多層プリント配線板。   4. The component built-in multilayer printed wiring board according to claim 1, wherein wiring layers are provided on the front and back surfaces of the first and second insulating substrates. 前記第一及び第二の絶縁基板の間に設けられた絶縁層側の配線層及び部品実装パッドの少なくとも一部に保護膜が設けられていることを特徴とする請求項1〜4何れか1項記載の部品内蔵型多層プリント配線板。   5. The protective film is provided on at least a part of the wiring layer on the insulating layer side and the component mounting pad provided between the first and second insulating substrates. The component built-in type multilayer printed wiring board according to the item. 前記埋め込まれている電子部品と対向する絶縁基板側には、配線層及び保護膜が形成されていないことを特徴とする請求項1〜5何れか1項記載の部品内蔵型多層プリント配線板。   6. The component built-in multilayer printed wiring board according to claim 1, wherein a wiring layer and a protective film are not formed on an insulating substrate side facing the embedded electronic component. 前記埋め込まれている電子部品と対向する絶縁基板部位が開口されていると共に、当該開口部位に前記絶縁層が充填されていることを特徴とする部品内蔵型多層プリント配線板。   A component-embedded multilayer printed wiring board, wherein an insulating substrate portion facing the embedded electronic component is opened, and the opening layer is filled with the insulating layer. 前記埋め込まれている電子部品の電極の一部又は全部が、上層の導体と層間接続ビアによって接続されていることを特徴とする請求項7記載の部品内蔵型多層プリント配線板。   8. The component built-in multilayer printed wiring board according to claim 7, wherein some or all of the electrodes of the embedded electronic component are connected to the upper layer conductor by an interlayer connection via. 前記埋め込まれている電子部品の少なくとも1つの電極が第一の絶縁基板上の導体と接続され、当該第一の絶縁基板と接続された電極以外の少なくとも1つの電極が第二の絶縁基板上の導体と接続されていることを特徴とする請求項7又は8記載の部品内蔵型多層プリント配線板。   At least one electrode of the embedded electronic component is connected to a conductor on the first insulating substrate, and at least one electrode other than the electrode connected to the first insulating substrate is on the second insulating substrate. 9. The component built-in multilayer printed wiring board according to claim 7 or 8, wherein the component built-in multilayer printed wiring board is connected to a conductor. 前記埋め込まれている電子部品が、はんだ接続されていないことを特徴とする請求項7〜9何れか1項記載の部品内蔵型多層プリント配線板。   The component built-in multilayer printed wiring board according to claim 7, wherein the embedded electronic component is not solder-connected.
JP2006259074A 2006-09-25 2006-09-25 Built-in multi-layer printed wiring board Pending JP2008078573A (en)

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JP2009283689A (en) * 2008-05-22 2009-12-03 Dainippon Printing Co Ltd Method for manufacturing of component-incorporating wiring board, and component-incorporating wiring board
JP2012182269A (en) * 2011-03-01 2012-09-20 Dainippon Printing Co Ltd Component built-in wiring board
CN112203412A (en) * 2019-07-07 2021-01-08 深南电路股份有限公司 Embedded circuit boards, electronic devices
CN114501854A (en) * 2020-10-27 2022-05-13 鹏鼎控股(深圳)股份有限公司 Method for manufacturing circuit board with embedded element and circuit board with embedded element
JP2024032672A (en) * 2022-08-29 2024-03-12 ズハイ アクセス セミコンダクター シーオー.,エルティーディー Embedded flip chip package substrate and manufacturing method thereof

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283689A (en) * 2008-05-22 2009-12-03 Dainippon Printing Co Ltd Method for manufacturing of component-incorporating wiring board, and component-incorporating wiring board
JP2012182269A (en) * 2011-03-01 2012-09-20 Dainippon Printing Co Ltd Component built-in wiring board
CN112203412A (en) * 2019-07-07 2021-01-08 深南电路股份有限公司 Embedded circuit boards, electronic devices
CN114501854A (en) * 2020-10-27 2022-05-13 鹏鼎控股(深圳)股份有限公司 Method for manufacturing circuit board with embedded element and circuit board with embedded element
CN114501854B (en) * 2020-10-27 2024-03-29 鹏鼎控股(深圳)股份有限公司 Method for manufacturing circuit board with embedded element and circuit board with embedded element
JP2024032672A (en) * 2022-08-29 2024-03-12 ズハイ アクセス セミコンダクター シーオー.,エルティーディー Embedded flip chip package substrate and manufacturing method thereof
JP7573702B2 (en) 2022-08-29 2024-10-25 ズハイ アクセス セミコンダクター シーオー.,エルティーディー Embedded flip chip package substrate and manufacturing method thereof

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