JP2008089954A - Data line drive circuit, liquid crystal display, and electronic device equipped therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data line drive circuit having a built-in DAC consuming less power with a small area. <P>SOLUTION: A hold circuit is provided between a DAC circuit and an analog buffer circuit and longer time is required for writing from the analog buffer circuit to the data line than writing from the DAC circuit to the hold circuit. Furthermore, two hold circuits are used for writing from the analog buffer circuit to the data lines in line sequence. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to, for example, a data line driving circuit, a liquid crystal display device, and an electronic apparatus equipped with the same.

  In recent years, so-called System On Glass (SOG) technology for forming a thin film transistor (TFT) circuit on a glass substrate using a low-temperature polysilicon thin film forming technology has been developed, and a driver circuit is formed on the glass substrate of a liquid crystal display. Development of a display device called a monolithic driver or a liquid crystal display device with a built-in drive circuit is being advanced. In particular, a data line driving circuit (or a horizontal driving circuit or H-DRIVER or the like) including a DAC (Digital Analogue Converter) circuit (or a D / A conversion circuit or the like) is formed on a glass substrate. Therefore, it is expected that the cost of the driver IC will be very low, and it is being put into practical use. When such a data line driving circuit with a built-in DAC circuit is formed on a glass substrate, as described in Patent Document 1, a selection circuit (or shift register circuit), a first memory circuit (or a sampling latch) are sequentially provided. Circuit), a second memory circuit (or a line sequential drive latch circuit), a DAC circuit, and the like. Here, the first memory circuit is a memory for capturing digital video signals input from the outside at an appropriate timing given by the sequential selection circuit, and the second memory circuit uses digital data transmitted in a dot sequential manner. This is a memory for operating a DAC circuit by line sequential driving. In this way, by driving the DAC circuit line-sequentially, the driving capability necessary for the DAC circuit capability is lowered, and low power consumption is realized. Patent document 1 etc. are proposed as a detailed structural example of a liquid crystal display device.

JP 2000-242209 A

  In a drive circuit integrated liquid crystal display device, it is necessary to form a complicated circuit with a design rule about 10 times larger than that of an IC. Therefore, the data line drive circuit including the first memory circuit and the second memory circuit is large in size. Therefore, there is a problem that the peripheral area size of the display area of the liquid crystal display device is increased. This problem becomes more prominent as the number of gradations of the DAC circuit is increased. In view of the above problems, the present invention proposes a data line driving circuit which suppresses an increase in power consumption while reducing the size of the device by omitting the second memory circuit.

  According to an aspect of the present invention, a data line driving circuit converts a first digital data into a first analog signal and outputs the DAC circuit, and the first analog signal is supplied to the first digital data. A first holding circuit that holds an analog signal; and an analog buffer circuit that outputs a potential based on the first analog signal held in the first holding circuit to a data line. The time period during which the first analog signal is supplied from the first DAC circuit to the first holding circuit is shorter than the time period during which the analog buffer circuit outputs the potential to the data line.

  In another aspect of the present invention, the data line driving circuit further includes a second holding circuit that is supplied with a second analog signal and holds the second analog signal. The DAC circuit converts the first digital data and the second digital data into the first analog signal and the second analog signal, respectively, so that the first analog signal and the second analog signal are converted. The analog signal is output alternately. Further, the first holding circuit and the second holding circuit are alternately electrically connected to the DAC circuit, whereby the first analog signal and the second analog signal are converted into the first analog signal. It is supplied to the holding circuit and the second holding circuit, respectively. Further, the first holding circuit and the second holding circuit are alternately electrically connected to the analog buffer circuit, whereby the first analog signal and the second analog signal are converted into the analog buffer. Input to the circuit. Here, at the timing when the first analog signal is supplied from the DAC circuit to the first holding circuit, the second analog signal is input from the second holding circuit to the analog buffer circuit.

  In still another aspect of the invention, the DAC circuit is configured to output a plurality of analog potentials, and the first holding circuit receives a plurality of analog potentials and outputs one analog potential.

  In still another embodiment of the present invention, the active element constituting the data line driving circuit is a thin film transistor formed on a glass substrate.

  In still another aspect of the present invention, a liquid crystal display device includes the above-described data line driving circuit. Further, the electronic apparatus may include such a liquid crystal display device.

  According to the configuration as described above, the first holding circuit is provided in the subsequent stage of the DAC circuit, and the analog buffer circuit can be driven line-sequentially by holding the analog potential in the first holding circuit. Compared to the two-memory circuit, the first holding circuit has a significantly reduced number of elements, and the device can be downsized.

(Example 1)
FIG. 1 is a block diagram of a 6-bit DAC built-in VGA liquid crystal data line driving circuit 302 for realizing the first embodiment of the present invention.

  The data line driving circuit 302 receives the digital video signals D1 to D18 and the clock signal CLK synchronized with the signal and the signal ST indicating the SYNC timing from the outside, and the analog signals are supplied to the data lines 202-1 to 1920 based on these digital signals. This circuit outputs a potential.

  Specifically, in this embodiment, the data line driving circuit 302 includes 643 sequential selection unit circuits 530-0 to 642, 1920 unit driving circuits 540-1 to 1920, an inverter circuit 570, and a reference potential generation. A source 580, a NAND circuit 581, and an inverter circuit 582 are provided. Reference potential generation source 580 is also referred to as a reference potential generator.

  Each of the sequential selection unit circuits 530-0 to 642 includes a clock signal terminal CLK1, a clock signal terminal CLK2, an in terminal, and an out terminal. The ST signal is connected to the in terminal of the sequential selection unit circuit 530-0. In addition, the sequential selection unit circuits 530-0 to 642 are connected in series such that the out terminal of the sequential selection unit circuit 530-0 is connected to the in terminal of the sequential selection unit circuit 530-1. Further, each of the sequential selection unit circuits 530-1 to 640 is configured to select the corresponding selection signal terminal 510-1 to 640. Further, the out terminal of the sequential selection unit circuit 530-641 and the out terminal of the sequential selection unit circuit 530-642 are connected to two input terminals of the NAND circuit 581. The output of the NAND circuit 581 is connected to the inverter circuit 582. The output of the inverter circuit 582 is connected to the signal wiring 590.

  Here, among the sequential selection unit circuits 530-0 to 640, the even-numbered ones are expressed as even-numbered sequential selection unit circuits, and the odd-numbered ones are expressed as odd-numbered sequential selection unit circuits. When this notation is used, the CLK signal input from the outside is connected to the clock signal terminal CLK1 of the even-numbered sequential selection unit circuit, and the CLK signal inverted by the inverter circuit 570 is connected to the clock signal terminal CLK2. The CLK signal inverted by the inverter circuit 570 is connected to the clock signal terminal CLK1 of the odd-stage sequential selection unit circuit (for example, the sequential selection unit circuit 530-1), and the CLK signal is connected to the clock signal CLK2. In other words, the connection relationship between the clock signal terminals CLK1 and CLK2 and the CLK signal of the odd-stage sequential selection circuit is opposite to that of the even-stage sequential selection circuit.

  FIG. 2 shows the circuit configuration of each of the sequential selection unit circuits 530-n. Here, n is an integer of 1 to 640. The sequential selection unit circuit 530-n includes a D-FF circuit 535-n using a clocked inverter, a NAND circuit 531-n, and an inverter circuit 532-n. The circuit configuration of the sequential selection unit circuits 530-0, 641, and 642 is the same as the circuit configuration of the sequential selection unit circuit 530-n except that it is not connected to the selection signal terminal 510-n.

  Returning to FIG. 1, 1920 unit drive circuits 540-1 to 1920 are further arranged in the data line drive circuit 302. As described above, when n is an integer of 1 to 640, three adjacent unit drive circuits 540- (n * 3-2), unit drive circuit 540- (n * 3-1), and unit drive A common selection signal terminal 510-n is connected to the circuit 540-n * 3, and the selection timing is sequentially given by three units. The unit drive circuit 540- (n * 3-2) receives video signals D1 to D6, the unit drive circuit 540- (n * 3-1) receives video signals D7 to D12, and the unit drive circuit 540-n. * 3 is connected to video signals D13 to D18, respectively. In addition, a signal wiring 590 is input to each of all the unit drive circuits 540-1 to 1920.

  FIG. 3 is a circuit diagram of the unit drive circuit 540-m. Here, m is an integer from 1 to 1920. The unit drive circuit 540-m includes six transmission gates 601- (m, 1) to (m, 6), six clocked inverters 602- (m, 1) to (m, 6), A decoder circuit 620, a transmission gate 610-m, a holding circuit 545-m, and an analog buffer circuit 550-m are provided.

  The digital signals Dk to Dk + 5 are supplied to the inputs of the six transmission gates 601- (m, 1) to (m, 6), respectively. Where m = 1, 4, 7,. . . , 1918, k = 1 and m = 2, 5, 8,. . . , 1919, k = 7 and m = 3, 6, 9,. . . , 1920, k = 13.

  A selection signal terminal 510-n is commonly supplied to each of the transmission gates 601- (m, 1) to (m, 6). Each of the transmission gates 601- (m, 1) to (m, 6) becomes conductive at the timing when the selection signal terminal 510-n is selected, and therefore the digital signals Dk to Dk + 5 are sent to the decoder circuit 620. Data is input. At the same time, the clocked inverters 602-(m, 1) to (m, 6) connected to the digital signals Dk to Dk + 5 are also operated, and inverted signals of the digital signals Dk to Dk + 5 are also input to the decoder circuit 620. Hereinafter, the decoder circuit 620 is also referred to as a DAC circuit 620.

  The DAC circuit 620 is a decoder circuit in which 64 switches in which 6 Nch transistors are arranged in series are arranged, and reference power supplies V0 to V63 are connected to one of the switches. The other side of the switch is short-circuited and connected to the input terminals of the holding circuit 545-m and the analog buffer circuit 550-m through the transmission gate 610-m. Here, the DAC circuit 620 outputs any one of the reference power supplies V0 to V63 to the transmission gate 610-m according to the bit state of the input digital signals Dk to Dk + 5. For example, if all the digital signals Dk to Dk + 5 are LOW, V0 is output, and if all are high, V63 is output.

  The transmission gate 610-m is turned on at the timing when the selection signal terminal 510-n is selected, and any one of the reference potentials V0 to V63 is written into the holding circuit 545-m. Here, the holding circuit 545-m is composed of a capacitor having a proper capacitance (0.5 pF in this case) that is grounded. When the selection signal terminal 510-n is not selected, the transmission gate 610-m is turned off, and the potential written in the holding circuit 545-m is held until the next selection timing. The potential written in the holding circuit 545-m becomes an appropriate potential by the analog buffer circuit 550-m at the timing when the signal wiring 590 is selected, and is output to the data line 202-m with higher driving capability. FIG. 5 is a circuit diagram of the analog buffer circuit 550-m. In this embodiment, a two-stage differential amplifier is used, and in this case, the input (in) potential and the output (out) potential are equal. Here, VH = 8V, VL = -4V, Vbias1 = 0V, and Vbias2 = 4V. The potential VW and the potential VB are inverted potentials of + 4V and 0V. The D1 to D18, CLK, and ST signals input from the outside are digital signals of 0V / 8V, and the data line driving circuit 302 is all driven by a 0V / 8V power supply except the analog buffer circuit 550-m.

  As described above, the data line driving circuit 302 also includes the reference potential generation source 580. FIG. 4 is a circuit diagram of the reference potential generation source 580. The potential VB and the potential VW are a black reference potential and a white reference potential, respectively, which are inverted at a constant period and are signals having opposite phases. The potential VB and the potential VW are divided by a resistor having an appropriate resistance value to generate reference potentials V0 to V63.

  As another embodiment, an analog buffer circuit 550'-m shown in FIG. 6 may be used instead of the analog buffer circuit 550-m. In this example, VH = + 8V, VL = 0V, and Vbias = + 3V. At this time, the output (out) potential is the input (in) potential −3V. Therefore, the potential VW and the potential VB of the reference potential generation source 580 shown in FIG. 4 may be set higher by 3V and set to the inverted potentials of + 7V and + 3V. This circuit configuration has the advantage that the number of elements is small and the applied power supply voltage is small. However, it has a demerit that the linearity of the input potential and the output potential deteriorates when the transistor characteristics are not ideal saturation characteristics, so it is only necessary to decide which one to adopt considering both the merit and demerit .

  FIG. 7 is a timing chart of this embodiment. The CLK signal is a clock with a half cycle of T1C (seconds), the ST signal has a cycle of T1H = 646 × T1C (seconds), the high period is T1C (seconds), and the CLK signal is out of phase with T1C ÷ 2 (seconds) These signals are both input from the outside. The video signals D1 to D18 are digital signals whose data period is T1C (seconds) in synchronization with the CLK signal. In this embodiment, data in the case of monochrome display is shown. The first data (D1 to D18 data High = black in FIG. 7) is input 1.5 × T1C (seconds) after the ST signal, and then the next data is input every T1C seconds (every CLK signal inversion). In this embodiment, T1C = 53.53 nanoseconds. When such data is input, the selection signal terminal 510-n is selected every T1C seconds as shown in FIG. That is, in FIG. 3, since the transmission gate 610-m is in the conductive state for T1C seconds, the period during which the DAC circuit 620 writes the potential to the holding circuit 545-m is T1C seconds. On the other hand, the selection period (TAMP) of the signal wiring 590 is 3 × T1C seconds as shown in FIG. 7, and the DAC circuit 620 writes the data to the data line 202-m during the analog buffer circuit 550-m. 3 times the time to write to Also, VW and VB are signals of 1292 × T1C (seconds) periods that are inverted from each other + 4V and 0V during the ST selection period, and have opposite phases. As a result, 1H inversion driving is realized in which the potential output from the data line is reversed in polarity for each ST signal.

  As described above, in the data line driving circuit 302 according to this embodiment, the analog circuit is held in the holding circuit 545-m so that the writing time of the analog buffer circuit 550-m is longer than the writing time of the DAC circuit 620. Therefore, even if the capacity of the data line 202-m is increased, the driving capability of the analog buffer circuit 550-m can be minimized, and the power consumption of the analog buffer circuit 550-m can be reduced correspondingly. In addition, since there is no digital memory circuit, the area of the drive circuit is reduced.

  FIG. 8 is a configuration diagram of an active matrix substrate 101 using the data line driving circuit 302 of FIG. On the active matrix substrate 101, 480 scanning lines (201-1 to 480) and 1920 data lines (202-1 to 1920) are formed orthogonally, and 480 capacitance lines (203- 1 to 480) are arranged in parallel with the scanning lines (201-1 to 480). The capacitor lines (203-1 to 480) are short-circuited to each other and are also connected to the opposing conductive portion (330), and an appropriate common potential VCOM is applied from the power supply circuit 304. Here, the common potential VCOM is an AC inversion potential of +4 V and 0 V, and is driven with the same phase as the potential VW in the timing chart of FIG.

The scanning lines (201-1 to 480) are connected to the scanning line driving circuit 301 and sequentially given driving signals. As described above, the data lines (202-1 to 1920) are connected to the data line driving circuit 302 and are supplied with video signals. The scanning line driving circuit 301 and the data line driving circuit 302 are connected to the power supply circuit 304 and the signal circuit 305, and supply necessary signals (for example, SP and CLK signals) and necessary potentials (for example, +8, −4, 0V DC power supply). Supplied. The data line driving circuit 302 is supplied with digital video signals D1 to D18 from the signal input terminal 320. The signal circuit 305 and the power supply circuit 304 are also supplied with necessary signals (master clock, SYNC signal, etc.) and power supply potential (for example, +2.6 V and GND signal).
The scanning line driving circuit 301, the data line driving circuit 302, the power supply circuit 304, and the signal circuit 305 are formed by integrating polysilicon thin film transistors as active elements on a glass substrate constituting a part of the active matrix substrate. This is a so-called drive circuit built-in type liquid crystal display device manufactured in the same process as a pixel switching element (401-ji) to be described later.

  FIG. 9 is a circuit diagram in the vicinity of the intersection of the i-th data line (202-i) and the j-th scanning line (201-j) in the pixel display area indicated by the dotted line 310 in FIG. A pixel switching element (401-j-i) made of an N-channel field effect polysilicon thin film transistor is formed at each intersection of the scanning line (201-j) and the data line (202-i), and its gate electrode Are connected to the scanning line (201-j), and the source / drain electrodes are connected to the data line (202-i) and the pixel electrode (402-j-i), respectively. The pixel electrode (402-ji) and the electrode short-circuited to the same potential form a capacitance line (203-j) and an auxiliary capacitance capacitor (403-ji), and when assembled as a liquid crystal display device. Forms a capacitor with the counter substrate electrode 930 (COM) across the liquid crystal element.

  FIG. 10 is a perspective configuration diagram (partially sectional view) of the transmission type VGA resolution liquid crystal display device with a built-in 6-bit DAC in the first embodiment using the active matrix substrate of FIG. The liquid crystal display device 910 includes an active matrix substrate 101 (first substrate) and a counter substrate 912 (second substrate) which are bonded to each other with a sealant 923 at a predetermined interval and sandwich a nematic liquid crystal material 922. Although not shown, an alignment material made of polyimide or the like is applied onto the active matrix substrate 101 and rubbed to form an alignment film. The counter substrate 912 includes a color filter corresponding to a pixel (not shown), a black matrix for preventing light leakage and improving contrast, and a common potential short-circuited with the counter conductive portion 330 on the active matrix substrate 101. A counter substrate electrode 930 made of an ITO film is supplied. An alignment material made of polyimide or the like is applied to a surface in contact with the liquid crystal material 922, and is rubbed in a direction orthogonal to the rubbing direction of the alignment film of the active matrix substrate 101.

  Further, an upper polarizing plate 924 is disposed outside the counter substrate 912, and a lower polarizing plate 925 is disposed outside the active matrix substrate 101, so that the polarization directions thereof are orthogonal to each other (crossed Nicols). Further, a backlight unit 926 forming a surface light source is disposed below the lower polarizing plate 925. The backlight unit 926 may be a cold cathode tube or LED with a light guide plate or a scattering plate attached thereto, or a unit that emits light entirely from an EL element. Although not shown, if necessary, the periphery may be covered with an outer shell, or a protective glass or acrylic plate may be attached further above the upper polarizing plate 924, and optical for improving the viewing angle. A compensation film may be attached.

  In addition, the active matrix substrate 101 is provided with a protruding portion 927 that protrudes from the counter substrate 912, and an FPC (flexible substrate) 928 is mounted on and electrically connected to the signal input terminal 320 in the protruding portion 927. ing.

  FIG. 11 is a block diagram showing a specific configuration of the electronic device 990 in this embodiment. In the electronic device 990, the liquid crystal display device 910 is the 6-bit DAC built-in VGA resolution liquid crystal display device described with reference to FIG. 10, and a power supply circuit 784 and a video processing circuit 780 are required through an FPC (flexible substrate) 928 and a signal input terminal 320 Various signals and power are supplied to the liquid crystal display device 910. The central processing circuit 781 acquires input data from the input / output device (783) via the external I / F circuit (782). Here, the input / output device (783) is, for example, a keyboard, a mouse, a touch panel, a trackball, an LED, a speaker, an antenna, or the like. The central processing circuit (781) performs various arithmetic processing based on data from the outside, and transfers the result to the video processing circuit 780 or the external I / F circuit 782 as a command. The video processing circuit 780 updates the video information based on the command from the central processing circuit 781 and changes the signal to the liquid crystal display device 910, whereby the display video of the liquid crystal display device 910 changes.

  The electronic device 990 configured as described above has a small driving circuit portion of the display device, low power consumption, and low cost because the driving circuit and the signal circuit are integrally formed on the active matrix substrate 101. High reliability. For this reason, a small and long battery driving time and a highly reliable electronic device can be provided at low cost.

  Specifically, the electronic device includes a monitor, a TV, a notebook computer, a PDA, a digital camera, a video camera, a mobile phone, a mobile photo viewer, a mobile video player, a mobile DVD player, a mobile audio player, and the like.

(Example 2)
FIG. 12 is a configuration diagram of a 6-bit DAC built-in VGA liquid crystal data line driving circuit 302b for realizing the second embodiment of the present invention. Compared with the data line driving circuit 302 in FIG. 1, the unit driving circuits 540-1 to 1920 are replaced with the unit driving circuits 540b-1 to 1920, and the signal POL from the outside is input, and the selection unit circuits 530-641 are sequentially selected. The sequential selection unit circuits 530-642, NAND circuit 581 and inverter circuit 582 are respectively deleted, and the signal wiring 590 is connected to an external AMPON signal. Other than that, there is no difference from FIG. 1 of the first embodiment. In FIG. 12, parts that are the same as those in FIG. 1 are not described in detail by using the same symbols.

  FIG. 13 is a circuit diagram of the unit drive circuit 540b-m. Compared to the unit drive circuit 540-m in FIG. 3, the holding circuit 545-m is replaced with a first holding circuit 546-m and a second holding circuit 547-m, and the first holding circuit 546-m and the second holding circuit are replaced. The first input transmission gate 621-m and the second input transmission gate 622-m that switch the input of the 547-m by the POL signal, and the outputs of the first holding circuit 546-m and the second holding circuit 547-m are switched by the POL signal. A first output transmission gate 623-m and a second output transmission gate 624-m are respectively added. When the POL signal is Low, the first input transmission gate 621-m and the second output transmission gate 624-m are turned on, the second input transmission gate 622-m and the first output transmission gate 623-m are turned off, and POL When the signal is High, the reverse is the case. In FIG. 13, the same reference numerals are used for portions that are the same as those in FIG. 3, and detailed description thereof is omitted.

  FIG. 14 is a timing chart in the second embodiment. The AMPON signal (signal wiring 590) has a period T1H (= 646 × T1C), and a high period (TAMP ′) is 640 × T1C seconds. The POL signal has the same waveform as VW. Other waveforms are the same as those in FIG. 7 of the first embodiment. Therefore, every time the selection signal terminal 510-n is selected, High / Low is inverted in the POL signal, and either the first input transmission gate 621-n or the second input transmission gate 622-n is alternately opened. ing. In other words, the analog potential output from the DAC circuit 620 is charged alternately between the first holding circuit 546-m and the second holding circuit 547-m.

  On the other hand, the input (in) of the analog buffer circuit 550-m is connected to the first output transmission gate 623-m and the second output transmission gate 624-m, and each time the selection signal terminal 510-n is selected, Are alternately turned ON, and the potential of either the first holding circuit 546-m or the second holding circuit 547-m is alternately input. At this time, the holding connected to the input of the analog buffer circuit 550-m The circuit and the holding circuit written from the DAC circuit 620 are always different. That is, at the timing when the potential is written from the DAC circuit 620 to the first holding circuit 546-m, the analog buffer circuit 550-m is connected to the second holding circuit 547-m, and from the DAC circuit 620 to the second holding circuit. At the timing when the potential is written in the circuit 547-m, the analog buffer circuit 550-m is connected to the first holding circuit 546-m.

  In this manner, the potential output from the analog buffer circuit 550-m during the AMPON signal High period is the potential written from the DAC circuit 620 during the previous AMPON signal High period. That is, since the first holding circuit 546-m and the second holding circuit 547-m function as an analog potential memory, the analog buffer circuit 550-m can be driven by line sequential writing.

  The first memory circuit and the second memory circuit in the conventional example are digital S-RAM type memory circuits, and the circuit area increases. However, the first holding circuit 546-m and the second holding circuit 547-m are storage capacitor elements. Since only one is grounded, the circuit area is reduced. The writing time of the analog buffer circuit 550-m is the AMPON signal High period (= 640 × T1C), which is longer than the writing time (3 × T1C) in the first embodiment, and the driving capability. Can be set even smaller to reduce power consumption.

  The configuration of the active matrix substrate 101, the liquid crystal display device 910, and the electronic equipment using the data line driving circuit 302b of this embodiment is the same as that of the first embodiment except that the data line driving circuit 302 is replaced with the data line driving circuit 302b. Since it is the same as that, it is omitted. Note that the AMPON signal and the POL signal used in the data line driver circuit 302 b are supplied from the signal circuit 305.

  FIG. 15 is a block diagram of a unit drive circuit 540c-m that provides another embodiment of the second embodiment instead of FIG. Compared with FIG. 13, the clocked inverters 602-(m, 1) to (m, 6) are deleted and replaced with first memory circuits 630-(m, 1) to (m, 6). Further, the transmission gate 610-m is deleted, and the output of the DAC circuit 620 is directly connected to the first input transmission gate 621-m and the second input transmission gate 622-m.

  In this alternative embodiment, the selection signal terminal 510-n is selected, and the digital video signals Dk to Dk + 5 that have passed through the transmission gates 601- (m, 1) to (m, 6) are converted into the first memory circuit 630- (m , 1) to (m, 6), and then held until the selection signal terminal 510-n is selected. Therefore, the DAC circuit 620 continues to output the same potential during the period from the selection of the selection signal terminal 510-n to the next selection. Since the holding circuit to be written is switched at the timing when the POL signal is inverted, the period during which the DAC circuit 620 is actually writing to the first holding circuit 546-m or the second holding circuit 547-m is (646-n) × T1C ( Second). Since n = 1 to 640, it is at least 6 × T1C (seconds), and the writing time is at least 6 times that of the configuration of FIG. Therefore, the writing ability of the DAC circuit 620 and the reference potential generation source 580 can be lowered, and the circuit can be configured with lower power consumption and a small circuit area. The writing capability of the DAC circuit 620 and the reference potential generation source 580 may be designed so that all of n = 1 to 640 can be written uniformly at 6 × T1C (seconds). If n is small, the writing capability is reduced. May be. The other points are the same as those of the unit drive circuit 540b-m in FIG. 13, and the detailed description is omitted by using the same symbols. A description of the data line driving circuit according to this alternative embodiment will be omitted because only the unit driving circuit 540b-m is replaced with the unit driving circuit 540c-m in the data line driving circuit of FIG.

(Example 3)
FIG. 16 is a diagram showing the configuration of a 6-bit DAC built-in VGA liquid crystal data line driving circuit 302d for realizing the third embodiment of the present invention. Compared to FIG. 12 showing the data line driving circuit 302c in the second embodiment, sequential selection unit circuits 530-641 are sequentially added and are sequentially connected in series to the selection unit circuits 530-640. Further, each unit drive circuit 540b-m is replaced with each unit drive circuit 540d-m, and is connected to an adjacent selection signal terminal 510-n + 1 in addition to the selection signal terminal 510-n. The reference potential generation source 580 is also replaced with the reference potential generation source 580d. Other than that, there is no difference from FIG. 12 of the second embodiment. In FIG. 16, the same reference numerals are used for portions that are the same as those in FIG. 12, and detailed description thereof is omitted.

  FIG. 17 is a circuit diagram of the unit drive circuit 540d-m. Compared to FIG. 15 showing the unit drive circuit 540c-m in the configuration example according to the second embodiment, the first memory circuit 630- (m, 1) to (m, 6) is replaced with the first memory circuit 640- (m, 1 ) To (m, 6), and adjacent selection signal terminals 510-n + 1 are connected. Further, the DAC circuit 620 is replaced with the DAC circuit 620 ′, and the output terminal 691 from the DAC circuit 620 ′ is connected to the first CDAC circuit 548-m (corresponding to the first holding circuit) through the third input transmission gate 625-m. The second CDAC circuit 549-m (corresponding to the second holding circuit) is connected to each other through the fourth input transmission gate 626-m. The output terminal 692 from the DAC circuit 620 ′ is connected to the first CDAC circuit 548-m (corresponding to the first holding circuit) through the fifth input transmission gate 627-m, and to the second CDAC circuit 549 through the sixth input transmission gate 628-m. -M (corresponding to the second holding circuit) respectively. The first CDAC circuit 548-m is connected to the positive and negative outputs of the first memory circuit 640- (m, 1) to (m, 2) and the POL signal, and the output terminal is the first output transmission gate 623-m. Connected to. The second CDAC circuit 549-m is connected to the positive and negative outputs of the first memory circuit 640- (m, 1) to (m, 2) and the reverse-phase signal of the POL signal, and the output terminal transmits the second output. Connected to gate 624-m. Since the timing chart in the present embodiment is basically the same as that of FIG. 14 used in the second embodiment, description thereof is omitted. The output terminal 691 is also referred to as a first output signal wiring, and the output terminal 692 is also referred to as a second output signal wiring.

  The DAC circuit 620 ′ in FIG. 17 differs from the DAC circuit 620 of the first and second embodiments in that decoding is performed using only the output signals of the first memory circuits 640- (m, 3) to (m, 6). This is a 4-bit DAC circuit. The DAC circuit 620 ′ includes a first sub-DAC circuit 620′a and a second sub-DAC circuit 620′b, each of which includes 16 n-channel transistors connected in series. 1 and connected to the output terminal 691 or the output terminal 692 with one end shorted to the reference potential Vn and connected to the output terminal 691 or the output terminal 692, and the number of bits is 6 bits from the DAC circuit 620 of the first and second embodiments. The other is just the 4bit. The reference potential connected between the first sub DAC circuit 620'a and the second sub DAC circuit 620'b is shifted by one level. That is, when all the outputs (OUT) of the first memory circuits 640- (m, 3) to (m, 6) are High, the first sub DAC circuit 620′a selects the reference potential V16, whereas The two sub DAC circuit 620′b selects the reference potential V15. That is, if the output terminal 691 is the reference potential Vn, the output terminal 692 always outputs an adjacent reference potential such as the reference potential Vn-1. Here, when the outputs (OUT) of the first memory circuits 640- (m, 1) to (m, 2) are all low, an analog potential to be written to the data line is output to the output terminal 692, and to the output terminal 691. If it is a 6-bit video signal, an analog potential on four gradations is output. When the POL signal = Low, the analog potential applied to the output terminal 691 (hereinafter referred to as VIN1) is supplied to the first input terminal IN1 of the first CDAC circuit 548-m through the third input transmission gate 625-m. When High, the analog signal is input to the first input terminal IN1 of the second CDAC circuit 549-m (corresponding to the second holding circuit) through the fourth input transmission gate 626-m, and is similarly supplied to the output terminal 692. The potential (hereinafter referred to as VIN2) is transmitted to the second input terminal IN2 of the first CDAC circuit 548-m through the fifth input transmission gate 627-m when the POL signal = Low, and the sixth input transmission when the POL signal = High. The signals are input to the second input terminal IN2 of the second CDAC circuit 549-m (corresponding to the second holding circuit) through the gate 628-m.In FIG. 17, the same reference numerals are used for portions that are the same as those in FIG. 15, and detailed description thereof is omitted.

  FIG. 18 is a circuit diagram of the first memory circuit 640-m. The IN terminal is connected to the capacitor 641 and also connected to the input terminal of the NAND circuit 643. The output of the inverter circuit 642 is connected to the other end of the capacitor 641, and the input is connected to the output of the NAND circuit 643. The other input of the NAND circuit 643 is connected to the NT terminal (= selection signal terminal 510-n + 1). The NT terminal is also connected to the control terminal of the clocked inverter 644, and the signal from the NT terminal generates a reverse phase signal at the inverter 645 and is connected to the reverse phase control terminal of the clocked inverter 644. The input of the clocked inverter 644 is connected to the IN terminal, and the output is connected to one end of the capacitor 646 and the inverter 647.

  With such a configuration, when the selection signal terminal 510-n is selected, the transmission gates 601- (3 * n-2, 1-6), (3 * n-1, 1-6), (3 When * n, 1-6) is opened and the signal input to the IN terminal is High, the level is shifted by the inverter circuit 642 at the timing when the selection signal terminal 510-n is selected. On the other hand, when the signal input to the IN terminal is Low, it remains as it is. That is, the potential amplitude input to the clocked inverter 644 becomes the potential amplitude of the video signal Dk + the power source potential difference of the inverter circuit 642, and level shift is performed, so that a memory circuit with a built-in level shifter whose output amplitude is amplified from the input amplitude It works. With such a configuration, it is possible to increase the potential level applied to the DAC circuit 620 ′ and ensure driving capability while reducing the power consumption by reducing the potential amplitude of the video signal Dk.

  In this embodiment, the potential amplitude of the video signal Dk (k = 1 to 18) is 0V / 5V, the power supply potential of the inverter circuit 642 and the NAND circuit 643 is 0V / 5V, the clocked inverter 644, and the inverters 645, 647, and 648. The power supply potential is 0V / 8V. Other power supply potential settings are the same as those in the first and second embodiments. With such a configuration, although the potential amplitude of the video signal Dk is 0V / 5V, the output amplitude from the first memory circuit is 0V / 8V.

  Note that when the level shift is unnecessary, the circuit configuration shown by the first memory circuit 630-m in FIG. 15 may be used as the first memory circuit instead of the configuration shown by 640-m in FIG. Since the area of the circuit configuration of the first memory circuit 630-m is smaller, which one should be selected may be determined from the power consumption and the priority of the circuit area. Alternatively, the first memory circuit 640-m may be eliminated, only the clocked inverter 602-m may be provided as in the configuration of FIG. 13, and the transmission gate 610-m may be placed at the output of the DAC circuit 620 '. In this case, the circuit area is further reduced, but since the writing time of the DAC circuit 620 'is shortened, the power consumption is increased. Similarly, of course, the first memory circuit 630-m in FIG. 15 of the second embodiment may be replaced with the configuration of the first memory circuit 640-m in FIG.

  FIG. 19 is a circuit diagram of the first CDAC circuit 548-m and the second CDAC circuit 549-m. The potential on the first input terminal IN1 is transmitted through the transmission gates 811-m and 813-m, and the potential on the second input terminal IN2 is transmitted through the transmission gates 812-m and 814-m to input signals D1, XD1, D2, and so on. The signals are selected and input to the transmission gate 821-m and the transmission gate 822-m according to XD2. Since the CMB terminal of the first CDAC circuit 548-m is connected to the POL signal and the CMB terminal of the second CDAC circuit 549-m is connected to the reverse phase signal of the POL signal, the potential is input to the input terminal IN1 ( That is, at the timing when the third input transmission gate 625-m and the fifth input transmission gate 627-m in FIG. 17 are open), the CMB signal (= POL signal) of the first CDAC circuit 548-m is always LOW, At the timing when a potential is input to the terminal IN2 (that is, the fourth input transmission gate 626-m and the sixth input transmission gate 628-m in FIG. 17 are open), the CMB signal (= POL) of the second CDAC circuit 549-m. The reverse phase of the signal is always LOW. That is, since the transmission gate 821-m and the transmission gate 822-m are open at this timing, the selected potential is charged in the capacitor 841-m and the capacitor 842-m. Further, 843-m is charged with the potential VIN2 of the input terminal IN2. At this time, the transmission gate 831-m and the transmission gate 832-m are closed.

  For example, assuming that D1 = High (hence XD1 = Low) and D2 = Low (hence XD2 = High), the transmission gate 811-m and the transmission gate 814-m are opened, and the transmission gate 812-m and the transmission gate 813- m is closed. Accordingly, the capacitor 841-m is charged with VIN1, the capacitor 842-m is charged with VIN2, and the capacitor 843-m is charged with VIN2.

  Next, when the POL signal is inverted, the transmission gates 821-m, 822-m, and 823-m are closed, and the transmission gates 831-m and 832-m are opened. Then, one ends of the capacitors 841-m, 842-m, and 843-m are all short-circuited with the output terminal OUT.

  When the capacitance of the capacitor 841-m is 100 fF, the capacitance of the capacitor 842-m is 200 fF, and the capacitance of the capacitor 843-m is 100 fF, when the POL signal is inverted in the state of the previous example, the potential VOUT at the OUT terminal is VOUT = VIN1 × 1/4 + VIN2 × 3/4. Thus, the output potential VOUT when the POL signal is inverted is (VIN1−VIN2) × 1/1 from VOUT = VIN1 × 3/4 + VIN2 × 1/4 to VIN2 in accordance with the input signals D1, XD1, D2, and XD2. There are 4 steps in 4 steps. That is, it operates as a 2-bit C-DAC.

  FIG. 20 is a circuit diagram of the reference potential generation source 580d. Compared with the reference potential generating source 580 of the first and second embodiments shown in FIG. 4, the basic configuration is the same, but the number of potentials for voltage division output is reduced from 64 to 17. This is a change according to the number of bits of the DAC circuit 620 '.

  Thus, in this circuit configuration, the DAC circuit 620 ′ decodes the upper 4 bits, outputs two analog potentials, and the first CDAC circuit 548-m or the second CDAC circuit 549-m decodes the lower 2 bits. It has a DAC configuration. The first CDAC circuit 548-m and the second CDAC circuit 549-m also play the same role as the first holding circuit 546-m and the second holding circuit 547-m of the second embodiment. That is, when the POL signal is LOW, when the input is made to the first CDAC circuit 548-m, the second CDAC circuit 549-m decodes the potential inputted in the previous cycle and converts it into an appropriate analog potential, The signal is output to the analog buffer circuit 550-m through the second output transmission gate 624-m, and vice versa when the POL signal = High.

  With this configuration, the size of the DAC circuit 620 ′ is reduced to half that of the DAC circuit 620 of the first embodiment and the second embodiment without sacrificing the number of output analog gradations, and the circuit area is further reduced. A data line driving circuit can be realized.

  The present invention is not limited to the embodiments, and is used for liquid crystal display devices such as a vertical alignment mode (VA mode) instead of the TN mode, an IPS mode using a lateral electric field, and an FFS mode using a fringe electric field. It doesn't matter. Moreover, not only a total transmission type but also a total reflection type and a reflection / transmission combined type may be used.

1 is a circuit diagram of a data line driving circuit according to a first embodiment of the present invention. The circuit diagram of the sequential selection unit circuit based on the Example of this invention. 1 is a circuit diagram of a unit drive circuit according to a first embodiment of the present invention. The circuit diagram of the reference potential circuit concerning the example of the present invention. 1 is a circuit diagram of an analog buffer circuit according to an embodiment of the present invention. The circuit diagram of the analog buffer circuit concerning another embodiment of the 1st example of the present invention. The timing chart which concerns on 1st Example of this invention. 1 is a configuration diagram of an active matrix substrate according to an embodiment of the present invention. 1 is a pixel circuit diagram of an active matrix substrate according to an embodiment of the present invention. 1 is a perspective view of a liquid crystal display device according to an embodiment of the present invention. 1 is a block diagram illustrating an embodiment of an electronic device of the present invention. The circuit diagram of the data line drive circuit concerning 2nd Example of this invention. The circuit diagram of the unit drive circuit which concerns on 2nd Example of this invention. The timing chart which concerns on 2nd Example of this invention. The circuit diagram of the unit drive circuit which concerns on another embodiment of 2nd Example of this invention. The circuit diagram of the data line drive circuit concerning 3rd Example of this invention. The circuit diagram of the unit drive circuit which concerns on 3rd Example of this invention. The circuit diagram of the 1st memory circuit concerning the 3rd example of the present invention. The circuit diagram of the CDAC circuit which concerns on 3rd Example of this invention. FIG. 6 is a circuit diagram of a reference potential circuit according to a third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Active matrix board | substrate, 201 ... Scan line, 202 ... Data line, 302 ... Data line drive circuit, 540 ... Unit drive circuit, 550, 550 '... Analog buffer circuit, 545 ... Holding circuit, 580 ... Reference potential generation source, 620 ... DAC circuit, 401 ... pixel switching element, 402 ... pixel electrode, 910 ... liquid crystal display device.

Claims (6)

A DAC circuit for converting the first digital data into a first analog signal and outputting the first analog signal;
A first holding circuit which is supplied with the first analog signal and holds the first analog signal;
An analog buffer circuit for outputting a potential based on the first analog signal held in the first holding circuit to a data line;
A data line driving circuit comprising:
The time period during which the first analog signal is supplied from the first DAC circuit to the first holding circuit is shorter than the time period during which the analog buffer circuit outputs the potential to the data line. Data line driving circuit. The data line driving circuit according to claim 1,
A second holding circuit that is supplied with a second analog signal and holds the second analog signal;
The DAC circuit converts the first digital data and the second digital data into the first analog signal and the second analog signal, respectively, so that the first analog signal and the second analog signal are converted. Output signals alternately,
The first holding circuit and the second holding circuit are alternately electrically connected to the DAC circuit, so that the first analog signal and the second analog signal become the first holding circuit. And the second holding circuit, respectively.
The first holding circuit and the second holding circuit are alternately electrically connected to the analog buffer circuit, whereby the first analog signal and the second analog signal are transferred to the analog buffer circuit. Entered,
At a timing when the first analog signal is supplied from the DAC circuit to the first holding circuit, the second analog signal is input from the second holding circuit to the analog buffer circuit.
A data line driving circuit characterized by that. The data line driving circuit according to claim 1 or 2,
The DAC circuit outputs a plurality of analog potentials,
The data line driving circuit, wherein the first holding circuit receives a plurality of analog potentials and outputs one analog potential.   4. The data line driving circuit according to claim 1, wherein the active element constituting the data line driving circuit is a thin film transistor formed on a glass substrate.   A liquid crystal display device comprising the data line driving circuit according to claim 1.   An electronic apparatus comprising the liquid crystal display device according to claim 5.

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