JP2008090673A - Cache memory control device - Google Patents

Abstract

A cache memory control apparatus capable of realizing an efficient cache memory configuration in accordance with the type of buffer to be used.
There are provided as many memory units as the number of buffer memories to be used. The cache control unit 400 assigns the input selectors 200 to 230 so that the data in the buffer memory to be used is cached in at least one memory unit. The output selectors 300 to 320 determine whether or not the data in the buffer memory to be used has hit based on the hit flags 102 to 132 output from any one of the memory units 100 to 130. .
[Selection] Figure 1

Description

  The present invention mainly relates to a cache memory control device used in a graphics device using various buffer memories.

  The graphics device uses various buffer memories. For example, a color buffer (frame buffer) / depth buffer / stencil buffer / alpha buffer / mask buffer / texture buffer / display list buffer are used. In a system in which each buffer data is stored in a storage device outside the graphics apparatus and a part of the buffer data is temporarily stored in a cache memory installed inside the graphics apparatus, the following method is applied.

(1) Separate cache memory system A dedicated cache memory is installed for each of various buffers. Each cache memory operates independently. However, the following disadvantages occur.
Depending on the type of graphics function used, an unused buffer may occur. In this case, the corresponding dedicated cache memory becomes unused, and the cache memory is wasted (disadvantage 1). For example, when the alpha buffer is not used as the graphics function, the alpha dedicated cache memory is unused.
In addition, as the types of buffers used by the graphics device increase, the number of dedicated cache memories corresponding to that increases (disadvantage 2).

(2) Unified cache memory system One cache memory is shared and used. Only the buffer data to be used is temporarily stored in the cache memory, and the cache memory can be used up with these data. Disadvantages 1 and 2 of the separate cache method can be solved. However, the following disadvantages occur.
Since the parallel operation cannot be performed, the operation speed of the graphics apparatus becomes slow. For example, when the color buffer data and the alpha buffer data cannot be read at the same timing, the operation speed of the graphics apparatus may be reduced.

  Thus, an unused cache memory is generated in the separated cache memory system. Further, in the unified cache memory system, such a problem does not occur, but parallel operation cannot be performed. In any case, a cache memory that can be operated in parallel and has no unused portion is the most efficient for the graphics device, but in the past, either method could not be realized.

  On the other hand, a technique for improving the usage efficiency of a cache memory by dynamically reconfiguring the cache memory has been developed (see, for example, Patent Document 1 or Patent Document 2).

Japanese Patent Laid-Open No. 5-241962 JP-A-2005-293300

  However, the above-described technology for dynamically reconfiguring the cache memory relates to a configuration change for a cache memory that operates independently, and has a problem that it cannot be applied to a cache memory that operates in parallel.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a cache memory control device capable of realizing an efficient cache memory configuration according to the type of buffer used. .

  The cache memory control device according to the present invention includes a plurality of memory units provided with a number equal to or greater than the type of buffer memory to be used, and a plurality of memory units corresponding to the plurality of memory units. A plurality of input selection means for providing an address of the buffer memory to be used, and a buffer memory provided corresponding to the buffer memory to be used, and used based on a hit flag output from any one of the plurality of memory units. Output selection means for determining whether or not the data in the buffer memory to be hit is hit, and assigning the input selection means so that at least one input selection means selects the address of the buffer memory to be used, and output selection means Selects the output of the memory unit that caches the data in the corresponding buffer memory. To such, in which a cache memory control means for assigning the output selection means.

  The cache memory control device of the present invention is provided with a number of memory units equal to or greater than the type of buffer memory to be used, and the cache memory control means is configured so that data of the buffer memory to be used is cached in at least one memory unit. Since the input selection means and the output selection means are assigned, an efficient cache memory configuration can be realized according to the type of buffer memory to be used.

Embodiment 1 FIG.
1 is a block diagram showing a cache memory control apparatus according to Embodiment 1 of the present invention.
In the figure, the cache memory control device includes memory units 100 to 130, input selectors (input selection means) 200 to 230, output selectors (output selection means) 300 to 320, and a cache control unit (cache memory control means) 400. ing.

  In the present embodiment, it is assumed that the graphic device using the cache memory control device uses, for example, a color buffer, a depth buffer, and an alpha buffer at the same time. The reconfigurable cache memory built in the graphics apparatus is allocated to caches for three buffers. Each of the four memory units 100 to 130 is dynamically allocated as a cache memory of any one of color buffer / depth buffer / alpha buffer.

  Here, if the number of buffer memories (hereinafter simply referred to as “buffers”) simultaneously processed by the graphic device is the maximum number of parallel operations M and the number of memory units is U, a reconfigurable cache memory so that M ≦ U. Need to be configured. This is because the U memory units are divided into M cache memories that operate in parallel. The example of FIG. 1 is a cache memory configuration example when M = 3 and U = 4. Accordingly, U input selectors 200 to 230 are required, and M addresses are input to each of the input selectors 200 to 230. M output selectors 300 to 320 are required and receive hit flags and data from 100 to 130U memory units.

Details of each component will be described below.
The memory units 100 to 130 are cache memories for caching data in a buffer (not shown), and four memory units are provided in the illustrated example. The input selectors 200 to 230 are provided corresponding to the respective memory units 100 to 130, and correspond to the addresses of any of the given buffers based on the allocation of the cache control unit 400. The memory units 100 to 130 are configured to be given. The output selectors 300 to 320 are provided corresponding to the number of buffers to be used, and internally include hit determination units 301, 311, 321 and data selectors 302, 312, 322. These output selectors 300 to 320 determine whether or not the output signals from the memory units 100 to 130 are hit by the hit determination units 301, 311, and 321 based on the allocation by the cache control unit 400. In the case of a hit, the data selectors 302, 312, and 322 are configured to send data signals from the corresponding memory units 100 to 130.

  The cache control unit 400 assigns each of the input selectors 200 to 230 so as to select an address of at least one buffer, and from the memory units 100 to 130 corresponding to the assigned input selectors 200 to 230. Assignment is made to the output selectors 300 to 320 so that only the output signals are valid.

Next, the operation of the cache memory control device according to the first embodiment will be described.
First, the cache memory reconfiguration (assignment of the input selectors 200 to 230 and the output selectors 300 to 320) by the cache control unit 400 will be described.
The graphics apparatus holds function parameters, and the graphics function to be used can be changed according to the function parameters. Note that the function parameters of the graphics apparatus are set by a CPU of the graphics apparatus (not shown). The cache control unit 400 of the graphics device determines the type of buffer used by the graphics device from the set function parameters. For example, when only a graphics function that uses only a color buffer and a depth buffer is enabled, it is determined that a buffer other than the color buffer and the depth buffer is not used.

The cache control unit 400 determines the allocation of the memory units 100 to 130 from the type of buffer to be used. At least one memory unit 100 to 130 is allocated to the buffer determined to be used.
For example, when drawing using only a color buffer and a depth buffer, it is not necessary to allocate a cache memory for the alpha buffer. Therefore, two memory units 100 and 110 are allocated to the color buffer, and two memory units 120 and 130 are allocated to the depth buffer. In this way, the four memory units 100 to 130 are divided so as to be used up.

  The input selectors 200 to 230 select an input (address) to the memory units 100 to 130 based on the allocation result from the cache control unit 400. For example, as described above, when two memory units 100 and 110 are allocated to the color buffer and two memory units 120 and 130 are allocated to the depth buffer, the input selectors 200 and 210 select the address 500 of the color buffer. The input selectors 220 and 230 select the address 510 of the depth buffer.

  The output selectors 300 to 320 select an output (hit flag or data) from the memory units 100 to 130 based on the allocation result by the cache control unit 400. For example, as described above, when two memory units 100 and 110 are allocated to the color buffer and two memory units 120 and 130 are allocated to the depth buffer, the output selector 300 for the color buffer includes the memory unit 100 and 110 output is selected, and the output selector 310 for the depth buffer selects the output of the memory units 120 and 130.

  In the hit determination unit 301 of the output selector 300 for the color buffer, if any of the hit flags 102 and 112 output from the memory units 100 and 110 is valid, one of the memory units 100 and 110 is hit. This indicates that the output hit flag 301a is valid. In the memory units 100 to 130, the tag values corresponding to the index are extracted based on the given addresses 101, 111, 121, and 131, and the tag values included in the addresses 101, 111, 121, and 131 are extracted. The hit determination is performed by comparing with, and the output of the data 103, 113, 123, and 133 when the hit is determined or hit is a known cache memory operation, and the description thereof is omitted here. .

  The data selector 302 in the output selector 300 selects data output from the hit memory unit 100 (or 110) and outputs it as data 302a. On the other hand, the output selector 300 treats the signals output from the memory units 120 and 130 that are not assigned to the color buffer as invalid.

  In the output selector 310 for the depth buffer, the hit determination unit 311 generates a hit flag 311 a from the output signals from the memory units 120 and 130. The output signals from the memory units 100 and 110 are ignored. If either of the two hit flags 122 and 132 is valid, it indicates that one of the memory units 120 and 130 is hit. In this case, the hit flag 311a to be output is validated, the data of the hitting memory unit 120 (or 130) is selected and output as data 312a.

  The output selector 320 for the alpha buffer does not use the outputs of the memory units 100 to 130 at all. Therefore, the hit flag 321a and data 322a to be output are always invalidated.

  If rebuilt in this way, the configuration is the same as that of the cache memory shown in FIG. The color buffer cache memory has a two-way set associative configuration, and the depth buffer cache memory also has a two-way set associative configuration. Unused cache memory does not occur.

Next, an example of reconstruction in the case where a color buffer, a depth buffer, and an alpha buffer are used at the same time will be shown.
If the cache control unit 400 determines to use a color buffer, a depth buffer, and an alpha buffer based on the function parameters, for example, two for the color buffer, one for the depth buffer, and for the alpha buffer. One memory unit 100 to 130 is allocated. Again, the four memory units are divided so that they are used up. That is, in the cache control unit 400, the two input selectors 200 and 210 select the color buffer address 500, the input selector 220 selects the depth buffer address 510, and the input selector 230 selects the alpha buffer address 520. Control each.

  Further, in the cache control unit 400, for the output selectors 300 to 320, the output selector 300 outputs the outputs of the memory units 100 and 110, the output selector 310 outputs the output of the memory unit 120, and the output selector 320 stores the memory. Control is performed to perform hit determination and data output based on the output of the unit 130.

  If reconstructed in this way, the configuration is the same as that of the cache memory shown in FIG. The color buffer cache memory has a two-way set associative configuration, and the depth buffer cache memory and the alpha buffer cache memory have a one-way set associative (= direct map) configuration. Unused cache memory does not occur. In this example, the color buffer cache memory has a two-way set associative configuration, but may have a two-way set associative configuration with respect to a depth buffer or an alpha buffer.

  Next, an example of reconstruction when only a color buffer is used will be described. In this case, the cache control unit 400 controls the input selectors 200 to 230 and the output selectors 300 to 320 so as to allocate all the memory units 100 to 130 to the color buffer cache memory. That is, all the input selectors 200 to 230 control to select the color buffer address 500, and the color buffer output selector 300 selects the output from all the memory units 100 to 130.

  If reconstructed in this way, the configuration is the same as that of the cache memory shown in FIG. The cache memory for the color buffer has a 4-way set associative configuration. Unused cache memory does not occur.

  As described above, according to the cache memory control device of the first embodiment, the number of types of buffer memory to be used is more than that, the data of the used buffer memory is cached, and When an address is given, a plurality of memory units that output a hit flag indicating whether or not the cached data has been hit, and a plurality of memory units are provided and used for the corresponding memory units. A plurality of input selection means for giving an address of the buffer memory and a buffer memory used corresponding to the buffer memory to be used, and used based on a hit flag output from any one of the plurality of memory units Used with output selection means for determining whether or not the data in the buffer memory has been hit The input selection means is assigned so that the address of the buffer memory is selected by at least one input selection means, and the output selection means selects the output of the memory unit that caches the data in the corresponding buffer memory. Cache memory control means for assigning means, for example, parallel operation is possible even when a plurality of buffer memories are used, and a plurality of memory units are assigned even when only one buffer memory is used. Thus, an efficient cache memory configuration can be realized in accordance with the type of buffer to be used.

  Further, according to the cache memory control apparatus of the first embodiment, the cache memory control means allocates a plurality of input selection means and output selection means so that the data of any buffer memory is cached in all the memory units. Therefore, a cache memory configuration without waste can be realized.

Embodiment 2. FIG.
In the second embodiment, a memory unit that is not used is provided while satisfying the condition that at least one memory unit is allocated to the buffer to be used. Since the configuration on the drawing is the same as that of FIG. 1, description will be made with reference to FIG.

  The cache control unit 400 according to the second embodiment performs control so that at least one input selector 200 to 230 selects a buffer address to be used, and there are input selectors 200 to 230 that do not select any buffer address. It is configured to perform allocation control. Further, the unused memory units 100 to 130 are configured to stop power supply and clock supply.

For example, a reconfiguration example in the case of using a color buffer, a depth buffer, and an alpha buffer at the same time will be described.
If the cache control unit 400 determines to use a color buffer, a depth buffer, and an alpha buffer based on the function parameters, for example, one memory unit 100 to 130 is allocated to each of these buffers. For example, the input selector 200 performs allocation control so that the color buffer address 500, the input selector 210 selects the depth buffer address 510, and the input selector 220 selects the alpha buffer address 520. For the output selectors 300 to 320, the output selector 300 for the color buffer outputs the output of the memory unit 100, the output selector 310 for the depth buffer outputs the output of the memory unit 110, and the output for the alpha buffer. The data selector 320 controls the allocation so as to select the outputs of the memory units 120, respectively.

  By performing the allocation control in this way, the memory unit 130 is unused among the four memory units 100 to 130. In this case, the cache control unit 400 instructs a power supply unit and a clock supply unit of a graphics apparatus (not shown) to stop supplying power and clocks to the memory unit 130. As a result, power supply to the memory unit 130 and clock supply are stopped, and power consumption as the graphics device can be reduced.

  Although the memory unit 130 has been described as an unused memory unit, any memory unit may be unused. Further, as long as the allocation satisfies the condition that at least one memory unit is allocated to the buffer to be used, any allocation may be performed according to the relationship between the type of buffer to be used and the number of memory units. .

  As described above, according to the cache memory control device of the second embodiment, the cache memory control means seems to include an unused memory unit that does not cache the buffer memory data among all the memory units. Since a plurality of input selection means and output selection means are assigned, an efficient cache memory configuration can be realized according to the type of buffer used, and assignment control to the input selection means and output selection means can be realized. Only a minimum cache memory configuration can be obtained, and for example, an effect of reducing power consumption can be obtained.

1 is a configuration diagram showing a cache memory control device according to Embodiment 1 of the present invention; FIG. It is explanatory drawing which shows the 1st reconfiguration example of the cache memory control apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the 2nd reconfiguration example of the cache memory control apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the 3rd reconfiguration example of the cache memory control apparatus by Embodiment 1 of this invention.

Explanation of symbols

  100, 110, 120, 130 Memory unit, 101, 111, 121, 131 Address, 102, 112, 122, 132 Hit flag, 103, 113, 123, 133 Data, 200, 210, 220, 230 Input selector (input selection) Means), 300, 310, 320 output selector (output selection means), 301, 311, 321 hit determination unit, 302, 312, 322 data selector, 400 cache control unit (cache memory control means), 500 for color buffer Address, address for 510 depth buffer, address for 520 alpha buffer.

Claims (3)

Whether or not the cached data has been hit when the number of types of buffer memory to be used is provided and the data of the buffer memory to be used is cached and the address of the buffer memory to be used is given A plurality of memory units that output a hit flag indicating
A plurality of input selection means provided corresponding to the plurality of memory units, and giving the addresses of the buffer memories used to the corresponding memory units;
Based on a hit flag provided corresponding to the used buffer memory and output from any one of the plurality of memory units, it is determined whether or not the data in the used buffer memory has hit. An output selection means for determining;
The input selection unit is assigned so that at least one of the input selection units selects the address of the buffer memory to be used, and the output selection unit outputs the output of the memory unit that caches the data of the corresponding buffer memory. A cache memory control device comprising: cache memory control means for assigning the output selection means so as to select.   2. The cache memory control device according to claim 1, wherein the cache memory control means assigns a plurality of input selection means and output selection means so that data of any buffer memory is cached in all memory units.   The cache memory control means allocates a plurality of input selection means and output selection means so that there is an unused memory unit that does not cache data in the buffer memory among all the memory units. 2. The cache memory control device according to 1.

Images