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JP2008016534A - 貼り合わせウェーハの製造方法 - Google Patents

貼り合わせウェーハの製造方法 Download PDF

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Publication number
JP2008016534A
JP2008016534A JP2006184237A JP2006184237A JP2008016534A JP 2008016534 A JP2008016534 A JP 2008016534A JP 2006184237 A JP2006184237 A JP 2006184237A JP 2006184237 A JP2006184237 A JP 2006184237A JP 2008016534 A JP2008016534 A JP 2008016534A
Authority
JP
Japan
Prior art keywords
wafer
layer
active layer
oxygen ion
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006184237A
Other languages
English (en)
Japanese (ja)
Inventor
Nobuyuki Morimoto
信之 森本
Akihiko Endo
昭彦 遠藤
Etsuro Morita
悦郎 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Priority to JP2006184237A priority Critical patent/JP2008016534A/ja
Priority to TW096124368A priority patent/TWI355711B/zh
Priority to PCT/JP2007/063387 priority patent/WO2008004591A1/fr
Priority to US12/064,605 priority patent/US8048769B2/en
Priority to EP07768139A priority patent/EP1936664A4/fr
Priority to CNA2007800012350A priority patent/CN101356622A/zh
Publication of JP2008016534A publication Critical patent/JP2008016534A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
JP2006184237A 2006-07-04 2006-07-04 貼り合わせウェーハの製造方法 Pending JP2008016534A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2006184237A JP2008016534A (ja) 2006-07-04 2006-07-04 貼り合わせウェーハの製造方法
TW096124368A TWI355711B (en) 2006-07-04 2007-07-04 Method of producing simox wafer
PCT/JP2007/063387 WO2008004591A1 (fr) 2006-07-04 2007-07-04 Procédé de production d'une tranche liée
US12/064,605 US8048769B2 (en) 2006-07-04 2007-07-04 Method for producing bonded wafer
EP07768139A EP1936664A4 (fr) 2006-07-04 2007-07-04 Procédé de production d'une tranche liée
CNA2007800012350A CN101356622A (zh) 2006-07-04 2007-07-04 贴合晶片的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006184237A JP2008016534A (ja) 2006-07-04 2006-07-04 貼り合わせウェーハの製造方法

Publications (1)

Publication Number Publication Date
JP2008016534A true JP2008016534A (ja) 2008-01-24

Family

ID=38894558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006184237A Pending JP2008016534A (ja) 2006-07-04 2006-07-04 貼り合わせウェーハの製造方法

Country Status (6)

Country Link
US (1) US8048769B2 (fr)
EP (1) EP1936664A4 (fr)
JP (1) JP2008016534A (fr)
CN (1) CN101356622A (fr)
TW (1) TWI355711B (fr)
WO (1) WO2008004591A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2075830A2 (fr) 2007-10-11 2009-07-01 Sumco Corporation Procédé de production de plaquette fixée
JP2009289948A (ja) * 2008-05-29 2009-12-10 Sumco Corp 貼り合わせウェーハの製造方法
JP2010045148A (ja) * 2008-08-12 2010-02-25 Sumco Corp 貼り合わせウェーハの製造方法
JP2010129839A (ja) * 2008-11-28 2010-06-10 Sumco Corp 貼り合わせウェーハの製造方法
KR101032564B1 (ko) 2008-04-11 2011-05-06 가부시키가이샤 사무코 접합 웨이퍼의 제조 방법
US8003494B2 (en) 2007-09-07 2011-08-23 Sumco Corporation Method for producing a bonded wafer
KR101066315B1 (ko) * 2008-05-08 2011-09-20 가부시키가이샤 사무코 접합 웨이퍼의 제조 방법
WO2019187844A1 (fr) * 2018-03-28 2019-10-03 住友精密工業株式会社 Procédé de fabrication de dispositif mems, dispositif mems, et dispositif obturateur l'utilisant

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5261960B2 (ja) 2007-04-03 2013-08-14 株式会社Ｓｕｍｃｏ 半導体基板の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000024059A1 (fr) * 1998-10-16 2000-04-27 Shin-Etsu Handotai Co., Ltd. Procede de production de tranche soi utilisant un procede de separation d'implantation d'ions hydrogene et tranche soi produite a l'aide du procede
WO2004010505A1 (fr) * 2002-07-18 2004-01-29 Shin-Etsu Handotai Co.,Ltd. Plaquette de silicium sur isolant et son procede de production
WO2004064145A1 (fr) * 2003-01-10 2004-07-29 Shin-Etsu Handotai Co., Ltd. Procédé de production d'une plaquette soi et plaquette soi
WO2005067053A1 (fr) * 2004-01-08 2005-07-21 Sumco Corporation Procede de production d'une plaquette soi
WO2005074033A1 (fr) * 2004-01-30 2005-08-11 Sumco Corporation Procede pour la fabrication de tranches soi

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2003046993A1 (ja) * 2001-11-29 2005-04-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP4147577B2 (ja) 2002-07-18 2008-09-10 信越半導体株式会社 Ｓｏｉウェーハの製造方法
TW200428637A (en) * 2003-01-23 2004-12-16 Shinetsu Handotai Kk SOI wafer and production method thereof
JP2005340348A (ja) * 2004-05-25 2005-12-08 Sumco Corp Ｓｉｍｏｘ基板の製造方法及び該方法により得られるｓｉｍｏｘ基板
JP5168788B2 (ja) * 2006-01-23 2013-03-27 信越半導体株式会社 Ｓｏｉウエーハの製造方法
US7977221B2 (en) * 2007-10-05 2011-07-12 Sumco Corporation Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000024059A1 (fr) * 1998-10-16 2000-04-27 Shin-Etsu Handotai Co., Ltd. Procede de production de tranche soi utilisant un procede de separation d'implantation d'ions hydrogene et tranche soi produite a l'aide du procede
WO2004010505A1 (fr) * 2002-07-18 2004-01-29 Shin-Etsu Handotai Co.,Ltd. Plaquette de silicium sur isolant et son procede de production
WO2004064145A1 (fr) * 2003-01-10 2004-07-29 Shin-Etsu Handotai Co., Ltd. Procédé de production d'une plaquette soi et plaquette soi
WO2005067053A1 (fr) * 2004-01-08 2005-07-21 Sumco Corporation Procede de production d'une plaquette soi
WO2005074033A1 (fr) * 2004-01-30 2005-08-11 Sumco Corporation Procede pour la fabrication de tranches soi

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8003494B2 (en) 2007-09-07 2011-08-23 Sumco Corporation Method for producing a bonded wafer
EP2075830A2 (fr) 2007-10-11 2009-07-01 Sumco Corporation Procédé de production de plaquette fixée
KR101032564B1 (ko) 2008-04-11 2011-05-06 가부시키가이샤 사무코 접합 웨이퍼의 제조 방법
KR101066315B1 (ko) * 2008-05-08 2011-09-20 가부시키가이샤 사무코 접합 웨이퍼의 제조 방법
JP2009289948A (ja) * 2008-05-29 2009-12-10 Sumco Corp 貼り合わせウェーハの製造方法
JP2010045148A (ja) * 2008-08-12 2010-02-25 Sumco Corp 貼り合わせウェーハの製造方法
JP2010129839A (ja) * 2008-11-28 2010-06-10 Sumco Corp 貼り合わせウェーハの製造方法
WO2019187844A1 (fr) * 2018-03-28 2019-10-03 住友精密工業株式会社 Procédé de fabrication de dispositif mems, dispositif mems, et dispositif obturateur l'utilisant

Also Published As

Publication number Publication date
US8048769B2 (en) 2011-11-01
CN101356622A (zh) 2009-01-28
US20100015779A1 (en) 2010-01-21
TW200816368A (en) 2008-04-01
EP1936664A1 (fr) 2008-06-25
WO2008004591A1 (fr) 2008-01-10
TWI355711B (en) 2012-01-01
EP1936664A4 (fr) 2011-02-23

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