JP2008034856A - Method for forming fine via hole and multilayer printed circuit board using this via hole forming method - Google Patents

Abstract

Kind Code: A1 A fine via hole forming method capable of efficiently filling a conductive liquid thermosetting material in a fine via hole using a (nano) inkjet jet method, and a multilayer printed circuit board using the via hole forming method I will provide a.
A method of forming a via hole for electrically connecting wirings of respective layers, wherein a first step of processing a via hole in a hole processing material, and the via hole contains a conductive liquid thermosetting substance. A second step of filling the ink by using an ink jet ejection method, and a third step of applying heat to the ink filled in the via hole to selectively leave a conductive thermosetting substance in the via hole, In the method of forming a via hole, the operations of the second step and the third step are repeated to fill the via hole with a conductive thermosetting substance.
[Selection] Figure 4

Description

The present invention relates to a method for forming a fine via hole that can efficiently fill a fine via hole with a conductive thermosetting substance, and a multilayer printed circuit board using the method for forming the via hole.

1A to 1C are process cross-sectional views illustrating via hole formation according to the prior art.
As shown in FIG. 1A, a conventional via hole forming method forms a metal film by depositing a conductive metal such as aluminum (Al) on a semiconductor substrate 10 by a sputtering method. The metal wiring 12 is formed by removing by a photolithography process. At this time, a transistor (Transistor) or the like is manufactured in the lower portion of the semiconductor substrate 10, and the transistor is covered with an oxide film.

Further, a TiN film 13 serving as an antireflection layer for reducing light reflection is formed on the metal wiring 12 at the time of patterning the photosensitive film in the subsequent process.
Next, as shown in FIG. 1B, an insulating material such as silicon oxide is deposited on the resultant product so as to cover the metal wiring 12 by chemical vapor deposition (CVD).
4 is formed.

  Next, a photosensitive resin is applied on the interlayer insulating film 14 and a photosensitive resin layer is applied. The photosensitive resin layer is exposed and developed to expose a portion corresponding to the metal wiring 12. A photosensitive film pattern 11 made of the cured product is formed.

Thereafter, as shown in FIG. 1C, using the photosensitive film pattern as a mask, the interlayer insulating film 14 is removed by dry etching to form a via hole 18 exposing the metal wiring 12.
Next, the via hole will be described in detail.

With the diversification and miniaturization of functions of electronic components, interconnect traces (Trace) are further demanded as circuits, which makes the structure of a printed circuit board (PCB) very complicated.
As an example of a PCB having a complicated configuration, it is necessary to make a PCB that has been driven by a single layer in the past to be a multilayer, and as the PCB becomes multilayered, each layer is electrically connected. It is becoming necessary to connect to each other. Here, a perforated plating barrel interconnecting these layers is called a “Via”.

  Further, with the diversification of functions and the miniaturization of the device, the via size is gradually reduced, and the number of vias to be formed is increased. Such a new small via is called a micro via. Furthermore, in addition to the vias penetrating the PCB, it is necessary to form a via hole for electrically connecting a part of the multilayered PCB. In this way, the via hole that does not penetrate the PCB This is called Blind Via. That is, a blind via is a via that does not completely penetrate the multilayer printed circuit board and stops at a predetermined depth.

Via holes in the printed circuit board (PCB) are formed by exposing copper (Cu) interconnect lands on individual layers by a drill method.
Thereafter, the printed circuit board (PCB) passes through the plating solution, and the various layers are connected by plating formed on the inner surface of the through hole (Through Hole) or attached copper.

Such a via hole needs to be filled flat for buffering action and multilayering in preparation for impact.
Conventionally, the hole is filled with resin after copper plating and the hole is filled with silver or copper paste to ensure conductivity and bump function.

However, since the size of the substrate is reduced and the line width and the size of holes (including via holes) are reduced in order to realize multiple functions on the substrate, the voids of the filler filled in the via holes are minimized. There is a strong need for a new method of filling via holes.

  An object of the present invention is to form a fine via hole capable of efficiently filling a conductive via-hardening material in a fine via hole using a (nano) inkjet jet method, and a multilayer printed circuit using the via hole forming method It is to provide a substrate.

The method for forming a via hole according to the present invention includes:
A method of forming a via hole for electrically connecting the wiring of each layer,
A first step of processing a via hole in a hole processing material;
A second step of filling the via hole with an ink containing a conductive thermosetting substance by adopting an inkjet ejection method;
A third step of applying heat to the ink filled in the via hole to selectively leave a conductive thermosetting substance in the via hole;
The operations of the second step and the third step are repeated to fill the via hole with a conductive thermosetting substance.

  In the present invention, as a method of filling the via hole with a conductive thermosetting substance that is a conductive substance, ink containing nano-sized silver particles is filled by adopting an inkjet jet method.

  The ink used in the present invention contains nano-sized silver powder, a solvent for ejecting the nano-sized silver powder by an ink jet ejecting system, and an organic adhesive, a dispersant, and the like as necessary.

  In order to selectively leave the conductive thermosetting substance involved in the conductivity by injecting the ink containing the nano silver powder in the via hole as described above, in the present invention, after performing the inkjet injection, 140 to 180 Heat for 5 to 15 minutes at a temperature in the range of ° C to evaporate and remove the solvent as a vaporizing component, and selectively leave nano-sized silver powder as a conductive thermosetting substance in the via hole. To do.

The amount of silver nano-powder in the ink used for inkjet ejection as described above is usually in the range of 30 to 60 parts by weight, with the remainder being components such as a solvent.
As described above, the amount of the silver nanopowder contained in the ink (conductive liquid curable substance) is 30 to 60 parts by weight as described above, and the remainder is mainly a vaporized component such as a solvent. By repeating the second step and the third step of removing the vaporized component by ejecting ink containing nanoparticles, the via hole is filled with silver nanoparticles as a conductive curable substance.

  When the ink (conductive liquid curable material) is repeatedly ejected into the via hole by ink jet ejection and dried as described above, the upper surface may not be flush with the upper surface of the adjacent wiring. .

  Therefore, in the present invention, after the step of filling the via hole with the conductive thermosetting substance, it is preferable to perform level adjustment with the wiring in the vicinity of the via hole by performing a planarization operation on the upper surface.

  In addition, the present invention is characterized by providing a multilayer printed circuit board manufactured by using PCB as a method for forming a via hole formed as described above.

  According to the present invention, by providing a method for forming a via hole by filling a fine via hole with a conductive liquid thermosetting substance using a nano ink jet injection method and removing the vaporizable substance, the hole is formed. Even if it is fine, the hole can be minimized by tightly filling the hole with the conductive thermosetting substance as a filler. Furthermore, since the conductive substance filled in the via hole is a cured body of silver nanoparticles, it exhibits good conductivity.

  Thereby, this invention can fully absorb the impact which acts from upper part, and can prevent the crack of a printed circuit board (PCB).

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 2 is a process diagram illustrating formation of a fine via hole according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view illustrating an ink filling process using an inkjet ejector in the fine via hole according to an embodiment of the present invention. It is. FIGS. 5A to 5F are process cross-sectional views showing formation of fine via holes according to an embodiment of the present invention, and show an omission process between the later-described FIG. 3C process and FIG. 3D process.

Referring to the drawing, in order to form a fine via hole according to the present invention, first, as a first step, a via hole is processed in the hole processing material 100 (FIG. 2: S101).
Here, the hole processing material 100 is a material in which the via hole is formed, such as the circuit pattern 140 and the insulating layers 110 and 160 in FIG. 5A.

In other words, in the first step of forming the via hole, the via hole is processed in the single layer base substrate 150 stacked in multiple layers.
The via hole is usually formed using a mechanical drill. However, since fine processing is required when forming a fine circuit pattern, a yttrium aluminum garnet (YAG) laser or a CO ₂ laser may be used. preferable. The YAG laser is a laser beam having a wavelength capable of processing both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser beam having a wavelength suitable mainly for processing the insulating layer.

As described above, after processing the via hole in the hole processing material, in the present invention, the second step (FIG. 2: S
102) The via hole is filled with ink (conductive liquid thermosetting substance) (see FIG. 5A).

For the ink filling, an ink jet ejection method using the ink jet ejecting apparatus 1 shown in FIG. 4, more preferably a nano ink jet ejecting method is adopted.
That is, inkjet ejection using a nano inkjet ejection apparatus including a printer head described in a patent filed by the present applicant (registered patent number: 10-0510777, title of invention: nano inkjet printer head and manufacturing method thereof) It is preferable to adopt a method.

The ink contains silver (Ag) nano powder (Nano Powder) that is cured to become a conductive material, usually a solvent, and, if necessary, an organic adhesive, a dispersant, a resin, and the like.
The ink used in the present invention preferably contains silver nanopowder in an amount in the range of 30 to 60 parts by weight.

  The organic adhesive, which may be contained in the ink, sprays the ink onto the substrate, evaporates the solvent by applying heat, and when the silver nanopowder remains, the silver nanopowder is stable on the substrate. It adheres to the film and plays the role of exerting the desired performance under any conditions (for example, cracks occur when the substrate is heated). The solvent contains silver nanopowder and occupies most of the ink. Currently used solvents include water and ethanol. The solvent is used to make silver nanopowder liquid. At this time, the liquid ink (conductive liquid thermosetting substance = silver paste) preferably has a low viscosity so that it can be ejected by a nano ink jet printer.

The conductive liquid thermosetting substance means nano-sized silver particles contained in a solvent, and the silver particles are usually 20 nm (20 × 10 ⁻⁹ m) or less. It has a diameter. These fine silver particles tend to agglomerate with each other in a solvent and become large, and such aggregates may become a problem during jetting. Dispersion can be achieved.

In the present invention, as described above, the ink is filled in the via hole in the second step, preferably by nano inkjet ejection, and then heat is applied to the ink in the via hole filled in the third step (FIG. 2: S103).

By heating in this manner, the solvent contained in the ink evaporates, and mainly nano-sized silver particles that are the conductive thermosetting substance in the conductive liquid thermosetting substance remain. Here, a part of the remaining silver nanopowder is fused to the wall while melting in heat, but most remains on the bottom. (See Figure 5B)
Although the heating temperature at this time changes with solvents to be used, it is normally set in the range of 140-180 degreeC. The heating time under such temperature conditions is usually 5 to 15 minutes.

In the present invention, the operation of filling the via hole with the conductive thermosetting substance is repeated by repeating the second step and the third step of filling and drying the conductive liquid thermosetting substance in the via hole as described above. However, since the entire inside of the via hole cannot be filled with the conductive thermosetting material in one operation, the second step (FIG. 2: S102) and the third step (FIG. 2: S103) are repeated, and the inside of the via hole is repeated. Is filled with a conductive thermosetting substance (reference numeral 180 in FIG. 3D below). (See FIGS. 5C to 5F)
In the present invention, if the solvent is removed after the conductive liquid thermosetting material is filled in the via hole as described above, the upper surface of the conductive thermosetting material may not be flush with the adjacent wiring. In the present invention, it is preferable to perform a flattening process so that the upper surface of the conductive thermosetting material is flat (FIG. 2: S104).

Hereinafter, a manufacturing process of a multilayer printed circuit board according to an embodiment of the present invention will be described in detail with reference to FIGS.
First, as shown in FIG. 3A, a circuit pattern is formed on the insulating layer.

  That is, a hole having a predetermined shape (eg, a trapezoid whose lower side is shorter than the upper side) is formed in the insulating layer, and the hole is insulated while being filled with a conductive liquid thermosetting material (eg, conductive liquid photosensitive material). After application on layer 110, the conductive liquid thermosetting material is cured. Thereafter, an artwork film on which a circuit pattern is formed or a glass mask such as a glass mask on which a circuit pattern is formed by coating chromium on the surface of the conductive thermosetting material, and performing exposure and phenomenon processes. The single-layer base substrate 150 on which the circuit pattern 140 is formed is completed.

After the base substrate 150 is completed as described above, the base substrate 150 is stacked according to a desired number of layers as shown in FIG. 3B, and then heated and pressed to complete a multilayer printed circuit board.
After the multilayer printed circuit board is formed by heating and pressurizing as described above, a via hole 170 is formed as shown in FIG. 3C, and then a desmear process is performed.

  The via hole 170 is for electrically connecting the layers and is formed using a mechanical drill. Various contaminants and foreign matters generated during drilling are removed through a desmear process.

  Thereafter, as described above, the conductive thermosetting material 180 contained in the ink is filled in the via hole 170 in the process as shown in FIGS. 2 and 5 to finally complete the multilayer printed circuit board.

  Although the invention has been described with reference to the preferred embodiments, it is intended to be illustrative only and should not be construed as limiting the scope of the invention. Moreover, those skilled in the art will understand that various modifications and changes can be made without departing from the spirit and scope of the present invention described in the claims.

FIG. 1A is a process cross-sectional view illustrating via hole formation according to the prior art. FIG. 1B is a process cross-sectional view subsequent to the process of FIG. 1A. FIG. 1C is a process cross-sectional view subsequent to the process of FIG. 1B. FIG. 5 is a process diagram showing formation of a fine via hole according to an embodiment of the present invention. FIG. 3A is a process cross-sectional view of a multilayer printed circuit board according to an embodiment of the present invention. FIG. 3B is a process cross-sectional view subsequent to the process of FIG. 3A. 3C is a process cross-sectional view subsequent to the process of FIG. 3B. FIG. 3D is a process cross-sectional view subsequent to the process of FIG. 3C. FIG. 5 is a cross-sectional view illustrating a process of filling ink using an inkjet ejector in a fine via hole according to an embodiment of the present invention. FIG. 5A is a process cross-sectional view illustrating formation of a fine via hole according to an embodiment of the present invention. FIG. 5B is a process cross-sectional view subsequent to the process of FIG. 5A. FIG. 5C is a process cross-sectional view subsequent to the process of FIG. 5B. FIG. 5D is a process cross-sectional view subsequent to the process of FIG. 5C. FIG. 5E is a process cross-sectional view subsequent to the process in FIG. 5D. FIG. 5F is a process cross-sectional view subsequent to the process in FIG. 5E.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Inkjet injection apparatus 10 ... Semiconductor substrate 11 ... Photosensitive film pattern 12 ... Metal wiring 13 ... TiN film 14 ... Interlayer insulation film 18 ... -Via hole 100 ... Hole processed material 110, 160 ... Insulating layer 140 ... Circuit pattern 150 ... Single layer base substrate 170 ... Via hole 180 ... Conductive thermosetting substance

Claims (6)

A method of forming a via hole for electrically connecting the wiring of each layer,
A first step of processing a via hole in a hole processing material;
A second step of filling the via hole with an ink containing a conductive thermosetting substance by adopting an inkjet ejection method;
A third step of applying heat to the ink filled in the via hole to selectively leave a conductive thermosetting substance in the via hole;
A method of forming a via hole, wherein the operations of the second step and the third step are repeated to fill the via hole with a conductive thermosetting substance.   The method for forming a via hole according to claim 1, wherein the ink is an ink jettable liquid containing silver nanopowder.   2. The method of forming a via hole according to claim 1, wherein the conductive thermosetting substance is selectively left in the via hole by heating at a temperature of 140 to 180 [deg.] C. for 5 to 15 minutes.   The method for forming a via hole according to claim 1, wherein the ink contains silver nanopowder in an amount within a range of 30 to 60 parts by weight.   2. The method of forming a via hole according to claim 1, wherein after the fourth step of filling the via hole with a conductive thermosetting substance, a process of flattening the upper surface of the via hole is performed. 3.   A multilayer printed circuit board manufactured by using the method for forming a via hole according to claim 1.

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