JP2008146796A - Nonvolatile semiconductor memory device - Google Patents

Abstract

[PROBLEMS] To suppress a decrease in product yield due to the presence of defective cells in a nonvolatile semiconductor memory device, improve reliability, and suppress an increase in circuit scale.
Effective data is stored in the lower 4 bits of an e-fuse block 22 composed of serially connected 7-bit memory cells 10 (100 to 106), and code data is stored in the upper 3 bits. The first selector circuit 41 has two input terminals IN0 and IN1, and an input signal SI from the outside is input to the former, and an output signal from the error correction circuit 44 is input to the latter. In the code generation / syndrome generation circuit 42, the exclusive OR circuits 425 and 426 execute exclusive OR operations necessary for code data generation or syndrome generation. The other circuits 421-424 are responsible for switching the functions (code data generation, syndrome generation) of the exclusive OR circuits 425 and 426.
[Selection] Figure 3

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  In a semiconductor integrated circuit composed of a memory such as a DRAM or SRAM, a logic circuit, etc., it is necessary to store initial setting information including repair information of defective memory cells, circuit setting information, etc. in a nonvolatile manner and execute initial setting. In order to store such information, a nonvolatile semiconductor memory device using a fuse element or the like is mounted (for example, see Patent Document 1). As one of such nonvolatile semiconductor memory devices, an insulating film destructive semiconductor memory element (hereinafter referred to as “an insulating film breakdown semiconductor memory element”) that stores information by applying a high voltage exceeding the maximum rating to a semiconductor element having a MOS structure and destroying the insulating film. A nonvolatile semiconductor memory device using an e-fuse element has been proposed.

  The storage of the initial setting information in the nonvolatile semiconductor memory device is executed at a test stage in the manufacturing process, and it is required to maintain the state for a long time after product shipment. Depending on the manufacturing conditions and programming conditions of the fuse, there is a possibility that the data may be destroyed due to a change with time after the programming, and the requirement for the reliability of the element is severe.

Further, such a nonvolatile semiconductor memory device has a problem that it is difficult to remedy defects depending on the specifications of the product, and if even one bit is defective, it may become a fatal defect for the product.
JP 2005-116003 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device that can suppress a decrease in product yield due to the presence of defective cells, increase reliability, and suppress an increase in circuit scale.

  A nonvolatile semiconductor device according to an aspect of the present invention includes a plurality of memory cells including a semiconductor memory element that stores data in a nonvolatile manner and a data register that stores data read from the semiconductor memory element, A data register is serially connected, and is provided with a shift register that sequentially transfers data to the outside, stores the data transferred from the outside, and stores the data in the semiconductor memory element. While storing m-bit effective data in the semiconductor memory element, n-bit code data for executing error correction of effective data is stored in the n-bit semiconductor memory element corresponding to the preceding stage of the shift register as a whole ( m + n, m) A memory cell array capable of storing cyclic code data, and upstream of the preceding stage A first selector circuit that selectively inputs either the externally input data or the output data of the subsequent stage part to the head of the preceding stage part, and is disposed between the preceding stage part and the subsequent stage part A second selector circuit for selectively inputting either the output data of the rear part or the output data of the rear stage part to the head of the rear stage part, the output signal of the rear stage part being inputted, and the effective data and the code data An error correction circuit that performs error correction of the effective data by inputting a syndrome generated based on the data, and an exclusive OR circuit serially connected to the data register included in the front stage, The effective data stored in the unit is input via the first selector circuit to generate code data for correcting an error in the effective data, and And the code data stored in the preceding stage and the effective data stored in the succeeding stage are input via the first selector circuit to generate a syndrome, and the syndrome is replaced with the code data. A code data / syndrome generation circuit to be stored in the preceding stage is provided.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can suppress a decrease in product yield due to the presence of defective cells, increase reliability, and suppress an increase in circuit scale.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  In the following embodiments, an example in which a so-called e-fuse element is used as a semiconductor memory element of a nonvolatile semiconductor memory device will be described. However, the present invention is not limited to this, and a variety of laser fuse elements, mask ROMs, etc. The present invention can be applied to a nonvolatile memory cell.

  First, an example of a nonvolatile semiconductor memory device using an e-fuse element will be described with reference to the drawings, and then a characteristic part of an embodiment of the present invention will be described.

  First, an example of a nonvolatile semiconductor memory device using an e-fuse element will be described with reference to FIGS. A configuration example of the e-fuse memory cell 10 used in this example will be described with reference to FIG. The memory cell 10 includes an e-fuse element 1 (semiconductor memory element), a barrier transistor 2, a selection transistor 3, a sense amplifier 4, and data registers FFR and FFW.

  The e-fuse element 1 is composed of a p-channel MOS transistor to which a substrate, a source, and a drain are short-circuited and a write voltage VBP is applied. The gate is connected to the drain of an n-channel MOS transistor constituting the barrier transistor 2.

  The barrier transistor 2 is provided to alleviate the influence of a high voltage during programming on peripheral circuits such as the sense amplifier 4 and the voltage VBT is applied to the gate during writing. Since the voltage VBT is also related to the current control at the time of writing, the value of the voltage VBT−Vt (Vt is the threshold voltage of the barrier transistor 2) is set to a value as large as possible without causing a problem even when applied to the sense amplifier. It is desirable to set.

  The source of the barrier transistor 2 is connected to the drain of an n-channel MOS transistor constituting the selection transistor 3, and the source is grounded.

  The sense amplifier 4 has an input terminal connected to a connection node between the barrier transistor 2 and the selection transistor 3, and detects and amplifies a signal at the connection node.

  The signal amplified by the sense amplifier 4 is stored as data in the data register FFR. A plurality of memory cells 10 are arranged in the X direction shown in FIG. 1, and a plurality of data registers FFR are connected in series in the X direction to form a shift register. Therefore, the data stored in the memory cell 10 is held in the data register FFR, then sequentially transferred through the shift register according to the clock signal, and output to the outside.

  Further, the data register FFW is used for taking in data to be written to the e-fuse element 1 from the outside and temporarily holding it. If the data held in the data register FFW is “1”, the selection transistor 3 is turned on, and the barrier transistor 2 is also turned on, whereby the e-fuse element 1 is destroyed and data “1” is written. On the other hand, if the data held in the data register FFW is “0”, the selection transistor 3 is turned OFF, whereby the e-fuse element 1 is not destroyed, and the data held in the memory cell 10 is “0”. To be left.

  FIG. 2 shows a configuration example of a fuse macro 20 formed by integrating a plurality of the memory cells 10 of FIG. 1 according to this example. The fuse macro 20 shown in FIG. 2 includes a voltage generation circuit 21, an e-fuse block 22, and a control circuit 23.

  The e-fuse block 22 includes, for example, 64 memory cells 10 and a control circuit 22B. In this example, a plurality of e-fuse blocks 22 are connected in series to form the fuse macro 20. In the example shown in FIG. 2, a fuse macro of 64 × 16 = 1024 bits is configured by connecting 16 stages of e-fuse blocks 22 in series. This is merely an example, and the number of memory cells in the e-fuse block 22 and the total number of memory cells can be arbitrarily changed as necessary.

  The data registers FFW and FFR included in the 64 memory cells 10 are connected in series to form a shift register, and the held data is shifted bit by bit to the output terminal side according to the clock pulse CLK, and the least significant bit. Can be output from the output terminal SO.

  The voltage generation circuit 21 supplies the e-fuse block 22 with voltages (for example, VBP, VBT) necessary for writing, reading, and the like.

  The control circuit 23 is configured to serially input write data SI in synchronization with the clock signal CLK, and to serially output data from the data output terminal SO when reading. In addition, various control signals are input. The input data is sequentially transferred from the head e-fuse block 22 and written to each memory cell 10.

  Heretofore, an example of a nonvolatile semiconductor device using an e-fuse element has been shown. Such a nonvolatile semiconductor device is often used for storing information for relieving a defective element of another semiconductor memory device such as a DRAM or SRAM, various circuit setting information, chip identification information, and the like. . That is, a program is executed at the test stage in the manufacturing process, and it is required to maintain the state for a long time after product shipment. Depending on the manufacturing conditions and programming conditions of the fuse, there is no possibility that the data will be destroyed due to a change with time after the programming, so that the requirements regarding the reliability of the element are severe.

  In addition, the nonvolatile semiconductor memory device using such an e-fuse element is used in such a manner that the data stored in the e-fuse element is transferred almost automatically when the power is turned on in the memory device. If there is a defective element, it is very difficult to relieve it, and if even one bit is defective, it can be fatal to the product. Therefore, there is a possibility that the yield of the nonvolatile semiconductor memory device using such an e-fuse element is directly connected to the yield of the entire memory device. Therefore, in the present embodiment, this problem is solved by adding an error correction function as described below to the nonvolatile semiconductor memory device having a format for reading data by the shift register as described above. Further, an increase in circuit scale due to the addition of the error correction function is minimized.

[First Embodiment]
Next, the nonvolatile semiconductor memory device 1 according to the first embodiment having an error correction function will be described with reference to FIG. The same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted below. In FIG. 3, only the data register FFR is illustrated among the components of the memory cell 10, and the other components (FIG. 1) are not shown.

  The nonvolatile semiconductor memory device of this embodiment is an e-fuse macro composed of serially connected 7-bit memory cells 10 (100 to 106), and uses (7, 4) cyclic codes as error correction codes. One-bit correction is performed. The 7-bit memory cell 10 forms an e-fuse block 22. The use of the 7-bit, (7, 4) cyclic code is merely an example, and in general, the (m + n) -bit e-fuse block that can store (m + n, m) cyclic code data is also used. The invention is applicable.

  In the nonvolatile semiconductor memory device 1 of this embodiment, effective data that is actually used externally is stored in the lower 4 bits (memory cells 100 to 103) of the serially connected 7-bit memory cell 10, and the upper 3 Code data used for error correction of the effective data can be stored in bits (memory cells 104 to 106). When the syndrome is generated, the syndrome is stored in the upper 3 bits of the memory cells 104 to 106 instead of the code data, and is used for error correction.

  In order to execute such a function, the nonvolatile semiconductor memory device 1 of this embodiment includes a first selector circuit 41, a code generation / syndrome generation circuit 42, a second selector circuit 43, an error, as shown in FIG. A correction circuit 44 and a control circuit 23 are provided. Although details of these circuits 41 to 45 will be described later, the configuration shown in FIG. 3 eliminates the need to separately provide a special storage element for storing syndromes, thereby reducing the circuit scale.

  The first selector circuit 41 is provided on the upstream side of the e-fuse block 22 and has a function of switching data input to the e-fuse block 22 based on a control signal SL1 output from the control circuit 23. Specifically, the first selector circuit 41 has two input terminals IN0 and IN1, and an input signal SI from the outside is input to the former and an output signal from the error correction circuit 44 is input to the latter. Which signal is selected and input is determined by the control signal SL1 output from the control circuit 23.

  The code generation / syndrome generation circuit 42 includes a logic gate 421, an inverter 422, a logic gate 423, an inverter 424, an exclusive OR circuit 425, and an exclusive OR circuit 426. The exclusive OR circuits 425 and 426 execute exclusive OR operations necessary for code data generation or syndrome generation, and the others are functions of the exclusive OR circuits 425 and 426 (code data generation and syndrome generation). I am in charge of switching.

  The logic gate 421 receives the output signal of the memory cell 104 and the control signal Sig1 from the control circuit 23, and outputs an inverted value (negative value) of the logical product of these input signals. The inverter 422 receives the output signal of the logic gate 421 and outputs its inverted signal.

  The logic gate 423 receives the control signal Sig1 and the output signal of the exclusive OR circuit 425, and outputs an inverted value (negative value) of the logical product of these input signals. The inverter 424 receives the output signal of the logic gate 423 and outputs its inverted signal.

  The exclusive OR circuit 425 is serially connected between the output terminal O of the first selector circuit 41 and the memory cell 106 of the most significant bit. The output signal of the inverter 422 is input to one input terminal of the exclusive OR circuit 425, and the output signal from the output terminal O of the first selector circuit 41 is input to the other input terminal. The output signal of the exclusive OR circuit 425 is also connected to one input terminal of the logic gate 423 as described above.

  The exclusive OR circuit 426 is serially connected between the memory cell 106 of the most significant bit and the memory cell 105 one level lower. That is, one input terminal of the exclusive OR circuit 426 is connected to the memory cell 106, and the other input terminal is connected to the output terminal of the inverter 424. The output terminal of the exclusive OR circuit 426 is connected to the memory cell 105.

  When the control signal Sig1 is “L” (VSS), the exclusive OR circuit 425 functions to simply pass the output signal of the first selector circuit 41. The exclusive OR circuit 426 functions to simply pass the output signal of the memory cell 106.

  On the other hand, when the control signal Sig1 is “H” (VDD), the exclusive OR circuits 425 and 426 execute an exclusive OR operation necessary for code data generation or syndrome generation.

  The second selector circuit 43 is serially connected between the upper stage (memory cells 104 to 106) and the rear stage (memory cells 100 to 103) constituting the e-fuse block 22, and is output from the control circuit 23. Based on the signal SL2, it has a function of switching data input to the subsequent stage of the e-fuse block 22. Specifically, the second selector circuit 43 has three input terminals IN0, IN1, and IN2. An input signal SI from the outside can be input to the input terminal IN0, an output signal from the upper stage (memory cell 104) can be input to the input terminal IN1, and an output signal from the error correction circuit 44 can be input to the input terminal IN2. Which signal is selected and input is determined by the control signal SL2 output from the control circuit 23.

  The error correction circuit 44 includes a logic gate 441, a logic gate 442, and an exclusive OR circuit 443. The logic gate 441 receives the inverted value of the logical product of the latch data of the data register FFR6 of the memory cell 106, the inverted data of the latch data of the data register FFR5 of the memory cell 105, and the inverted data of the latch data of the data register FFR4 of the memory cell 104. Output.

  The logic gate 442 receives the output signal of the logic gate 441 at one input terminal and the control signal Sig2 from the control circuit 23 at the other, and outputs an inverted value of the logical sum of both input signals.

  The exclusive OR circuit 443 outputs an exclusive OR signal of the output signal of the memory cell 100 and the output signal of the logic gate 442. When the control signal Sig2 is “H” (VDD), the output of the logic gate 442 is fixed to “L”, whereby the error correction circuit 44 does not perform error correction, but simply outputs from the e-fuse block 22. It functions to pass the output signal. When the control signal Sig2 is set to “L” (VSS), error correction of effective data stored in the memory cells 100 to 103 (lower part) based on the syndrome stored in the upper part of the e-fuse block 22 Is executed.

Next, the operation of the nonvolatile semiconductor memory device of this embodiment will be described. (1) Transfer of external data for data writing, (2) Code data generation / writing, (3) Syndrome generation, (4) Error correction and data transfer to the outside will be described in this order.
(1) Transfer of external data (input signal from outside) for data writing When effective data and code data are written in the e-fuse block 22, for example, as shown in FIG. , SL2 is switched, and an external input signal SI is input from the input terminal IN0 of the first selector circuit 41, and an output signal of the memory cell 104 is input from the input terminal IN1 of the second selector circuit 43. Further, the control signal Sig1 is set to “L” (VSS) to stop the operation of the code data / syndrome generation circuit 42, and the control signal Sig2 is set to “H” (VDD) to operate the error correction circuit 44. Stop. In this way, the effective data is stored in the data registers FFW0 to 3 of the memory cells 100 to 103 (lower part).

An external input signal SI may be input from the input terminal IN0 of the second selector circuit 43. In this case, it is preferable that the second selector circuit 41 does not output a signal (outputs the ground potential VSS).
(2) Code data generation / write Next, code data for error correction of the effective data written in the memory cells 100 to 103 is generated, and after generation, the above-described effective data (memory cells 100 to 103 (lower part) are generated. ) And the code data stored in the e-fuse element 1 will be described with reference to FIG.

  In this case, the control signal Sig 1 is set to “H” (VDD) to set the code data / syndrome generation circuit 42 to the operating state, and the control signal Sig 2 is set to “H” (VDD) to set the error correction circuit 44. Keep the operation stopped. Further, the input terminal IN1 of the first selector circuit 41 is selected by the control signal SL1, and the output signal of the memory cell 100 (the lowermost memory cell of the e-fuse block 22) is sent via the error correction circuit 44 (stopped state). The code data / syndrome generation circuit 42 can be input.

  In addition, the input terminal IN2 of the second selector circuit 43 is selected by the control signal SL2, and similarly, the output signal of the memory cell 100 can be input to the memory cell 103 via the error correction circuit 44 (stopped state). . In other words, the effective data written in the memory cells 100 to 103 can be transferred to the code data / syndrome generation circuit 42 by the first selector circuit 41, and the lower part of the e-fuse block 22 by the second selector circuit 43. The memory cells 100 to 103 can be circulated.

  In this state, when four pulses of the clock signal CLK are input and data transfer of 4 bits is performed, the effective data of 4 bits stored in the lower part (memory cells 100 to 103) of the e-fuse block 22 is encoded data. / Syndrome generation circuit 42, and 3-bit code data is generated and stored in data registers FFW4-6 of memory cells 104-106.

  On the other hand, in the lower part of the e-fuse block 22 (memory cells 100 to 103), the second selector circuit 43 makes a cycle of 4-bit effective data and returns to the original data registers FFW0 to FFW3.

Effective data and code data are stored in the data registers FFW0 to FFW6 by the procedures (1) and (2). Thereafter, these data are written in the e-fuse element 1 by a known method.
(3) Syndrome Generation Next, a procedure for generating a syndrome based on the above effective data and code data will be described with reference to FIG. First, effective data and code data stored in the e-fuse element 1 are read out and stored in the data registers FFR0 to FFR6.

  Next, the control signal Sig 1 is set to “L” (VSS), the code data / syndrome generation circuit 42 is set to the stop state, and the control signal Sig 2 is set to “H” (VDD), so that the error correction circuit 44 Keep the operation stopped. The first selector circuit 41 selects the input terminal IN1 and the second selector circuit 43 selects the input terminal IN1 based on the control signals SL1 and SL2. In this state, in order to generate a syndrome, the clock signal CLK is output for three pulses, and the data for three bits is circulated in the data registers FFR0 to FFR6.

Next, the control signal Sig1 is switched from “L” to “H”, the code data / syndrome generation circuit 42 is switched to the operating state, and then four pulses of the clock signal CLK are output, and 4 in the data registers FFR0-6. Transfer data for bits. As a result, the syndrome is stored in the upper 3 bits of the e-fuse block 22 instead of the code data.
(4) Error correction and external data transfer Next, error correction of effective data stored in the data registers FFR0 to FFR3 is executed based on the syndromes stored in the data registers FFR4 to FFR6, and after error correction A procedure for transferring the effective data to the outside will be described with reference to FIG. At this time, the first selector circuit 41 is set so that neither the input terminal IN0 nor IN1 is selected and the ground potential VSS is output from the output terminal. In the second selector circuit 42, the input terminal IN2 is selected, and effective data can be circulated in the memory cells 100 to 103.

  Further, the control signal Sig1 is set to “H” (VDD), and the control signal Sig2 is set to “L”. As a result, the code data / syndrome generation circuit 42 operates and cycles the syndrome data stored in the data registers FFR4 to FFR6 according to the clock signal CLK. Further, the error correction circuit 44 operates, and effective data that is circulated bit by bit in the exclusive OR circuit 443 in accordance with the clock signal CLK and output data of the logic gate 441 according to the input syndrome data. Output exclusive OR. The output data is effective data after error correction. The effective data after error correction is circulated in the memory cells 100 to 103 by the second selector circuit 43 and a 4-bit clock signal CLK is input. The effective data after error correction is output to the outside as output data SO.

As described above, in the present embodiment, by introducing the above-described circuits 41 to 44 to the e-fuse block 22, it is possible to perform error correction, whereby a defective cell is 1 bit out of 7 bits. Even if it exists, the error can be corrected and output. Further, the generated syndrome is stored in a shift register constituting the e-fuse block 22 instead of the code data, and no special storage unit is required. Therefore, according to this embodiment, a decrease in product yield due to the presence of defective cells can be suppressed, reliability can be improved, and an increase in circuit scale can be suppressed.
[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG.

  The nonvolatile semiconductor memory device of this embodiment is configured by connecting two stages of nonvolatile semiconductor memory blocks 1-1 and 1-2 including the 7-bit e-fuse block 22 of the first embodiment in series. ing. Others are the same as those in the first embodiment. Each block 1-i includes selector circuits 41 and 43, a code data / syndrome generation circuit 42, and an error correction circuit 44 as in the first embodiment, and code data generation and syndrome generation for each block. And error correction.

  The output terminal of the upper block 1-1 is connected to the input terminals IN0 of the two selector circuits 41 and 43 of the lower block 1-2. The error-corrected effective data output from the upper block 1-1 can be transferred to the second selector circuit 43 of the lower block 1-2. In this case, the control signal sig2 is set to “H” (VDD) in the lower block 1-2 at the timing when the effective data before error correction is input to the exclusive OR circuit 443 in the upper block 1-1. Thus, the effective data after error correction of the upper block 1-1 can be output. Alternatively, data transfer may be executed by returning the error-corrected data to the original data register and then setting the control signal Sig2 of the lower block 1-2 to “H”.

Even if the degree of integration of the e-fuse type memory macro is increased by executing each control related to error correction in parallel in units of blocks as in this embodiment, it is necessary for the scale and control of the control circuit. Time increase can be suppressed.
[Other]
Although the embodiments of the invention have been described above, the present invention is not limited to these embodiments, and various modifications and additions can be made without departing from the spirit of the invention. For example, in the above embodiment, an example in which (7, 4) cyclic code is stored in the 7-bit memory cell 10 has been described. However, as described above, the present invention can store (m + n) cyclic code data. The present invention is also applicable to a semiconductor memory device having an (m + n) -bit e-fuse block. At this time, the first selector circuit 41 is similarly placed at the head of the e-fuse block, and the second selector circuit 43 is similarly similarly used to store the upper stage portion in which the code data or syndrome is stored and the effective data. It can arrange | position to the boundary with a lower step part.

An example of a nonvolatile semiconductor memory device using an e-fuse element is described. An example of a nonvolatile semiconductor memory device using an e-fuse element is described. 1 shows a nonvolatile semiconductor memory device according to a first embodiment of the present invention. The operation of the nonvolatile semiconductor memory device according to the first embodiment will be described. The operation of the nonvolatile semiconductor memory device according to the first embodiment will be described. The operation of the nonvolatile semiconductor memory device according to the first embodiment will be described. The operation of the nonvolatile semiconductor memory device according to the first embodiment will be described. 4 shows a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... e-fuse element, 2 ... Barrier transistor, 3 ... Selection transistor, 4 ... Sense amplifier, FFR, FFW ... Data register, 10 ... Memory cell, 20 ... The fuse macro, 22 ... e-fuse block, 23 ... control circuit, 41 ... first selector circuit, 42 ... code data / syndrome generation circuit, 43 ... second selector circuit, 44 ... Error correction circuit.

Claims (5)

A plurality of memory cells including a semiconductor memory element for storing data in a non-volatile manner and a data register for storing data read from the semiconductor memory element are arranged, and the data registers are serially connected. A shift register for transferring and storing data transferred from the outside and storing the data in the semiconductor memory element, and storing m-bit effective data in an m-bit semiconductor memory element corresponding to a subsequent stage of the shift register. Memory in which n-bit code data for executing error correction of effective data is stored in an n-bit semiconductor memory element corresponding to the preceding stage of the shift register, and (m + n, m) cyclic code data can be stored as a whole A cell array;
A first selector circuit that is arranged on the upstream side of the front stage part and selectively inputs either external input data or output data of the rear stage part at the head of the front stage part;
A second selector circuit that is arranged between the preceding stage and the succeeding part and selectively inputs either the output data of the preceding stage or the output data of the succeeding part to the head of the succeeding part;
An error correction circuit that receives an output signal of the subsequent stage and inputs a syndrome generated based on the effective data and the code data and performs error correction of the effective data;
It includes at least an exclusive OR circuit serially connected to the data register included in the front stage unit, and the effective data stored in the rear stage unit is input via the first selector circuit to correct errors in the effective data. Code data for correction is generated and stored in the front stage, and the code data stored in the front stage and the effective data stored in the rear stage are input via the first selector circuit to generate a syndrome. And a code data / syndrome generation circuit that stores the syndrome in the preceding stage in place of the code data.   The first selector circuit, when storing effective data in the subsequent stage, inputs input data from the outside and generates code data for correcting an error in the effective data stored in the subsequent stage. 2. The non-volatile semiconductor memory device according to claim 1, wherein output data of the subsequent stage is input in the case.   The second selector circuit inputs the output data of the subsequent stage when generating code data for correcting an error in effective data, and inputs the output data of the previous stage when generating a syndrome. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is configured as described above.   The second selector circuit is configured to be able to input external input data, and selectively selects one of the external input data, the output data of the front stage, or the output data of the rear stage. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is configured to be input at the head of the data. The nonvolatile semiconductor memory device according to claim 1, wherein the error correction circuit is connected to the preceding stage and configured to input the syndrome and perform error correction of the effective data.

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