JP2008165917A - Semiconductor device and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To constitute a semiconductor memory device having large data width by uniformalizing loads of external terminals and using a semiconductor device having small data width of memory data. <P>SOLUTION: The semiconductor device has: a memory cell array 22a; a first terminal 12a which is a terminal for performing input of address data being an address of a memory cell array inputting/outputting memory data stored in the memory cell array and inputting a part of the address data; a terminal having a second terminal 13a inputting a residual part of the address data; and a switch 20a in which when address data are input to the terminal, a part of the address data is connected to a first internal address line AI(n) or a second internal address line AI(n+16) based on shunting information and the residual part of the address data is connected to the other side internal address line. The invention includes also its control method. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a control method thereof, and relates to a semiconductor device having a semiconductor memory device and a control method thereof.

  In recent years, semiconductor memory devices such as flash memory, DRAM, and SRAM have been used in many electronic devices. A semiconductor memory device has a memory cell array in which memory cells for storing data are arranged in a matrix. The external circuit inputs / outputs data from / to the memory cell array by designating an address for inputting / outputting storage data stored in the memory cell array. Input / output of storage data from the external circuit and input of address data indicating an address are performed via the input / output circuit. Input / output of stored data between the external circuit and the input / output circuit is performed in parallel by a plurality of bits. The number of the plurality of bits is called a data width, and the data width is, for example, 16 bits or 32 bits. The address of the memory cell array for inputting / outputting storage data is specified by, for example, 25-bit address data. Input / output of storage data and address data between the external circuit and the input / output circuit is performed via a data terminal and an address terminal, respectively. However, reduction of these terminals is required. Therefore, there are cases where the data terminal and the address terminal are also used.

  A flash memory will be described as an example (conventional example 1) of a semiconductor memory device that serves both as a data terminal and an address terminal. FIG. 1 is a schematic diagram of a flash memory in which stored data is input / output with a data width of 16 bits and address data is 25 bits. The semiconductor chip 60 is provided with a memory cell array 68 and an input / output circuit 69. The input / output circuit 69 is connected to the pads 62 and 63. The pads 62 and 63 are connected to the external terminals 66 of the package by wires, for example. The pad 62 has D0 / A0 to D15 / A15 and is connected to ExD0 / A0 to ExD15 / A15 of the external terminal 66, respectively. The pad 63 has pads A16 to A24, and is connected to ExA16 to ExA24 of the external terminal 67, respectively.

  FIG. 2 is a diagram showing a data structure input / output from / to the external terminals 66 and 67 from an external circuit. The external circuit includes a system bus that also serves as a bus for sending address data and storage data. In the external circuit, the external terminal ExD0 / A0 inputs / outputs the first bit DB0 of the stored data when data is input / output. When the address is input, the first bit AB0 of the address data is input. The same applies to the external terminals ExD15 / A15. As described above, the external terminals ExD0 / A0 to ExD15 / A15 serve both as data terminals and address terminals. On the other hand, the external terminals ExA16 to ExA24 are address terminals for inputting only address data. Further, the pad 62 of the semiconductor chip 60 serves as both a data pad and an address pad. On the other hand, the pad 62 is an address pad for inputting only an address.

In Patent Document 1, in a plurality of semiconductor memory devices that do not use both an address terminal and a data terminal, the address terminals of the respective semiconductor memory devices are commonly connected, and the data terminals are separately connected to an external bus. Thus, a technology is disclosed that can cope with a wider external bus even if the data width of each semiconductor memory device is small.
JP-A-9-231131

  There is a demand to increase the data width for inputting / outputting data stored in a semiconductor memory device. However, for example, in order to realize a new semiconductor memory device with a data width of 32 bits, it is necessary to design and develop an input / output circuit. In this case, the development period and development cost increase. Therefore, for example, if two semiconductor chips having a data width of 16 bits as in Conventional Example 1 can be used to form a semiconductor memory device having a data width of 32 bits, the development period of the semiconductor memory device having a data width of 32 bits can be realized. And development costs can be reduced. However, if an attempt is made to construct a semiconductor memory device having a data width of 32 bits by using two semiconductor chips having a data width of 16 bits, both of which are used as address terminals and data terminals, the load on the external terminals is uniform. There is a problem of not being.

  The present invention has been made in view of the above problems, and a semiconductor device capable of configuring a semiconductor memory device having a large data width by using a semiconductor device having a uniform external terminal load and a small data width of stored data. The purpose is to provide.

  The present invention relates to a memory cell array, a terminal for inputting / outputting storage data to be stored in the memory cell array and inputting address data indicating an address of the memory cell array for inputting / outputting the storage data. A first terminal for inputting a part; a second terminal for inputting the remaining part of the address data; and a first internal address line and a second internal address line to which the address data is supplied And when the address data is input to the terminal, a part of the address data is connected to one of the first internal address line and the second internal address line based on predetermined replacement information, A switch for connecting the remaining part of the address data to the other of the first internal address line and the second internal address line. That is a semiconductor device. According to the present invention, the switch can change the address data to the address data without exchanging a part of the address data and the remaining part of the address data. By using two semiconductor devices of the present invention, the load connected to the external terminal can be equalized. This makes it possible to configure a semiconductor memory device having a larger data width.

  In the above configuration, when the storage data is input / output to / from the terminal, the storage data can be input / output to / from the memory cell array without passing through the switch. According to this configuration, the stored data can be directly input / output to / from the memory cell array regardless of the replacement information.

  In the above configuration, the first terminal inputs / outputs the stored data, inputs a part of the address data, and the second terminal inputs a remaining part of the address data. it can.

  In the above configuration, a replacement information terminal for inputting the predetermined replacement information may be provided, and the predetermined replacement information may be a voltage applied to the replacement information terminal. Moreover, in the said structure, it can be set as the structure which comprises the replacement | exchange information storage part which memorize | stores the said predetermined replacement | exchange information. According to these configurations, replacement information can be easily input.

  The present invention includes a first semiconductor device and a second semiconductor device which are semiconductor devices having the above-described configuration, and the first terminal of the first semiconductor device is a memory cell array of the first semiconductor device and the second semiconductor device. An external terminal for inputting / outputting first storage data which is a part of storage data stored in the memory, and inputting first address data which is a part of address data indicating an address of the memory cell array for inputting / outputting the storage data The second terminal of the first semiconductor device inputs / outputs second storage data that is the remaining part of the stored data, and the remaining part of the address data is connected to the first external terminal that is The second terminal is connected to a second external terminal that is an external terminal for inputting certain second address data, and the first terminal of the second semiconductor device is connected to the second external terminal. Serial second terminal is a semiconductor device that is connected to the first external terminal. According to the present invention, all external terminals are connected to two terminals. Therefore, the load connected to the external terminal can be equalized. As a result, it is possible to input / output parallel bits of stored data having a larger data width of the stored data of the first semiconductor device and the second semiconductor device.

  In the above configuration, the predetermined replacement information of the first semiconductor device may be different from the predetermined replacement information of the second semiconductor device.

  In the above configuration, the size of the first storage data and the size of the second storage data may be the same. According to this configuration, stored data can be stored using semiconductor devices having the same storage capacity and the same configuration.

  The present invention relates to a memory cell array, a terminal for inputting / outputting storage data to be stored in the memory cell array and inputting address data indicating an address of the memory cell array for inputting / outputting the storage data. A first terminal for inputting a part; a terminal having a second terminal for inputting the remaining part of the address data; a first internal address line and a second internal address line to which the address data is supplied; When the address data is input to the terminal, a part of the address data is transferred to the first internal address line and the second internal address line when the address data is input to the terminal. And the remaining part of the address data is transferred to the first internal address line and the second internal address. A control method of a semiconductor device having a step of connecting to the other line. According to the present invention, the switch can change the address data to the address data without exchanging a part of the address data and the remaining part of the address data. By using two semiconductor devices controlled by the present invention, the load connected to the external terminal can be equalized. Thereby, stored data having a larger data width can be stored.

  The present invention relates to a memory cell array, a terminal for inputting / outputting storage data to be stored in the memory cell array and inputting address data indicating an address of the memory cell array for inputting / outputting the storage data. A first terminal for inputting a part; a terminal having a second terminal for inputting the remaining part of the address data; a first internal address line and a second internal address line to which the address data is supplied; In the control method for the first semiconductor device and the second semiconductor device, respectively, the memory device stores the first terminal of the first semiconductor device in the memory cell arrays of the first semiconductor device and the second semiconductor device. A part of the first storage data is input / output, and the address of the memory cell array for inputting / outputting the storage data is indicated A step of connecting to a first external terminal which is an external terminal for inputting first address data which is a part of address data; and a second part of the first semiconductor device is connected to the remaining part of the stored data. Connecting to a second external terminal which is an external terminal for inputting / outputting certain second storage data and inputting second address data which is the remaining part of the address data; and A step of connecting one terminal to the second external terminal; a step of connecting the second terminal of the second semiconductor device to the first external terminal; and when the address data is input to the terminal, In each of the one semiconductor device and the second semiconductor device, a part of the address data is transferred between the first internal address line and the second internal address line based on predetermined replacement information. Connect Re or one, and connecting the remaining part of the address data to the other of said first internal address line and the second internal address line, a control method of a semiconductor device having a. According to the present invention, the loads connected to the external terminals can be made uniform. This makes it possible to input / output parallel bits of stored data having a larger data width of the stored data of the first semiconductor device and the second semiconductor device.

  According to the present invention, it is possible to configure a semiconductor memory device having a large data width by using a semiconductor device having a uniform external terminal load and a small data width of stored data.

  As an example of an external terminal, the data width of stored data is 32 bits, the address data is 25 bits, and the data terminal and the address terminal are used as an example. FIG. 3 is a diagram showing a data structure that is input to and output from the external circuit in this case. External terminals ExD0 / A0 to ExD24 / A24 serve both as data terminals and address terminals. ExD25 to ExD31 are data terminals.

FIG. 4 shows, as a comparative example, a semiconductor device in which the storage data has a data length of 16 bits, uses semiconductor chips 70a and 70b that do not serve as data pads and address pads, and inputs / outputs the storage data shown in FIG. 3 from an external circuit. It is. The semiconductor chips 70a and 70b have memory cell arrays 78a and 78b and input / output circuits 79a and 79b, respectively. Address pads 72a and 72b and data pads 73a and 73b are also provided. A0 to A24 which are address pads 72a of the semiconductor chip 70a are connected to ExD0 / A0 to ExA24 which are external terminals 76a, respectively. Therefore, when address data is input to the address pads A0 to A24 from the external terminal 76a, the bits AB0 to AB24 of the address data are input to the input / output circuit 79a. On the other hand, D0 to D15, which are data pads 73a, are connected to ExD0 / A0 to ExD15 / A15, which are external terminals 77a, respectively. Therefore, when stored data is input / output from / to the data pads D0 to D15 from the external terminal 77a, the bits DB0 to DB15 of the stored data are input / output to the input / output circuit 79a. In this manner, the semiconductor chip 79a stores DB0 to DB15 which are 16 bits out of the data width 32 bits of the storage data of the external terminal.

  The address pads 72b A0 to A24 of the semiconductor chip 70b are connected to the external terminals 76b ExD0 / A0 to Ex24, respectively. Therefore, when the address data bits AB0 to AB24 are input from the external terminal 76b to the address pads A0 to A24, the address data bits AB0 to AB24 are input to the input / output circuit 79b. On the other hand, D0 to D15 which are data pads 73b are respectively connected to ExD16 / A16 to ExD31 which are external terminals 77b. Therefore, when stored data is input / output from the external terminal 77b to the data pads D0 to D15, the bits DB16 to DB31 of the stored data are input / output to the input / output circuit 79a. As described above, the semiconductor chip 79a stores DB16 to DB32 corresponding to the remaining 16 bits of the data width 32 bits of the storage data of the external terminal. As described above, according to the comparative example, the data width of the storage data is 16 bits, two semiconductor chips that do not serve as the data input pad and the address pad are used, the data width of the storage data is 32 bits, and the address data is A 25-bit semiconductor memory device serving both as a data terminal and an address terminal is realized.

  However, the semiconductor memory device according to the comparative example has the following problems. As shown in FIG. 4, the external terminal ExD0 / A0 is connected to the pads A0 and D0 of the semiconductor chip 70a and the pad A0 and three pads of the semiconductor chip 70b. On the other hand, the external terminal ExA31 is connected to one pad of D15 of the semiconductor chip 70a. In this way, there are cases where there are three and one pad connected to the external terminal. Therefore, there is a problem that the load on the external terminal is different. An embodiment for solving the above problems will be described below.

  FIG. 5 is a schematic diagram of the semiconductor memory device according to the first embodiment. The semiconductor chips 10a and 10b are semiconductor devices having a data width of 16 bits and having both data pads and address pads. The semiconductor chips 10a and 10b have memory cell arrays 22a and 22b having flash memory cells, and input / output circuits 24a and 24b, respectively. The input / output circuits 24a and 24b have switches 20a and 20b for switching the address data based on the replacement information inputted from the option pads 14a and 14b, respectively.

  Switches 20a and 20b are connected to first internal address line AI (n) and second internal address line AI (n + 16), respectively. Here, n is 0 to 15 for the first internal address line and 0 to 8 for the second internal address line. The semiconductor chips 10a and 10b have first pads 12a and 12b, second pads 13a and 13b, and option pads 14a and 14b for inputting replacement information, respectively. Input / output circuits 24a and 24b connect the address data input to the first pad to the second internal address line AI (n + 16) and the address data input to the second pad when the replacement information is Vcc. 1 Connected to the internal address line AI (n). This connection operation is said to replace the address data. On the other hand, when the replacement information is Vss, the address data input to the first pad is connected to the first internal address line AI (n), and the address data input to the second pad is connected to the second internal address line AI ( n + 16). This connection operation is said not to replace the address operation. Note that the double lines below the symbols of the pads 12a, 13a, 12b and 13b indicate the address data selected in the semiconductor chips 10a and 10b. For example, the double line below A0 of D0 / D16 / A0 / A16 which is the first pad 12a indicates that the address data input from this pad is bit AB0. Details will be described later.

  D0 / D16 / A0 / A16 to D15 / D31 / A15, which are the first pads 12a of the semiconductor chip 10a, are connected to external terminals ExD0 / A0 to ExD15 / A15, respectively. The second pads 13a A0 / A16 to A15 are connected to the external terminals ExD16 / A16 to ExD31, respectively. The option pad 14a is connected to Vss which is a low level. For this reason, the switch 20a does not replace the address data. On the other hand, D0 / D16 / A0 / A16 to D15 / D31 / A15, which are the first pads 12b of the semiconductor chip 10b, are connected to the external terminals ExD16 / A16 to ExD31, respectively. The second pads 13b A0 / A16 to A15 are connected to the external terminals ExD0 / A0 to ExD15 / A15, respectively. The option pad 14b is connected to Vcc which is at a high level. For this reason, the switch 20b replaces the address data.

  FIG. 6 is a block diagram of the semiconductor chips 10a and 10b. The first external terminal 16 is connected to the first pad 12, the second external terminal 17 is connected to the second pad 13, and the option terminal 18 (Vss or Vcc) is connected to the option pad 14. Each pad 12, 13 and 14 is connected to an input / output circuit 24. The input / output circuit 24 includes an I / O circuit 30, address buffers 32 and 33, and a switch 20.

  In FIG. 6, one switch 20 is illustrated. However, the switch 20 includes a switch D0 / D16 / A0 / A16 of the first pad 12 and A15 / A16 of the second pad 13 and D15 of the first pad 12. / D31 / A15 and A15 of the second pad 13 are provided for each pair, and a replacement signal from the option pad 14 is input in common. For example, the set of D0 / D16 / A0 / A16 of the first pad 12 and A0 / A16 of the second pad 13 is connected to the internal address lines AI (0) and AI (16) via the switch 20, The address data input to the first pad 12 and the second pad 13 according to the exchange information is supplied to either the internal address line AI (0) or AI (16), respectively. Similarly, the set of D8 / D24 / A8 / A24 of the first pad 12 and A8 / A24 of the second pad 13 is connected to the internal address lines AI (8) and AI (24). The pairs of D9 / D25 / A9 to D15 / D31 / A15 of the first pad 12 and A9 to A15 of the second pad 13 are connected to the internal address lines AI (9) to AI (15) via the switch 20, respectively. Then, the address data input to one of the first pad 12 and the second pad 13 in accordance with the replacement information is supplied from the internal address lines AI (9) to AI (15).

  Stored data or address data input / output to / from the first pad 12 is output to the input / output or address buffer 32 to the I / O circuit 30. A WRE signal is input to the I / O circuit 30. The WRE signal is a signal that activates the I / O circuit 30. When the stored data is input / output, the I / O circuit 30 is activated. An ADV signal is input to the address buffer 32. The ADV signal is a signal that activates the address buffers 32 and 33. When address data is input, the address buffers 32 and 33 are activated and output the address data to the switch 20. On the other hand, the address data input to the second pad 13 is output to the address buffer 33. The address buffer 33 outputs address data to the switch 20. The option pad 14 is connected to the switch 20. The switch 20 outputs the address data input from the address buffers 32 and 33 to the internal address lines AI (n) and AI (n + 16) depending on whether the option pad 14 is Vss or Vcc.

  The internal address line AI outputs the address of the storage data stored in the memory cell array 22 to the X decoder 36 and the Y decoder 38. The I / O circuit 30 inputs / outputs stored data to / from the write circuit read circuit 42. The write circuit read circuit 42 writes the stored data to the memory cell array 22 via the Y selector 40 and reads the stored data. The Y selector 40 selects a bit line BL for writing or reading stored data in accordance with an instruction from the Y decoder 38. The X decoder selects a word line WL for writing or reading stored data. As described above, stored data can be written to or read from a desired address in the memory cell array 22.

  With reference to FIG. 7 to FIG. 10, the control when inputting / outputting storage data and inputting address data to / from the memory cell array 22 in the semiconductor memory device according to the first embodiment will be described.

  FIG. 7 shows a data structure when address data is input to the semiconductor chip 10a. The pads 12a and 13a of the semiconductor chip 10a (chip 1) and the external terminals 16a and 17a are connected as described with reference to FIG. AB0 to AB24, which are each bit of the address data 25 bits, are input from the external terminals ExD0 / A0 to Ex24 / A24 as the input of the external terminal. In the semiconductor chip 10a, the external terminals ExD0 / A0 to ExD15 / A15 are respectively connected to the first pads 12a, D0 / D16 / A0 / A16 to D15 / D31 / D15, so that D0 / D16 / A0 / A16 to D15 Bits AB0 to AB15 of the address data are input to / D31 / D15, respectively. AB0 to AB15 are input to the address buffer 32 and the I / O circuit. While the address data is input, the address buffer 32 is activated by the AVD signal. On the other hand, the I / O circuit 30 is inactivated by the WRE signal. Therefore, AB0 to AB15 are input to the address buffer 32 and are not input to the I / O circuit 30. The address buffer 32 outputs AB0 to AB15 to the switch 20a.

  On the other hand, since the external terminals ExD16 / A16 to ExD24 / A24 are connected to the second pads 13a A0 / A16 to A8 / A24, respectively, the address data bits AB16 to AB24 are respectively transferred from A0 / A16 to A8 / A24. Entered. Since the address buffer 33 is activated in the same manner as the address buffer 32, AB 16 to AB 24 are input to the address buffer 33. The address buffer 33 outputs bits AB16 to AB24 of the address data to the switch 20a.

  The option pad 14a of the semiconductor chip 10a is connected to Vss. At this time, the switch 20a outputs the address data input from the first pad 12a and the second pad 13a without switching. That is, the address signal input from the first pad 12a is output to the first internal address line AI (n), and the address signal input from the second pad 13a is output to the second internal address line AI (n + 16). . An internal address line AI in FIG. 7 indicates each internal address line from which a bit input to each pad is output. As shown in FIG. 7, the switch 20a is switched from D0 / D16 / A0 / A16 to D15 / D31 / D15 of the first pad 12a to AB0 to AB15 and from the second pad 13a to A0 / A16 to A8 / A24, respectively. The input AB16 to AB24 are not exchanged and output to the internal address line AI.

  FIG. 8 shows a data structure when stored data is inputted to and outputted from the semiconductor chip 10a. Bits DB0 to DB15 of the storage data input / output from / to external terminals ExD0 / A0 to ExD15 / A15 are input / output from D0 / D16 / A0 / A16 to D15 / D31 / A15, which are the first pads 12a, respectively. During input / output of stored data, the I / O circuit 30 is activated and the address buffer 32 is inactivated. Therefore, the bits DB0 to DB15 of the stored data are input / output to / from the I / O circuit 30 and are not input to the address buffer 32. Bits DB16 to DB31 of storage data input / output from / to ExD16 / A16 to ExD31, which are external terminals 17a, are input / output from A0 / 16 to A15 of second pad 13a, respectively. The second pad 13 a is not connected to the I / O circuit 30. Further, the address buffer 33 is inactivated during storage data input / output. Therefore, the bits DB16 to DB31 of the stored data are not input to the I / O circuit 30.

  As described above, in the semiconductor chip 10a, the bits DB0 to DB15 of the storage data are written to or read from the address specified by the bits AB0 to AB24 of the address data.

  FIG. 9 shows a data structure when an address is input to the semiconductor chip 10b. The pads 12b and 13b of the semiconductor chip 10b (chip 2) and the external terminals are connected as described with reference to FIG. AB0 to AB25, which are 25 bits of address data, are input from the external terminals ExD0 / A0 to ExD24 / A24 as input / output of the external terminals. In the semiconductor chip 10b, since the external terminals ExD16 / A16 to ExD24 / A24 are connected to the first pads 12b, D0 / D16 / A0 / A16 to D8 / D24 / A8 / A24, respectively, the first pads D0 / D16 / Bits AB16 to AB24 of the address data are input to A0 / A16 to D8 / D24 / A8 / A24, respectively. While the address data is input, the address buffer 32 is activated and the I / O circuit 30 is inactivated. Therefore, bits AB16 to AB24 of the address data are input to the address buffer 32 and are not input to the I / O circuit 30. The address buffer 32 outputs the bits AB16 to AB26 of the address data to the switch 20b.

  On the other hand, since the external terminals ExD0 / A0 to ExD15 / A15 are respectively connected to the second pads 13ba A0 / A16 to A15, the address data bits AB0 to AB15 are input to the second pads A0 / A16 to A15, respectively. Is done. Since the address buffer 33 is activated in the same manner as the address buffer 32, the bits AB0 to AB15 of the address data are input to the address buffer 33. The address buffer 33 outputs the bits AB0 to AB15 of the address data to the switch 20.

  The option pad 14b of the semiconductor chip 10b is connected to Vcc. At this time, the switch 20b exchanges and outputs the address data input from the first pad 12b and the second pad 13b. That is, the address data input from the first pad 12b is output to the second internal address line AI (n + 16), and the address data input from the second pad 13b is output to the first internal address line AI (n). . The switch 20b includes bits AB16 to AB24 of address data input to D0 / 16 / A0 / A16 to D8 / D24 / A8 / A24 of the first pad 12b, and A0 / A16 to A15 / A31 of the second pad 13b. The bits AB0 to AB31 of the address data respectively input to are exchanged and output to the internal address line AI.

  FIG. 10 shows a data structure when stored data is input / output to / from the semiconductor chip 10b. Bits DB16 to DB31 of storage data input / output from / to external terminals ExD16 / A16 to ExD31 are input / output from D0 / D16 / A0 / A16 to D15 / D31 / A15 of first pad 12b, respectively. During input / output of stored data, the I / O circuit 30 is activated and the address buffer 32 is inactivated. Therefore, the bits DB16 to DB31 of the stored data are input / output to / from the I / O circuit 30 and are not input to the address buffer 32. Bits DB0 to DB15 of storage data input / output from / to external terminals ExD0 / A0 to ExD15 / A15 are input / output from A0 / 16 to A15 of the second pad 13a, respectively. The second pad 13 b is not connected to the I / O circuit 30. Alternatively, the address buffer 33 is inactivated during storage data input / output. Therefore, the bits DB0 to DB15 of the stored data are not input to the I / O circuit 30.

  As described above, in the semiconductor chip 10b, the bits DB16 to DB31 of the storage data are written to or read from the address specified by the bits AB0 to AB24 of the address data.

  The semiconductor chip 10a (or 10b) of the semiconductor memory device according to the first embodiment has pads 12a and 13a (or terminals) that are terminals for inputting address data indicating addresses for inputting and outputting storage data stored in the memory cell array 18. 12b, 13b) (terminal). The first pad 12a (12b) is a pad (first terminal) for inputting a part of bits AB0 to AB15 (AB16 to AB24) of the address data, and the second pad 13a (13b) is a remaining part of the address data. Are pads (second terminals) for inputting bits AB16 to AB24 (AB0 to AB15). The address data is supplied to the first internal address line AI (n) (n is 0 to 15) and the second internal address line AI (n + 16) (n is 0 to 8). When the bits AB0 to AB24 of the address data are input to the pads 12a and 13a (12b and 13b), the switch 20a (20b) receives the address data based on the voltage of the option pad 14a (that is, predetermined replacement information). A part of bits AB0 to AB15 and a part of the remaining bits AB16 to AB24 of the address data are not replaced or replaced with address data. In other words, the switch 20a of the semiconductor chip 10a sends a part of the bits AB0 to AB15 of the address data to the first internal address line AI (n), and a part of the bits AB16 to AB24 of the address data to the second internal address line. Connect to AI (n + 16). Further, the switch 20b of the semiconductor chip 10b includes a part of bits AB0 to AB15 of the address data to the second internal address line AI (n + 16) and a part of bits AB16 to AB24 of the remaining part of the address data to the first internal address line. Connect to AI (n). As described above, the semiconductor chips 10a and 10b have the option pads 14a and 14b that allow the switches 20a and 20b to exchange the address data from the outside without replacing the bits AB0 to AB15 and AB16 to AB24 of the address data, respectively. Can be output to line AI.

In addition, as shown in FIG. 6, when bits DB0 to DB15 (DB16 to DB31) of the storage data are input / output to / from the first pad 12a (or 12b), the storage data does not pass through the switch 20a and is transferred to the memory cell array 18. Stored data is input / output. Thereby, the bits DB0 to DB15 (or DB16 to DB31) of the stored data can be directly input / output to / from the memory cell array 18 regardless of the replacement information.

  Further, the first pad 12a (or 12b) (first terminal) inputs / outputs the bits DB0 to DB15 (DB16 to DB31) of the stored data bits, and the bits AB0 to AB15 (or AB16) of some bits of the address data. Enter AB24). The second pad 13a (or 13b) (second terminal) inputs the remaining bits AB16 to AB24 (AB0 to AB15) of the address data.

  Furthermore, it has option pads 14a and 14b (exchange information terminals) for inputting replacement information from an external circuit, and the replacement information is voltages Vss and Vcc applied to the option pads 14a and 14b. Thus, by using the voltages applied to the option pads 14a and 14b as the replacement information, the replacement information can be easily input to the switches 20a and 20b.

  The semiconductor memory device according to the first embodiment includes a semiconductor chip 10a (first semiconductor device) and a semiconductor chip 10b (second semiconductor device). The external terminals ExD0 / A0 to ExD15 / A15 (first external terminals) input / output bits DB0 to DB15 (first storage data) that are part of the bits DB0 to DB31 of the storage data, and bits of the address data AB0 to AB15 (first address data), which are some bits of AB0 to AB24, are output. External terminals ExD16 / A16 to ExD31 (second external terminals) input / output DB16 to DB31 (second storage data), which are the remaining part of bits DB0 to DB31 of the storage data, and input the remaining one of the address data. The bits AB16 to AB24 (second address data) are output. External terminals ExD0 / A0 to ExD15 / A15 (first external terminals) are connected to D0 / D16 / A0 / A16 to D15 / D31 / A15 (first terminals) which are the first pads 12a of the semiconductor chip 10a. External terminals ExD16 / A16 to ExD31 (second external terminals) are connected to the two pads 13a (second terminals). On the other hand, external terminals ExD16 / A16 to ExD31 (second external terminals) are connected to D0 / D16 / A0 / A16 to D15 / D31 / A15 (first terminals), which are the first pads 12b of the semiconductor chip 10b. External terminals ExD0 / A0 to ExD15 / A15 (first external terminals) are connected to the two pads 13a (second terminals). With such a configuration, the external terminals D0 / A0 to D31 are all connected to the two pads. Therefore, unlike the comparative example, the external terminal is not connected to three pads and one pad. Thereby, the load connected to an external terminal can be equalized.

  Further, the replacement information of the semiconductor chip 10a is Vss, and the replacement information of the semiconductor chip 10b is Vcc, which is different. Accordingly, as shown in FIGS. 7 and 9, one of the switches 20a and 20b of the semiconductor chip 10a and the semiconductor chip 10b exchanges address data, and the other does not exchange address data. Therefore, the address data input to different pads in the semiconductor chip 10a and the semiconductor chip 10b can be returned to the address data in the same arrangement.

  Further, the size of the first storage data is 16 bits, and the size of the second storage data is 16 bits, which is the same. Thereby, bits DB0 to DB31 of stored data can be stored using semiconductor chips 10a and 10b having the same storage capacity and the same configuration.

  The second embodiment is an example of a semiconductor chip that stores replacement information in a CAM (Content Addressable Memory) instead of an option pad. 11 has a 1-bit CAM 26 in place of the option pad 14a with respect to the semiconductor chip 10a of FIG. Other configurations are the same as those of the semiconductor chips 10a and 10b of the first embodiment. The semiconductor chip 10 includes a memory cell array 22, a switch 20, and pads 12 and 13.

  According to the second embodiment, a CAM (replacement information storage unit) that stores replacement information is included. The semiconductor memory device according to the first embodiment is configured by using two semiconductor chips 10 according to the second embodiment. For example, by inputting data to the CAM when the semiconductor memory device is shipped, a semiconductor memory device having the same function as that of the first embodiment can be obtained.

  Although the first and second embodiments are examples of a semiconductor device using a flash memory, the present invention can also be applied to a semiconductor memory device such as a DRAM or SRAM having a memory cell array. Further, the pads 12a and 12b of the semiconductor chips 10a and 10b are described as the first terminals, and the pads 13a and 13b of the semiconductor chips 10a and 10b are described as the second terminals. The first terminal and the second terminal may be terminals that input and output stored data or address data from the semiconductor chip, and may be bumps formed on the semiconductor chip, for example. Furthermore, although the package leads have been described as examples of the first external terminal and the second external terminal, they may be connected by bumps or the like. Furthermore, the semiconductor chips 10a and 10b may be stacked and mounted. Further, although the data width of the storage data input / output from / to the external circuit is 32 bits and the data width of the semiconductor chips 10a and 10b is 16 bits, the present invention is not limited to this. As in the first embodiment, the data width of the storage data input / output from the external circuit is preferably double the data width of the semiconductor chips 10a and 10b.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible

FIG. 1 is a schematic diagram of a conventional semiconductor memory device. FIG. 2 is a diagram showing a data structure of an external terminal according to a conventional example. FIG. 3 is a diagram illustrating a data structure of the external terminals according to the comparative example and the example. FIG. 4 is a schematic diagram of a semiconductor memory device according to a comparative example. FIG. 5 is a schematic diagram of the semiconductor memory device according to the first embodiment. FIG. 6 is a block diagram of a semiconductor chip of the semiconductor memory device according to the first embodiment. FIG. 7 is a diagram illustrating a data structure when address data is input to the semiconductor chip 10a according to the first embodiment. FIG. 8 is a diagram illustrating a data structure when stored data is input to the semiconductor chip 10a according to the first embodiment. FIG. 9 is a diagram illustrating a data structure when address data is input to the semiconductor chip 10b according to the first embodiment. FIG. 10 is a diagram illustrating a data structure when storage data is input to the semiconductor chip 10b according to the first embodiment. FIG. 11 is a schematic diagram of a semiconductor chip according to the second embodiment.

Explanation of symbols

10, 10a, 10b Semiconductor chip 12, 12a, 12b First pad 13, 13a, 13b Second pad 14, 14a, 14b Option pad 16 First external terminal 17 Second external terminal 18 Memory cell array 20, 20a, 20b Switch 22 , 22a, 22b Memory cell array

Claims (10)

A memory cell array;
A terminal for inputting / outputting storage data to be stored in the memory cell array and inputting address data indicating an address of the memory cell array for inputting / outputting the storage data, wherein the first terminal inputs a part of the address data And a second terminal for inputting the remaining part of the address data, and
A first internal address line and a second internal address line to which the address data is supplied;
When the address data is input to the terminal, a part of the address data is connected to one of the first internal address line and the second internal address line based on predetermined replacement information, and the address data And a switch for connecting the remaining part of the second internal address line to the other of the first internal address line and the second internal address line.   A semiconductor device in which, when the stored data is input / output to / from the terminal, the stored data is input / output to / from the memory cell array without passing through the switch. The first terminal inputs / outputs the stored data, inputs a part of the address data,
The semiconductor device according to claim 1, wherein the second terminal inputs a remaining part of the address data. A replacement information terminal for inputting the predetermined replacement information;
The semiconductor device according to claim 1, wherein the predetermined replacement information is a voltage applied to the replacement information terminal.   4. The semiconductor device according to claim 1, further comprising a replacement information storage unit that stores the predetermined replacement information. A first semiconductor device and a second semiconductor device which are semiconductor devices according to any one of claims 1 to 5,
The first terminal of the first semiconductor device inputs and outputs first storage data that is a part of storage data stored in the memory cell arrays of the first semiconductor device and the second semiconductor device, and inputs the storage data. Connected to a first external terminal which is an external terminal for inputting first address data which is a part of address data indicating an address of the memory cell array to be output;
The second terminal of the first semiconductor device inputs and outputs second storage data that is the remaining part of the stored data, and inputs second address data that is the remaining part of the address data. Connected to a second external terminal, which is a terminal,
The first terminal of the second semiconductor device is connected to the second external terminal;
The semiconductor device wherein the second terminal of the second semiconductor device is connected to the first external terminal.   The semiconductor device according to claim 6, wherein the predetermined replacement information of the first semiconductor device is different from the predetermined replacement information of the second semiconductor device.   The semiconductor device according to claim 6 or 7, wherein the first storage data and the second storage data have the same size. A memory cell array, and a terminal for inputting / outputting storage data stored in the memory cell array and inputting address data indicating an address of the memory cell array for inputting / outputting the storage data, wherein a part of the address data is input A semiconductor device comprising: a first terminal that receives the second terminal for inputting the remaining part of the address data; and a first internal address line and a second internal address line to which the address data is supplied. In the device control method,
When the address data is input to the terminal, a part of the address data is connected to one of the first internal address line and the second internal address line based on predetermined replacement information, and the address A method for controlling a semiconductor device, comprising: connecting a remaining part of data to the other of the first internal address line and the second internal address line. A memory cell array, and a terminal for inputting / outputting storage data stored in the memory cell array and inputting address data indicating an address of the memory cell array for inputting / outputting the storage data, wherein a part of the address data is input And a first internal address line to which the address data is supplied, and a second internal address line to which the address data is supplied, respectively. In the control method of the first semiconductor device and the second semiconductor device,
The first terminal of the first semiconductor device inputs / outputs first storage data that is part of storage data stored in the memory cell arrays of the first semiconductor device and the second semiconductor device, and inputs the storage data Connecting to a first external terminal which is an external terminal for inputting first address data which is a part of address data indicating an address of the memory cell array to be output;
The second terminal of the first semiconductor device inputs / outputs second storage data that is the remaining part of the stored data, and inputs second address data that is the remaining part of the address data. Connecting to a second external terminal which is a terminal;
Connecting the first terminal of the second semiconductor device to the second external terminal;
Connecting the second terminal of the second semiconductor device to the first external terminal;
When the address data is input to the terminal, a part of the address data is transferred to the first internal address line and the first semiconductor device based on predetermined replacement information in each of the first semiconductor device and the second semiconductor device. And connecting to one of two internal address lines and connecting the remaining part of the address data to the other of the first internal address line and the second internal address line.

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