JP2008191348A - Display device - Google Patents

Abstract

When a drive circuit incorporates an electronic volume for adjusting a reference common voltage and a memory circuit for storing the adjustment value, the cost can be reduced as compared with the prior art.
A display device including a driving circuit for driving a plurality of pixels, each pixel having a pixel electrode and a counter electrode facing the pixel electrode, wherein the driving circuit A common voltage generation circuit that inputs a common voltage to the counter electrode, the common voltage generation circuit includes a reference common voltage generation circuit that generates a reference common voltage, and a memory circuit; and the reference common voltage generation circuit includes a reference common voltage generation circuit An electronic volume for adjusting a common voltage is provided, and the memory circuit includes a fuse memory element having a plurality of storage cells, and stores an adjustment value of the electronic volume. The memory circuit includes a fuse memory element having the plurality of memory cells, a register, and a control circuit.
[Selection] Figure 1

Description

  The present invention relates to a display device, and more particularly to a technique effective when applied to a common voltage generation circuit of a liquid crystal display device.

2. Description of the Related Art A TFT (Thin Film Transistor) type liquid crystal display module having a small liquid crystal panel is widely used as a display unit of a mobile device such as a mobile phone.
In general, since the life of a liquid crystal is deteriorated when a DC voltage is applied, it is necessary to drive the liquid crystal with an alternating current, and a common inversion driving method is known as one of the alternating current driving methods.
In this common inversion driving method, the electric field direction in the liquid crystal layer is a direction from the pixel electrode to the counter electrode (also referred to as a common electrode or a common electrode) (hereinafter referred to as positive writing), or from the counter electrode to the pixel. In the direction toward the electrode (hereinafter referred to as negative-polarity writing), the screen is alternately switched every screen (frame) or every horizontal scanning period.
That is, at the time of writing with positive polarity, the potential of the video voltage applied to the pixel electrode is higher than the potential of the common voltage (also referred to as common voltage) (Vcom) applied to the counter electrode. Sometimes, the potential of the common voltage (Vcom) applied to the counter electrode is higher than the potential of the video voltage applied to the pixel electrode. Here, the common voltage (Vcom) applied to the counter electrode at the time of positive polarity writing is the low level common voltage (VcomL), and the common voltage (Vcom) applied to the counter electrode at the time of negative polarity writing. Is referred to as a high level common voltage (VcomH).

The common voltage (Vcom) described above needs to be adjusted to a voltage value that optimizes the display quality of an image displayed on the liquid crystal display panel after the liquid crystal display panel is assembled.
In this case, the voltage of VcomH is generally adjusted, but in the conventional method, the voltage of VcomH is adjusted using a semi-fixed resistor which is an external component. .
In recent years, however, liquid crystal display modules have been demanded to be smaller and more integrated. Therefore, liquid crystal display modules having a small liquid crystal panel may not have a space for mounting a semi-fixed resistor. An electronic volume may be used instead of the semi-fixed resistor that is a component. When an electronic volume is used instead of the semi-fixed resistor, it is possible to reduce the cost.
In this case, since the electronic volume is built in the drive circuit (driver), it is necessary to store the adjustment value of the electronic volume after adjusting the voltage of VcomH in the memory circuit of the drive circuit. When EP or EEP-ROM is used as this memory circuit, there is a problem that the test cost increases.
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a display device with an electronic volume for adjusting a reference common voltage and a memory for storing the adjusted value in a drive circuit. It is an object of the present invention to provide a technique capable of reducing the cost as compared with the conventional case when a circuit is incorporated.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A display device including a plurality of pixels and a drive circuit that drives the plurality of pixels, wherein each pixel includes a pixel electrode and a counter electrode facing the pixel electrode, The drive circuit includes a common voltage generation circuit that inputs a common voltage to the counter electrode, and the common voltage generation circuit includes a reference common voltage generation circuit that generates a reference common voltage and a memory circuit, and the reference common voltage The generation circuit has an electronic volume for adjusting a reference common voltage, and the memory circuit has a fuse memory element having a plurality of storage cells, and stores an adjustment value of the electronic volume.
(2) In (1), the memory circuit stores the adjustment value read from the fuse memory element and the fuse memory element having the plurality of memory cells, or the adjustment value written to the fuse memory element. And a control circuit that reads the adjustment value stored in the fuse memory element and stores the adjustment value in the register, or writes the adjustment value stored in the register to the fuse memory element.

(3) In (1) or (2), the fuse memory element has m adjustment value storage blocks each consisting of k-bit storage cells and one management information storage consisting of n-bit storage cells. It is composed of blocks.
(4) In (3), the control circuit reads the management information stored in the management information storage block, specifies the adjustment value storage block in which the latest adjustment value is written, and specifies the specified The latest adjustment value is read from the adjustment value storage block and stored in the register, or the management information stored in the management information storage block is read and the new adjustment value is written. A block is specified, and the new adjustment value stored in the register is written into the specified adjustment value storage block.
(5) In any one of (1) to (4), the reference common voltage is a high level common voltage.
(6) In any one of (1) to (5), the display device is a liquid crystal display device.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the display device of the present invention, when the electronic circuit for adjusting the reference common voltage and the memory circuit for storing the adjustment value are incorporated in the drive circuit, the cost can be reduced as compared with the conventional case.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display module according to an embodiment of the present invention.
In the liquid crystal display panel (PNL), a plurality of scanning lines (or gate lines) (GL) and video lines (also called source lines or drain lines) (DL) are provided in parallel. A plurality of sub-pixels are provided corresponding to the intersections of the scanning lines (GL) and the video lines (DL). Each subpixel includes a thin film transistor (TFT), a pixel electrode (PX) connected to a source electrode (or drain electrode) of the thin film transistor (TFT), and a counter electrode facing the pixel electrode (PX) via a liquid crystal layer. (CT). Note that LC is a liquid crystal capacitor equivalently indicating a liquid crystal layer, and Cadd is a storage capacitor formed between the counter electrode (CT) and the pixel electrode (PX).
FIG. 2 is a diagram showing a subpixel structure of the liquid crystal display panel (PNL) shown in FIG. In the liquid crystal display panel (PNL) shown in FIG. 2, the R, G, and B subpixels are arranged in the order of R → G → B in one display line direction (extension direction of the scanning line (GL)), In addition, R, G, and B sub-pixels are arranged on one straight line in the extending direction of the video line (DL). In FIG. 2, the number of subpixels of the liquid crystal panel (PNL) is 640 × 3 × 480.

In FIG. 1, a counter electrode (also referred to as a common electrode or a common electrode) (CT) is provided so as to face each pixel electrode (PX) with the liquid crystal interposed therebetween. Therefore, a liquid crystal capacitor (LC) is formed between each pixel electrode (PX) and the counter electrode (CT).
The liquid crystal panel (PNL) is made of, for example, a glass substrate, and a second substrate on which a first substrate (SUB1) provided with a pixel electrode (PX), a thin film transistor (TFT), etc., and a color filter is formed. A substrate (not shown) is overlapped with a predetermined gap, and both substrates are bonded together by a seal material provided in a frame shape near the peripheral edge between the two substrates, and provided on a part of the seal material. The liquid crystal is sealed and sealed inside the sealing material between the substrates from the liquid crystal sealing port, and a polarizing plate is attached to the outside of the substrates.
Since the present invention is not related to the internal structure of the liquid crystal panel, a detailed description of the internal structure of the liquid crystal panel is omitted. Furthermore, the present invention can be applied to a liquid crystal panel having any structure. For example, in the case of the vertical electric field method, the counter electrode (CT) is formed on the second substrate. In the case of the horizontal electric field method, the counter electrode (CT) is formed on the first substrate. A color filter may be provided on the first substrate.

In the liquid crystal display module shown in FIG. 1, a drive circuit (DRV) is mounted on the first substrate (SUB1). In FIG. 1, FPC is a flexible wiring board.
Note that FIG. 1 illustrates the case where the drive circuit (DRV) is configured by one semiconductor chip. However, the drive circuit (DRV) includes, for example, a thin film transistor that uses low-temperature polysilicon for a semiconductor layer. It may be used to form directly on the first substrate (SUB1).
Similarly, a part of the circuit of the drive circuit (DRV) may be divided and the drive circuit (DRV) may be configured by a plurality of semiconductor chips. It may be formed directly on the first substrate (SUB1) by using a thin film transistor using low-temperature polysilicon as a layer. Further, the drive circuit (DRV) or a part of the drive circuit (DRV) may be formed on the flexible wiring substrate instead of being mounted on the first substrate (SUB1).
Display data and a display control signal are input to the drive circuit (DRV) from a graphic controller or the like on the main body side. In FIG. 1, DI is a display data interface (RGB interface), and is a system (external data) in which image data formed by an external graphic controller and a data capturing clock are continuously input. . In this display data interface (DI), the image data is sequentially captured in accordance with the capture clock in the same manner as a drain driver used in a conventional personal computer.

In FIG. 1, the drain electrode (or source electrode) of the thin film transistor (TFT) of each subpixel arranged in the column direction is connected to a video line (DL), and each video line (DL) is connected to a drive circuit (DRV). ). The drive circuit (DRV) supplies a video voltage corresponding to the display data to the video line (DL).
Further, the gate electrodes of the thin film transistors (TFTs) of the sub-pixels arranged in the row direction are respectively connected to the scanning lines (GL), and the respective scanning lines (GL) are connected to the driving circuit (DRV). The driving circuit (DRV) supplies a scanning voltage (positive or negative bias voltage) to the gate of the thin film transistor (TFT) for one horizontal scanning time.
When displaying an image on the liquid crystal display panel (PNL), the drive circuit (DRV) moves the scanning lines (GL1 to GLm) from top to bottom (in the order of GL1 → GLm) or from bottom to top. On the other hand, during the selection period of a certain scanning line, the drive circuit (DRV) supplies the video voltage corresponding to the display data to the video line (DL).
The voltage supplied to the video line (DL) is output to the pixel electrode (PX) via the thin film transistor (TFT), and finally the charge is charged to the storage capacitor (Cadd) and the liquid crystal capacitor (LC). Then, an image is displayed by controlling the liquid crystal molecules.

FIG. 3 is a block diagram showing a schematic configuration of the drive circuit (DRV) shown in FIG. In FIG. 3, 10 is an image data interface circuit, 11 is a D / A conversion circuit, 12 is a scanning line / video line driving circuit, 13 is a serial interface circuit (for a control register circuit), 14 is a memory circuit for adjusting a common voltage, Reference numeral 15 is a control register circuit, 16 is a common voltage generation circuit, and 17 is a liquid crystal application voltage generation circuit.
In this embodiment, when the display data (Data) input from the display data interface (DI) is composed of 6 bits for each of R, G, and B colors, the liquid crystal application voltage generation circuit 17 has 64 bits. A gradation voltage of (= 2 ⁶ ) gradation is generated.
The shift register circuit in the image data interface circuit 10 generates a capture pulse synchronized with the dot clock (DCLK) based on the dot clock (DCLK) input from the outside.
The latch circuit of the image data interface circuit 10 captures display data input from the outside based on the capture pulse output from the shift register circuit.
The D / A conversion circuit 11 selects and outputs the gradation voltage corresponding to the display data stored in the latch circuit from the gradation voltages of 64 gradations generated by the liquid crystal application voltage generation circuit 17. .
The scanning line / video line driving circuit 12 in the image data interface circuit 10 amplifies (current amplifies) the gradation voltage output from the D / A conversion circuit 11 and outputs it to the corresponding video line (DL). . The scanning line / video line driving circuit 12 generates a scanning voltage and outputs it to the scanning line (GL).
As a result, an image is displayed on the liquid crystal display panel (PNL). The above-described operation is executed under the instruction / control of the control register circuit 15.

The common voltage generation circuit 16 outputs a common voltage (Vcom) to the counter electrode (CT). The common voltage generation circuit 16 includes a reference common voltage generation circuit that generates a voltage VcomH (reference common voltage).
FIG. 4 is a circuit diagram illustrating an example of the reference common voltage generation circuit. In the reference common voltage generating circuit shown in FIG. 4, the voltage of VDH generated by the liquid crystal application voltage generating circuit 17 is divided by a series resistance voltage dividing circuit including an electronic volume (R1) and a resistance element (R2). , VcomH is generated. Further, the VcomL voltage generation circuit 30 generates a VcomL voltage from the VcomH voltage. The VcomL voltage generation circuit 30 includes a subtraction circuit using an operational amplifier.
In this embodiment, the voltage VcomH is adjusted by adjusting the electronic volume (R1) so that the display quality of the image displayed on the liquid crystal display panel (PNL) is optimized. The adjustment value at this time is stored in the common voltage adjustment memory circuit 14. The common voltage adjusting memory circuit 14 has a fuse memory element which is an OTP (One-Time-Program) -ROM.
The serial interface circuit 13 reads the adjustment value from the common voltage adjustment memory circuit 14 and passes it to the common voltage generation circuit 16 when the liquid crystal display module is activated. The common voltage generation circuit 16 adjusts the electronic volume based on the adjustment value, generates a voltage VcomH, and further generates a voltage VcomL from the voltage VcomH.
Then, a voltage VcomH or a voltage VcomL is output to the counter electrode (CT) in accordance with the AC period of the common inversion driving method.

FIG. 5 is a block diagram showing an example of the common voltage adjustment memory circuit 14 shown in FIG. In FIG. 5, 20 is a fuse memory element, 21 is a control circuit, 22 is a register for storing adjustment values, and 23 is a register for storing management information.
FIG. 6 is a circuit diagram showing an example of the configuration of one memory cell of the fuse memory element 20 shown in FIG. As shown in FIG. 6A, one memory cell of the fuse memory element 20 includes a level shift circuit (RES) for level-shifting a write signal (PROGRAM), a fuse element (FUSE) made of polysilicon, An NMOS transistor (NMS) for controlling on (melting) and off (non-melting) of the fuse element (FUSE), a level sense circuit (RSC) for detecting the state of the fuse element (FUSE), and a level sense circuit (RSC) The inverter (INB) inserted into the output of the signal, the transfer gate circuit (TFG) that is turned on by the read signal (READ) and reads the output of the level sense circuit (RSC), and the latch circuit (RCH).
In one memory cell of the fuse memory element 20 shown in FIG. 6, at the time of programming, a fuse element blowing power supply voltage (VFS), a fuse element on / off control power supply voltage (VPP), and a logic power supply voltage (VDD) are supplied. The fuse (FUSE) to be applied and programmed one address at a time by the address signal (A [5: 0]) is designated. Then, the write signal (PROGRAM) is set to “High” level, the NMOS transistor (NMS) is turned on, a current is passed through the fuse element (FUSE), and the fuse element (FUSE) is blown.

In one memory cell of the fuse memory element 20 shown in FIG. 6, it is sufficient that only the logic power supply (VDD) is applied at the time of reading. When an unprogrammed fuse element (FUSE) is read, FIG. ), The drain of the NMOS transistor (NMS) is pulled down to the ground voltage (GND) via the fuse element (FUSE) and the resistance element (R), so that the level sense circuit (RSC) is connected to the ground voltage (RSC). GND) is detected, and a “Low” level (= GND) is output. Since the “Low” level voltage is inverted by the inverter (INB) and further inverted by the latch circuit (RCH), the output (DOUT) becomes the “Low” level (= GND).
On the other hand, when the programmed fuse element (FUSE) is read, as shown in FIG. 6C, the drain of the NMOS transistor (NMS) is in a floating state, so that the level sense circuit (RSC) detects the floating state. Thus, the “High” level (= VDD) is output. This “High” level voltage is inverted by the inverter (INB) and further inverted by the latch circuit (RCH), so that the output (DOUT) becomes the “High” level (= VDD).
In this manner, the program state of the fuse memory element 20 can be output as a digital signal (DOUT [63: 0]) of “High” and “Low” level.

In the present embodiment, the fuse memory element 20 is composed of 64-bit storage cells. However, as shown in FIG. 7A, the [7: 0] -bit storage cells store management information. The remaining [63: 8] bit storage cells are used as information storage blocks, and the adjustment value storage blocks for storing the adjustment values of the electronic volume are used.
In this embodiment, since the adjustment value of the electronic volume is 7-bit data, the adjustment value storage block is an adjustment value storage block 1 composed of [14: 8] bit storage cells, [21:15]. Adjustment value storage block 2 consisting of bit storage cells, adjustment value storage block 3 consisting of [28:22] bit storage cells, adjustment value storage block 4 consisting of [35:29] bit storage cells, [ 42:36] adjustment value storage block 5 consisting of memory cells, adjustment value storage block 6 consisting of [49:43] bit storage cells, and adjustment value storage consisting of [56:50] bit storage cells The block 7 is composed of an adjustment value storage block 8 composed of [63:57] bit storage cells.
FIG. 7B shows the management information stored in the [7: 0] bit storage cell when the adjustment value is stored in the adjustment value storage blocks 1 to 8 of the fuse memory element 20. [7: 0] bit storage cells are programmed sequentially from the least significant bit (from [0] bit to [7] bit).

By inputting this management information to, for example, the logical circuit shown in FIG. 8, it is possible to determine the adjustment value storage block in which the latest adjustment value is stored. FIG. 7B also shows the output (B [7: 0]) of the logic circuit shown in FIG.
In the logic circuit shown in FIG. 8, when the [7: 0] bit storage cell is [0,0,0,0,0,0,0,1], its output (B [7: 0]) is [ 0,0,0,0,0,0,0,1], indicating that the adjustment value storage block that outputs the latest adjustment value is the adjustment value storage block 1, and [7: 0] bits When the memory cell is [0,0,0,0,0,0,1,1], its output (B [7: 0]) is [0,0,0,0,0,0,1, 0], indicating that the adjustment value storage block that outputs the latest adjustment value is the adjustment value storage block 2. Similarly, [7: 0] -bit storage cells are sequentially transferred from [0,0,0,0,0,1,1,1] to [1,1,1,1,1,1,1,1]. The output (B [7: 0]) is programmed from [0,0,0,0,0,1,0,0] to [1,0,0,0,0,0,0,0 The adjustment value storage blocks that output the latest adjustment values are the integer value storage block 3 to the adjustment value storage block 8.
Further, the adjustment value storage block to which the next adjustment value is written monitors the state of the [7: 0] bit. For example, the storage cell of the [7: 0] bit has a [0,0,0,0,0,0 , 0,1], the adjustment value storage block into which the adjustment value is written becomes the adjustment value storage block 2, and the [7: 0] bit storage cell is [0,0,0,0,0,0, [1, 1], address management is performed so that the adjustment value storage block into which the adjustment value is written becomes the adjustment value storage block 3.

Hereinafter, the adjustment value reading operation from the fuse memory element 20 of this embodiment will be described.
FIG. 9 is a flowchart for explaining the adjustment value reading operation from the fuse memory element 20 of this embodiment.
First, when the power is turned on (step 101) and the sequence bit is turned on (step 102), a read signal (READ) is generated (step 103).
Then, the data (DOUT [63: 0]) stored in each memory cell of the fuse memory element 20 is read from the fuse memory element 20 (step 104).
Next, based on the management information of [7: 0] bits in the read data (DOUT [63: 0]), an adjustment value storage block storing the latest adjustment value is selected (step 105). .
The 7-bit adjustment value is read from the adjustment value storage block selected in the above step and stored in the register 22.
Thereafter, the common voltage generation circuit 16 adjusts the electronic volume based on the adjustment value stored in the register 22 to generate a voltage VcomH, and further generates a voltage VcomL from the voltage VcomH.

FIG. 10 is a timing chart illustrating an example of an operation for reading an adjustment value from the fuse memory element 20 according to this embodiment.
In FIG. 10, VSYNC is a vertical synchronization signal, and HSYNC is a horizontal synchronization signal. Based on the signal of HSYNC1_P that synchronizes with the horizontal synchronization signal (HSYNC), the control circuit 21 enables the enable signal (ENB_N) for the period of T1.
Next, the control circuit 21 outputs a read signal (READ_P) to the fuse memory element 20, and data (DOUT [63: 0]) stored in each memory cell of the fuse memory element 20 from the fuse memory element 20. Is read.
Next, the control circuit 21 outputs a register clock (FADCK_P) to the register 23, and the register 23 stores management information of [7: 0] bits in the read data (DOUT [63: 0]). The management information (FBSEL [7: 0]) is output to the control circuit 21.
Based on the management information (FBSEL [7: 0]), the control circuit 21 selects an adjustment value storage block in which the latest adjustment value is stored, information on the selected adjustment value storage block, and a register clock (IN_SREG2_P) is output to the register 22.
The register 22 reads the 7-bit adjustment value (VCOM adjustment bit in FIG. 5) from the designated adjustment value storage block, stores the read value in the register 22, and then outputs the adjustment value (VCM [6: 0]).

Hereinafter, the adjustment value writing operation to the fuse memory element 20 of this embodiment will be described.
FIG. 11 is a flowchart for explaining the adjustment value writing operation to the fuse memory element 20 of this embodiment.
First, an image is displayed on the liquid crystal display panel (PNL) (step 111), and the electronic volume (R1) is adjusted while visually checking the image being displayed on the liquid crystal display panel (PNL) to adjust the voltage of VcomH. And the adjustment value of the electronic volume (R1) is stored in the register 22 (step 112).
Next, a read signal (READ) is generated (step 113), and data (DOUT [63: 0]) stored in each memory cell of the fuse memory element 20 is read from the fuse memory element 20 (step 114). .
Next, an adjustment value storage block for writing a new adjustment value is selected based on the management information of [7: 0] bits in the read data (DOUT [63: 0]) (step 115). The adjustment values stored in the register 22 are sequentially written (step 116), and the operation of writing the adjustment values to the fuse memory element 20 is terminated (step 117).
Thereafter, as shown in FIG. 11A, the voltage is immediately reflected in the voltage VcomH, or the latest adjustment value written in the register 22 in the re-on sequence is loaded and then reflected in the voltage VcomH ( Step 118).

FIG. 12 is a timing chart illustrating an example of an operation for writing an adjustment value to the fuse memory element 20 according to this embodiment.
The control circuit 21 outputs a register clock (FADCK_P) to the register 23. The register 23 outputs the stored management information (FBSEL [7: 0]) to the control circuit 21.
Based on the management information (FBSEL [7: 0]), the control circuit 21 sets an initial address (A [5: 0]) of an adjustment value storage block for storing a new adjustment value.
Next, the control circuit 21 enables the enable signal (ENB_N) in the period T2 in synchronization with the vertical synchronization signal (VSYNC). Further, within one vertical scanning period, an address signal (A [5: 0]) designates a fuse (FUSE) to be programmed one address at a time, and an adjustment value stored in the register 22 based on a write signal (PROGRAM). The newly written adjustment value (VCM [7: 0]) including is written to the adjustment value storage block.
That is, when the fuse element (FUSE) is blown, the write signal (PROGRAM) is set to “High” level, the NMOS transistor (NMS) is turned on, and when the fuse element (FUSE) is not blown, the write signal (PROGRAM) is turned on. ) Is set to the “Low” level, and the NMOS transistor (NMS) is turned off. In FIG. 12, the case where the fuse element (FUSE) is not melted is illustrated by a broken line.
In FIG. 12, the last bit (A in FIG. 12) of the 8-bit adjustment value is for programming one bit of the management information of the [7: 0] bits of the fuse memory element 20.

In the above description, the reference common voltage is the voltage VcomH and the voltage VcomH is adjusted by the electronic volume (R1). However, the reference common voltage is not necessarily the voltage VcomH. The reference common voltage may be, for example, VcomL voltage, or VcomH voltage that is intermediate between VcomH voltage and VcomL voltage. From these voltages, VcomH voltage, or VcomH voltage and VcomL voltage A voltage may be generated.
As described above, in this embodiment, the drive circuit (DRV) incorporates the electronic volume (R1) for adjusting the voltage of VcomH and the fuse memory element for storing the adjustment value. Parts (semi-fixed resistors) can be omitted. As a result, a space for mounting the external component (semi-fixed resistor) can be saved, and thus the size can be further reduced.
In this embodiment, since a fuse memory element which is an OTP (One-Time-Program) -ROM is used, the test cost does not increase as in the case of EP and EEP-ROM, so that the cost can be reduced. It becomes possible to plan.
Furthermore, in this embodiment, since the adjustment value can be written into the fuse memory element eight times, it is possible to cope with a case where the writing is missed.

In the above description, the case where the fuse memory element 20 is configured by a 64-bit storage cell has been described. However, the present invention is applied when the fuse memory element 20 is configured by a 64-bit or more multi-bit storage cell. Applicable.
In the above description, the case of adjusting the voltage of VcomH has been described. However, the individual difference of the liquid crystal display panel is adjusted by register setting using a driver built-in circuit, for example, the backlight and the liquid crystal display panel are adjusted. It is applicable to the case where the color adjustment at the time of combination is built in the driver and the individual differences of each liquid crystal display panel are absorbed without external parts by adjusting with a register.
Further, in place of the fuse memory element 20, it is also possible to use a memory element that can be read / written by address designation and whose output signal is digitized.
The present invention is not limited to a liquid crystal display device, and can be applied to a display device that periodically switches voltage levels.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

It is a block diagram which shows schematic structure of the liquid crystal display module of the Example of this invention. It is a figure which shows the subpixel structure of the liquid crystal display panel shown in FIG. FIG. 2 is a block diagram illustrating a schematic configuration of a drive circuit illustrated in FIG. 1. It is a circuit diagram which shows an example of a reference common voltage generation circuit. FIG. 4 is a block diagram illustrating an example of a common voltage adjustment memory circuit illustrated in FIG. 3. FIG. 6 is a circuit diagram showing an example of a configuration of one memory cell of the fuse memory element shown in FIG. 5. It is a figure which shows the structure of the memory cell of the fuse memory element of the Example of this invention. It is a circuit diagram which shows an example of the logic circuit for judging the adjustment value storage block which writes an adjustment value of the fuse memory element of the Example of this invention. 4 is a flowchart for explaining an operation of reading an adjustment value from a fuse memory element according to an embodiment of the present invention. 6 is a timing chart illustrating an example of an adjustment value read operation from the fuse memory element according to the embodiment of this invention. 6 is a flowchart for explaining an operation of writing an adjustment value to the fuse memory element according to the embodiment of the present invention. 5 is a timing chart illustrating an example of an operation of writing an adjustment value to the fuse memory element according to the embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Image data interface circuit 11 D / A conversion circuit 12 Scan line and video line drive circuit 13 Serial interface circuit (for control register circuit)
14 common voltage adjustment memory circuit 15 control register circuit 16 common voltage generation circuit 17 liquid crystal application voltage generation circuit 20 fuse memory element 21 control circuit 22,23 register 30 VcomL voltage generation circuit RES level shift circuit FUSE fuse element NMS NMOS transistor RSC Level sense circuit INB Inverter TFG Transfer gate circuit RCH Latch circuit PNL Liquid crystal panel DL Video line (source line or drain line)
GL scan line (or gate line)
TFT Thin film transistor PX Pixel electrode CT Counter electrode (common electrode or common electrode)
LC liquid crystal capacitor Cadd holding capacitor SUB1 first substrate DRV drive circuit FPC flexible wiring board R1 electronic volume R, R2 resistance element

Claims (6)

A plurality of pixels;
A display device comprising a drive circuit for driving the plurality of pixels,
Each of the pixels includes a pixel electrode;
A counter electrode facing the pixel electrode;
The drive circuit includes a common voltage generation circuit that inputs a common voltage to the counter electrode,
The common voltage generation circuit includes a reference common voltage generation circuit that generates a reference common voltage;
A memory circuit,
The reference common voltage generation circuit has an electronic volume for adjusting a reference common voltage,
The display device, wherein the memory circuit includes a fuse memory element having a plurality of storage cells and stores the adjustment value of the electronic volume. The memory circuit includes a fuse memory element having the plurality of storage cells;
A register for storing the adjustment value read from the fuse memory element, or for storing the adjustment value to be written to the fuse memory element;
The control circuit according to claim 1, further comprising: a control circuit that reads the adjustment value stored in the fuse memory element and stores the adjustment value in the register, or writes the adjustment value stored in the register into the fuse memory element. The display device described.   The fuse memory element includes m adjustment value storage blocks each including k-bit storage cells and one management information storage block including n-bit storage cells. Item 3. A display device according to item 1 or item 2.   The control circuit reads management information stored in the management information storage block, specifies the adjustment value storage block in which the latest adjustment value is written, and updates the latest adjustment value storage block from the specified adjustment value storage block. The adjustment value is read and stored in the register, or the management information stored in the management information storage block is read, the adjustment value storage block to which the new adjustment value is written is specified, and the register is stored in the register. The display device according to claim 3, wherein the stored new adjustment value is written in the specified adjustment value storage block.   The display device according to claim 1, wherein the reference common voltage is a high-level common voltage.   The display device according to claim 1, wherein the display device is a liquid crystal display device.

Images